95 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2# RUN: llc -mtriple riscv64 -mattr=+m,+v -target-abi=lp64 -start-before=prologepilog -o - \3# RUN: -verify-machineinstrs %s | FileCheck %s4--- |5 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"6 target triple = "riscv64"7 8 define void @spillslot() {9 ; CHECK-LABEL: spillslot:10 ; CHECK: # %bb.0:11 ; CHECK-NEXT: addi sp, sp, -203212 ; CHECK-NEXT: .cfi_def_cfa_offset 203213 ; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill14 ; CHECK-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill15 ; CHECK-NEXT: .cfi_offset ra, -816 ; CHECK-NEXT: .cfi_offset s0, -1617 ; CHECK-NEXT: addi s0, sp, 203218 ; CHECK-NEXT: .cfi_def_cfa s0, 019 ; CHECK-NEXT: addi sp, sp, -27220 ; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill21 ; CHECK-NEXT: csrr a0, vlenb22 ; CHECK-NEXT: sd a1, 0(sp) # 8-byte Folded Spill23 ; CHECK-NEXT: li a1, 324 ; CHECK-NEXT: slli a1, a1, 1025 ; CHECK-NEXT: mul a0, a0, a126 ; CHECK-NEXT: ld a1, 0(sp) # 8-byte Folded Reload27 ; CHECK-NEXT: sub sp, sp, a028 ; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload29 ; CHECK-NEXT: andi sp, sp, -12830 ; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill31 ; CHECK-NEXT: addi a0, sp, 204732 ; CHECK-NEXT: addi a0, a0, 24133 ; CHECK-NEXT: vs1r.v v25, (a0) # vscale x 8-byte Folded Spill34 ; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload35 ; CHECK-NEXT: call spillslot36 ; CHECK-NEXT: addi sp, s0, -203237 ; CHECK-NEXT: .cfi_def_cfa sp, 203238 ; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload39 ; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload40 ; CHECK-NEXT: .cfi_restore ra41 ; CHECK-NEXT: .cfi_restore s042 ; CHECK-NEXT: addi sp, sp, 203243 ; CHECK-NEXT: .cfi_def_cfa_offset 044 ; CHECK-NEXT: ret45 ret void46 }47 48...49---50name: spillslot51alignment: 452tracksRegLiveness: false53frameInfo:54 isFrameAddressTaken: false55 isReturnAddressTaken: false56 hasStackMap: false57 hasPatchPoint: false58 stackSize: 059 offsetAdjustment: 060 maxAlignment: 12861 adjustsStack: false62 hasCalls: false63 stackProtector: ''64 maxCallFrameSize: 429496729565 cvBytesOfCalleeSavedRegisters: 066 hasOpaqueSPAdjustment: false67 hasVAStart: false68 hasMustTailInVarArgFunc: false69 hasTailCall: false70 localFrameSize: 071 savePoint: []72 restorePoint: []73fixedStack: []74stack:75 - { id: 0, name: '', type: default, offset: 0, size: 2048, alignment: 128,76 stack-id: default, callee-saved-register: '', callee-saved-restored: true,77 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }78 - { id: 1, name: '', type: spill-slot, offset: 0, size: 24576, alignment: 8,79 stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,80 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }81body: |82 bb.0:83 liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31, $v2584 85 VS1R_V killed renamable $v25, %stack.1 :: (store (<vscale x 1 x s64>) into %stack.1, align 8)86 ; This is here just to make all the eligible registers live at this point.87 ; This way when we replace the frame index %stack.1 with its actual address88 ; we have to allocate two virtual registers to compute it.89 ; A later run of the the register scavenger won't find available registers90 ; either so it will have to spill two to the emergency spill slots91 ; required for this RVV computation.92 PseudoCALL target-flags(riscv-call) @spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x3193 PseudoRET94...95