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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s4 5; Check that we are able to legalize scalable-vector loads that require widening.6 7define <vscale x 3 x i8> @load_nxv3i8(ptr %ptr) {8; CHECK-LABEL: load_nxv3i8:9; CHECK: # %bb.0:10; CHECK-NEXT: csrr a1, vlenb11; CHECK-NEXT: srli a2, a1, 312; CHECK-NEXT: srli a1, a1, 213; CHECK-NEXT: add a1, a1, a214; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma15; CHECK-NEXT: vle8.v v8, (a0)16; CHECK-NEXT: ret17 %v = load <vscale x 3 x i8>, ptr %ptr18 ret <vscale x 3 x i8> %v19}20 21define <vscale x 5 x half> @load_nxv5f16(ptr %ptr) {22; CHECK-LABEL: load_nxv5f16:23; CHECK: # %bb.0:24; CHECK-NEXT: csrr a1, vlenb25; CHECK-NEXT: srli a2, a1, 326; CHECK-NEXT: srli a1, a1, 127; CHECK-NEXT: add a1, a1, a228; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma29; CHECK-NEXT: vle16.v v8, (a0)30; CHECK-NEXT: ret31 %v = load <vscale x 5 x half>, ptr %ptr32 ret <vscale x 5 x half> %v33}34 35define <vscale x 7 x half> @load_nxv7f16(ptr %ptr, ptr %out) {36; CHECK-LABEL: load_nxv7f16:37; CHECK: # %bb.0:38; CHECK-NEXT: csrr a2, vlenb39; CHECK-NEXT: srli a3, a2, 340; CHECK-NEXT: sub a2, a2, a341; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma42; CHECK-NEXT: vle16.v v8, (a0)43; CHECK-NEXT: vse16.v v8, (a1)44; CHECK-NEXT: ret45 %v = load <vscale x 7 x half>, ptr %ptr46 store <vscale x 7 x half> %v, ptr %out47 ret <vscale x 7 x half> %v48}49