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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s4 5; Check that we are able to legalize scalable-vector stores that require widening.6 7define void @store_nxv3i8(<vscale x 3 x i8> %val, ptr %ptr) {8; CHECK-LABEL: store_nxv3i8:9; CHECK: # %bb.0:10; CHECK-NEXT: csrr a1, vlenb11; CHECK-NEXT: srli a2, a1, 312; CHECK-NEXT: srli a1, a1, 213; CHECK-NEXT: add a1, a1, a214; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma15; CHECK-NEXT: vse8.v v8, (a0)16; CHECK-NEXT: ret17 store <vscale x 3 x i8> %val, ptr %ptr18 ret void19}20 21define void @store_nxv7f64(<vscale x 7 x double> %val, ptr %ptr) {22; CHECK-LABEL: store_nxv7f64:23; CHECK: # %bb.0:24; CHECK-NEXT: csrr a1, vlenb25; CHECK-NEXT: srli a2, a1, 326; CHECK-NEXT: sub a1, a1, a227; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma28; CHECK-NEXT: vse64.v v8, (a0)29; CHECK-NEXT: ret30 store <vscale x 7 x double> %val, ptr %ptr31 ret void32}33