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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f32(<vscale x 1 x float> %x) {8; CHECK-LABEL: llrint_nxv1i64_nxv1f32:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma11; CHECK-NEXT: vfwcvt.x.f.v v9, v812; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14 %a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f32(<vscale x 1 x float> %x)15 ret <vscale x 1 x i64> %a16}17 18define <vscale x 2 x i64> @llrint_nxv2i64_nxv2f32(<vscale x 2 x float> %x) {19; CHECK-LABEL: llrint_nxv2i64_nxv2f32:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma22; CHECK-NEXT: vmv1r.v v10, v823; CHECK-NEXT: vfwcvt.x.f.v v8, v1024; CHECK-NEXT: ret25 %a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f32(<vscale x 2 x float> %x)26 ret <vscale x 2 x i64> %a27}28 29define <vscale x 4 x i64> @llrint_nxv4i64_nxv4f32(<vscale x 4 x float> %x) {30; CHECK-LABEL: llrint_nxv4i64_nxv4f32:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma33; CHECK-NEXT: vmv2r.v v12, v834; CHECK-NEXT: vfwcvt.x.f.v v8, v1235; CHECK-NEXT: ret36 %a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f32(<vscale x 4 x float> %x)37 ret <vscale x 4 x i64> %a38}39 40define <vscale x 8 x i64> @llrint_nxv8i64_nxv8f32(<vscale x 8 x float> %x) {41; CHECK-LABEL: llrint_nxv8i64_nxv8f32:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma44; CHECK-NEXT: vmv4r.v v16, v845; CHECK-NEXT: vfwcvt.x.f.v v8, v1646; CHECK-NEXT: ret47 %a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f32(<vscale x 8 x float> %x)48 ret <vscale x 8 x i64> %a49}50 51define <vscale x 16 x i64> @llrint_nxv16i64_nxv16f32(<vscale x 16 x float> %x) {52; CHECK-LABEL: llrint_nxv16i64_nxv16f32:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma55; CHECK-NEXT: vfwcvt.x.f.v v24, v856; CHECK-NEXT: vfwcvt.x.f.v v16, v1257; CHECK-NEXT: vmv8r.v v8, v2458; CHECK-NEXT: ret59 %a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f32(<vscale x 16 x float> %x)60 ret <vscale x 16 x i64> %a61}62 63define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f64(<vscale x 1 x double> %x) {64; CHECK-LABEL: llrint_nxv1i64_nxv1f64:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma67; CHECK-NEXT: vfcvt.x.f.v v8, v868; CHECK-NEXT: ret69 %a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f64(<vscale x 1 x double> %x)70 ret <vscale x 1 x i64> %a71}72 73define <vscale x 2 x i64> @llrint_nxv2i64_nxv2f64(<vscale x 2 x double> %x) {74; CHECK-LABEL: llrint_nxv2i64_nxv2f64:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma77; CHECK-NEXT: vfcvt.x.f.v v8, v878; CHECK-NEXT: ret79 %a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f64(<vscale x 2 x double> %x)80 ret <vscale x 2 x i64> %a81}82 83define <vscale x 4 x i64> @llrint_nxv4i64_nxv4f64(<vscale x 4 x double> %x) {84; CHECK-LABEL: llrint_nxv4i64_nxv4f64:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma87; CHECK-NEXT: vfcvt.x.f.v v8, v888; CHECK-NEXT: ret89 %a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double> %x)90 ret <vscale x 4 x i64> %a91}92 93define <vscale x 8 x i64> @llrint_nxv8i64_nxv8f64(<vscale x 8 x double> %x) {94; CHECK-LABEL: llrint_nxv8i64_nxv8f64:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma97; CHECK-NEXT: vfcvt.x.f.v v8, v898; CHECK-NEXT: ret99 %a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f64(<vscale x 8 x double> %x)100 ret <vscale x 8 x i64> %a101}102 103define <vscale x 1 x i64> @llrint_nxv1f16(<vscale x 1 x half> %x) {104; CHECK-LABEL: llrint_nxv1f16:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma107; CHECK-NEXT: vfwcvt.f.f.v v9, v8108; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma109; CHECK-NEXT: vfwcvt.x.f.v v8, v9110; CHECK-NEXT: ret111 %a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f16(<vscale x 1 x half> %x)112 ret <vscale x 1 x i64> %a113}114 115define <vscale x 2 x i64> @llrint_nxv2f16(<vscale x 2 x half> %x) {116; CHECK-LABEL: llrint_nxv2f16:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma119; CHECK-NEXT: vfwcvt.f.f.v v10, v8120; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma121; CHECK-NEXT: vfwcvt.x.f.v v8, v10122; CHECK-NEXT: ret123 %a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f16(<vscale x 2 x half> %x)124 ret <vscale x 2 x i64> %a125}126 127define <vscale x 4 x i64> @llrint_nxv4f16(<vscale x 4 x half> %x) {128; CHECK-LABEL: llrint_nxv4f16:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma131; CHECK-NEXT: vfwcvt.f.f.v v12, v8132; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma133; CHECK-NEXT: vfwcvt.x.f.v v8, v12134; CHECK-NEXT: ret135 %a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f16(<vscale x 4 x half> %x)136 ret <vscale x 4 x i64> %a137}138 139define <vscale x 8 x i64> @llrint_nxv8f16(<vscale x 8 x half> %x) {140; CHECK-LABEL: llrint_nxv8f16:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma143; CHECK-NEXT: vfwcvt.f.f.v v16, v8144; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma145; CHECK-NEXT: vfwcvt.x.f.v v8, v16146; CHECK-NEXT: ret147 %a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f16(<vscale x 8 x half> %x)148 ret <vscale x 8 x i64> %a149}150 151define <vscale x 16 x i64> @llrint_nxv16f16(<vscale x 16 x half> %x) {152; CHECK-LABEL: llrint_nxv16f16:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma155; CHECK-NEXT: vfwcvt.f.f.v v16, v8156; CHECK-NEXT: vfwcvt.f.f.v v24, v10157; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma158; CHECK-NEXT: vfwcvt.x.f.v v8, v16159; CHECK-NEXT: vfwcvt.x.f.v v16, v24160; CHECK-NEXT: ret161 %a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f16(<vscale x 16 x half> %x)162 ret <vscale x 16 x i64> %a163}164 165define <vscale x 1 x i64> @llrint_nxv1bf16(<vscale x 1 x bfloat> %x) {166; CHECK-LABEL: llrint_nxv1bf16:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma169; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8170; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma171; CHECK-NEXT: vfwcvt.x.f.v v8, v9172; CHECK-NEXT: ret173 %a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1bf16(<vscale x 1 x bfloat> %x)174 ret <vscale x 1 x i64> %a175}176 177define <vscale x 2 x i64> @llrint_nxv2bf16(<vscale x 2 x bfloat> %x) {178; CHECK-LABEL: llrint_nxv2bf16:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma181; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8182; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma183; CHECK-NEXT: vfwcvt.x.f.v v8, v10184; CHECK-NEXT: ret185 %a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2bf16(<vscale x 2 x bfloat> %x)186 ret <vscale x 2 x i64> %a187}188 189define <vscale x 4 x i64> @llrint_nxv4bf16(<vscale x 4 x bfloat> %x) {190; CHECK-LABEL: llrint_nxv4bf16:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma193; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8194; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma195; CHECK-NEXT: vfwcvt.x.f.v v8, v12196; CHECK-NEXT: ret197 %a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4bf16(<vscale x 4 x bfloat> %x)198 ret <vscale x 4 x i64> %a199}200 201define <vscale x 8 x i64> @llrint_nxv8bf16(<vscale x 8 x bfloat> %x) {202; CHECK-LABEL: llrint_nxv8bf16:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma205; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8206; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma207; CHECK-NEXT: vfwcvt.x.f.v v8, v16208; CHECK-NEXT: ret209 %a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8bf16(<vscale x 8 x bfloat> %x)210 ret <vscale x 8 x i64> %a211}212 213define <vscale x 16 x i64> @llrint_nxv16bf16(<vscale x 16 x bfloat> %x) {214; CHECK-LABEL: llrint_nxv16bf16:215; CHECK: # %bb.0:216; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma217; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8218; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v10219; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma220; CHECK-NEXT: vfwcvt.x.f.v v8, v16221; CHECK-NEXT: vfwcvt.x.f.v v16, v24222; CHECK-NEXT: ret223 %a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16bf16(<vscale x 16 x bfloat> %x)224 ret <vscale x 16 x i64> %a225}226