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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+f,+d -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f32(<vscale x 1 x float> %x, <vscale x 1 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: llrint_nxv1i64_nxv1f32:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma11; CHECK-NEXT: vfwcvt.x.f.v v9, v8, v0.t12; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14 %a = call <vscale x 1 x i64> @llvm.vp.llrint.nxv1i64.nxv1f32(<vscale x 1 x float> %x, <vscale x 1 x i1> %m, i32 %evl)15 ret <vscale x 1 x i64> %a16}17 18define <vscale x 2 x i64> @llrint_nxv2i64_nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {19; CHECK-LABEL: llrint_nxv2i64_nxv2f32:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma22; CHECK-NEXT: vmv1r.v v10, v823; CHECK-NEXT: vfwcvt.x.f.v v8, v10, v0.t24; CHECK-NEXT: ret25 %a = call <vscale x 2 x i64> @llvm.vp.llrint.nxv2i64.nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 %evl)26 ret <vscale x 2 x i64> %a27}28 29define <vscale x 4 x i64> @llrint_nxv4i64_nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {30; CHECK-LABEL: llrint_nxv4i64_nxv4f32:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma33; CHECK-NEXT: vmv2r.v v12, v834; CHECK-NEXT: vfwcvt.x.f.v v8, v12, v0.t35; CHECK-NEXT: ret36 %a = call <vscale x 4 x i64> @llvm.vp.llrint.nxv4i64.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 %evl)37 ret <vscale x 4 x i64> %a38}39 40define <vscale x 8 x i64> @llrint_nxv8i64_nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {41; CHECK-LABEL: llrint_nxv8i64_nxv8f32:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma44; CHECK-NEXT: vmv4r.v v16, v845; CHECK-NEXT: vfwcvt.x.f.v v8, v16, v0.t46; CHECK-NEXT: ret47 %a = call <vscale x 8 x i64> @llvm.vp.llrint.nxv8i64.nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 %evl)48 ret <vscale x 8 x i64> %a49}50 51define <vscale x 16 x i64> @llrint_nxv16i64_nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 zeroext %evl) {52; CHECK-LABEL: llrint_nxv16i64_nxv16f32:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma55; CHECK-NEXT: vmv1r.v v24, v056; CHECK-NEXT: csrr a1, vlenb57; CHECK-NEXT: srli a2, a1, 358; CHECK-NEXT: sub a3, a0, a159; CHECK-NEXT: vslidedown.vx v0, v0, a260; CHECK-NEXT: sltu a2, a0, a361; CHECK-NEXT: addi a2, a2, -162; CHECK-NEXT: and a2, a2, a363; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma64; CHECK-NEXT: vfwcvt.x.f.v v16, v12, v0.t65; CHECK-NEXT: bltu a0, a1, .LBB4_266; CHECK-NEXT: # %bb.1:67; CHECK-NEXT: mv a0, a168; CHECK-NEXT: .LBB4_2:69; CHECK-NEXT: vmv1r.v v0, v2470; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma71; CHECK-NEXT: vfwcvt.x.f.v v24, v8, v0.t72; CHECK-NEXT: vmv8r.v v8, v2473; CHECK-NEXT: ret74 %a = call <vscale x 16 x i64> @llvm.vp.llrint.nxv16i64.nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 %evl)75 ret <vscale x 16 x i64> %a76}77 78define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x i1> %m, i32 zeroext %evl) {79; CHECK-LABEL: llrint_nxv1i64_nxv1f64:80; CHECK: # %bb.0:81; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma82; CHECK-NEXT: vfcvt.x.f.v v8, v8, v0.t83; CHECK-NEXT: ret84 %a = call <vscale x 1 x i64> @llvm.vp.llrint.nxv1i64.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x i1> %m, i32 %evl)85 ret <vscale x 1 x i64> %a86}87 88define <vscale x 2 x i64> @llrint_nxv2i64_nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {89; CHECK-LABEL: llrint_nxv2i64_nxv2f64:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma92; CHECK-NEXT: vfcvt.x.f.v v8, v8, v0.t93; CHECK-NEXT: ret94 %a = call <vscale x 2 x i64> @llvm.vp.llrint.nxv2i64.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 %evl)95 ret <vscale x 2 x i64> %a96}97 98define <vscale x 4 x i64> @llrint_nxv4i64_nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {99; CHECK-LABEL: llrint_nxv4i64_nxv4f64:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma102; CHECK-NEXT: vfcvt.x.f.v v8, v8, v0.t103; CHECK-NEXT: ret104 %a = call <vscale x 4 x i64> @llvm.vp.llrint.nxv4i64.nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 %evl)105 ret <vscale x 4 x i64> %a106}107 108define <vscale x 8 x i64> @llrint_nxv8i64_nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {109; CHECK-LABEL: llrint_nxv8i64_nxv8f64:110; CHECK: # %bb.0:111; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma112; CHECK-NEXT: vfcvt.x.f.v v8, v8, v0.t113; CHECK-NEXT: ret114 %a = call <vscale x 8 x i64> @llvm.vp.llrint.nxv8i64.nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 %evl)115 ret <vscale x 8 x i64> %a116}117