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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <vscale x 1 x i64> @llround_nxv1i64_nxv1f32(<vscale x 1 x float> %x) {8; CHECK-LABEL: llround_nxv1i64_nxv1f32:9; CHECK: # %bb.0:10; CHECK-NEXT: fsrmi a0, 411; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma12; CHECK-NEXT: vfwcvt.x.f.v v9, v813; CHECK-NEXT: fsrm a014; CHECK-NEXT: vmv1r.v v8, v915; CHECK-NEXT: ret16 %a = call <vscale x 1 x i64> @llvm.llround.nxv1i64.nxv1f32(<vscale x 1 x float> %x)17 ret <vscale x 1 x i64> %a18}19 20define <vscale x 2 x i64> @llround_nxv2i64_nxv2f32(<vscale x 2 x float> %x) {21; CHECK-LABEL: llround_nxv2i64_nxv2f32:22; CHECK: # %bb.0:23; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma24; CHECK-NEXT: vmv1r.v v10, v825; CHECK-NEXT: fsrmi a0, 426; CHECK-NEXT: vfwcvt.x.f.v v8, v1027; CHECK-NEXT: fsrm a028; CHECK-NEXT: ret29 %a = call <vscale x 2 x i64> @llvm.llround.nxv2i64.nxv2f32(<vscale x 2 x float> %x)30 ret <vscale x 2 x i64> %a31}32 33define <vscale x 4 x i64> @llround_nxv4i64_nxv4f32(<vscale x 4 x float> %x) {34; CHECK-LABEL: llround_nxv4i64_nxv4f32:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma37; CHECK-NEXT: vmv2r.v v12, v838; CHECK-NEXT: fsrmi a0, 439; CHECK-NEXT: vfwcvt.x.f.v v8, v1240; CHECK-NEXT: fsrm a041; CHECK-NEXT: ret42 %a = call <vscale x 4 x i64> @llvm.llround.nxv4i64.nxv4f32(<vscale x 4 x float> %x)43 ret <vscale x 4 x i64> %a44}45 46define <vscale x 8 x i64> @llround_nxv8i64_nxv8f32(<vscale x 8 x float> %x) {47; CHECK-LABEL: llround_nxv8i64_nxv8f32:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma50; CHECK-NEXT: vmv4r.v v16, v851; CHECK-NEXT: fsrmi a0, 452; CHECK-NEXT: vfwcvt.x.f.v v8, v1653; CHECK-NEXT: fsrm a054; CHECK-NEXT: ret55 %a = call <vscale x 8 x i64> @llvm.llround.nxv8i64.nxv8f32(<vscale x 8 x float> %x)56 ret <vscale x 8 x i64> %a57}58 59define <vscale x 16 x i64> @llround_nxv16i64_nxv16f32(<vscale x 16 x float> %x) {60; CHECK-LABEL: llround_nxv16i64_nxv16f32:61; CHECK: # %bb.0:62; CHECK-NEXT: fsrmi a0, 463; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma64; CHECK-NEXT: vfwcvt.x.f.v v24, v865; CHECK-NEXT: vfwcvt.x.f.v v16, v1266; CHECK-NEXT: fsrm a067; CHECK-NEXT: vmv8r.v v8, v2468; CHECK-NEXT: ret69 %a = call <vscale x 16 x i64> @llvm.llround.nxv16i64.nxv16f32(<vscale x 16 x float> %x)70 ret <vscale x 16 x i64> %a71}72 73define <vscale x 1 x i64> @llround_nxv1i64_nxv1f64(<vscale x 1 x double> %x) {74; CHECK-LABEL: llround_nxv1i64_nxv1f64:75; CHECK: # %bb.0:76; CHECK-NEXT: fsrmi a0, 477; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma78; CHECK-NEXT: vfcvt.x.f.v v8, v879; CHECK-NEXT: fsrm a080; CHECK-NEXT: ret81 %a = call <vscale x 1 x i64> @llvm.llround.nxv1i64.nxv1f64(<vscale x 1 x double> %x)82 ret <vscale x 1 x i64> %a83}84 85define <vscale x 2 x i64> @llround_nxv2i64_nxv2f64(<vscale x 2 x double> %x) {86; CHECK-LABEL: llround_nxv2i64_nxv2f64:87; CHECK: # %bb.0:88; CHECK-NEXT: fsrmi a0, 489; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma90; CHECK-NEXT: vfcvt.x.f.v v8, v891; CHECK-NEXT: fsrm a092; CHECK-NEXT: ret93 %a = call <vscale x 2 x i64> @llvm.llround.nxv2i64.nxv2f64(<vscale x 2 x double> %x)94 ret <vscale x 2 x i64> %a95}96 97define <vscale x 4 x i64> @llround_nxv4i64_nxv4f64(<vscale x 4 x double> %x) {98; CHECK-LABEL: llround_nxv4i64_nxv4f64:99; CHECK: # %bb.0:100; CHECK-NEXT: fsrmi a0, 4101; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma102; CHECK-NEXT: vfcvt.x.f.v v8, v8103; CHECK-NEXT: fsrm a0104; CHECK-NEXT: ret105 %a = call <vscale x 4 x i64> @llvm.llround.nxv4i64.nxv4f64(<vscale x 4 x double> %x)106 ret <vscale x 4 x i64> %a107}108 109define <vscale x 8 x i64> @llround_nxv8i64_nxv8f64(<vscale x 8 x double> %x) {110; CHECK-LABEL: llround_nxv8i64_nxv8f64:111; CHECK: # %bb.0:112; CHECK-NEXT: fsrmi a0, 4113; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma114; CHECK-NEXT: vfcvt.x.f.v v8, v8115; CHECK-NEXT: fsrm a0116; CHECK-NEXT: ret117 %a = call <vscale x 8 x i64> @llvm.llround.nxv8i64.nxv8f64(<vscale x 8 x double> %x)118 ret <vscale x 8 x i64> %a119}120 121define <vscale x 1 x i64> @llround_nxv1f16(<vscale x 1 x half> %x) {122; CHECK-LABEL: llround_nxv1f16:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma125; CHECK-NEXT: vfwcvt.f.f.v v9, v8126; CHECK-NEXT: fsrmi a0, 4127; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma128; CHECK-NEXT: vfwcvt.x.f.v v8, v9129; CHECK-NEXT: fsrm a0130; CHECK-NEXT: ret131 %a = call <vscale x 1 x i64> @llvm.llround.nxv1i64.nxv1f16(<vscale x 1 x half> %x)132 ret <vscale x 1 x i64> %a133}134 135define <vscale x 2 x i64> @llround_nxv2f16(<vscale x 2 x half> %x) {136; CHECK-LABEL: llround_nxv2f16:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma139; CHECK-NEXT: vfwcvt.f.f.v v10, v8140; CHECK-NEXT: fsrmi a0, 4141; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma142; CHECK-NEXT: vfwcvt.x.f.v v8, v10143; CHECK-NEXT: fsrm a0144; CHECK-NEXT: ret145 %a = call <vscale x 2 x i64> @llvm.llround.nxv2i64.nxv2f16(<vscale x 2 x half> %x)146 ret <vscale x 2 x i64> %a147}148 149define <vscale x 4 x i64> @llround_nxv4f16(<vscale x 4 x half> %x) {150; CHECK-LABEL: llround_nxv4f16:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma153; CHECK-NEXT: vfwcvt.f.f.v v12, v8154; CHECK-NEXT: fsrmi a0, 4155; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma156; CHECK-NEXT: vfwcvt.x.f.v v8, v12157; CHECK-NEXT: fsrm a0158; CHECK-NEXT: ret159 %a = call <vscale x 4 x i64> @llvm.llround.nxv4i64.nxv4f16(<vscale x 4 x half> %x)160 ret <vscale x 4 x i64> %a161}162 163define <vscale x 8 x i64> @llround_nxv8f16(<vscale x 8 x half> %x) {164; CHECK-LABEL: llround_nxv8f16:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma167; CHECK-NEXT: vfwcvt.f.f.v v16, v8168; CHECK-NEXT: fsrmi a0, 4169; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma170; CHECK-NEXT: vfwcvt.x.f.v v8, v16171; CHECK-NEXT: fsrm a0172; CHECK-NEXT: ret173 %a = call <vscale x 8 x i64> @llvm.llround.nxv8i64.nxv8f16(<vscale x 8 x half> %x)174 ret <vscale x 8 x i64> %a175}176 177define <vscale x 16 x i64> @llround_nxv16f16(<vscale x 16 x half> %x) {178; CHECK-LABEL: llround_nxv16f16:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma181; CHECK-NEXT: vfwcvt.f.f.v v16, v8182; CHECK-NEXT: fsrmi a0, 4183; CHECK-NEXT: vfwcvt.f.f.v v24, v10184; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma185; CHECK-NEXT: vfwcvt.x.f.v v8, v16186; CHECK-NEXT: vfwcvt.x.f.v v16, v24187; CHECK-NEXT: fsrm a0188; CHECK-NEXT: ret189 %a = call <vscale x 16 x i64> @llvm.llround.nxv16i64.nxv16f16(<vscale x 16 x half> %x)190 ret <vscale x 16 x i64> %a191}192 193define <vscale x 1 x i64> @llround_nxv1bf16(<vscale x 1 x bfloat> %x) {194; CHECK-LABEL: llround_nxv1bf16:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma197; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8198; CHECK-NEXT: fsrmi a0, 4199; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma200; CHECK-NEXT: vfwcvt.x.f.v v8, v9201; CHECK-NEXT: fsrm a0202; CHECK-NEXT: ret203 %a = call <vscale x 1 x i64> @llvm.llround.nxv1i64.nxv1bf16(<vscale x 1 x bfloat> %x)204 ret <vscale x 1 x i64> %a205}206 207define <vscale x 2 x i64> @llround_nxv2bf16(<vscale x 2 x bfloat> %x) {208; CHECK-LABEL: llround_nxv2bf16:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma211; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8212; CHECK-NEXT: fsrmi a0, 4213; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma214; CHECK-NEXT: vfwcvt.x.f.v v8, v10215; CHECK-NEXT: fsrm a0216; CHECK-NEXT: ret217 %a = call <vscale x 2 x i64> @llvm.llround.nxv2i64.nxv2bf16(<vscale x 2 x bfloat> %x)218 ret <vscale x 2 x i64> %a219}220 221define <vscale x 4 x i64> @llround_nxv4bf16(<vscale x 4 x bfloat> %x) {222; CHECK-LABEL: llround_nxv4bf16:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma225; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8226; CHECK-NEXT: fsrmi a0, 4227; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma228; CHECK-NEXT: vfwcvt.x.f.v v8, v12229; CHECK-NEXT: fsrm a0230; CHECK-NEXT: ret231 %a = call <vscale x 4 x i64> @llvm.llround.nxv4i64.nxv4bf16(<vscale x 4 x bfloat> %x)232 ret <vscale x 4 x i64> %a233}234 235define <vscale x 8 x i64> @llround_nxv8bf16(<vscale x 8 x bfloat> %x) {236; CHECK-LABEL: llround_nxv8bf16:237; CHECK: # %bb.0:238; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma239; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8240; CHECK-NEXT: fsrmi a0, 4241; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma242; CHECK-NEXT: vfwcvt.x.f.v v8, v16243; CHECK-NEXT: fsrm a0244; CHECK-NEXT: ret245 %a = call <vscale x 8 x i64> @llvm.llround.nxv8i64.nxv8bf16(<vscale x 8 x bfloat> %x)246 ret <vscale x 8 x i64> %a247}248 249define <vscale x 16 x i64> @llround_nxv16bf16(<vscale x 16 x bfloat> %x) {250; CHECK-LABEL: llround_nxv16bf16:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma253; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8254; CHECK-NEXT: fsrmi a0, 4255; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v10256; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma257; CHECK-NEXT: vfwcvt.x.f.v v8, v16258; CHECK-NEXT: vfwcvt.x.f.v v16, v24259; CHECK-NEXT: fsrm a0260; CHECK-NEXT: ret261 %a = call <vscale x 16 x i64> @llvm.llround.nxv16i64.nxv16bf16(<vscale x 16 x bfloat> %x)262 ret <vscale x 16 x i64> %a263}264