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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple riscv32 -mattr=+v %s -o - \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: llc -mtriple riscv64 -mattr=+v %s -o - \5; RUN: -verify-machineinstrs | FileCheck %s6 7define void @vadd_vint8m1(ptr %pc, ptr %pa, ptr %pb) nounwind {8; CHECK-LABEL: vadd_vint8m1:9; CHECK: # %bb.0:10; CHECK-NEXT: vl1r.v v8, (a1)11; CHECK-NEXT: vl1r.v v9, (a2)12; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma13; CHECK-NEXT: vadd.vv v8, v8, v914; CHECK-NEXT: vs1r.v v8, (a0)15; CHECK-NEXT: ret16 %va = load <vscale x 8 x i8>, ptr %pa17 %vb = load <vscale x 8 x i8>, ptr %pb18 %vc = add <vscale x 8 x i8> %va, %vb19 store <vscale x 8 x i8> %vc, ptr %pc20 ret void21}22 23define void @vadd_vint8m2(ptr %pc, ptr %pa, ptr %pb) nounwind {24; CHECK-LABEL: vadd_vint8m2:25; CHECK: # %bb.0:26; CHECK-NEXT: vl2r.v v8, (a1)27; CHECK-NEXT: vl2r.v v10, (a2)28; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma29; CHECK-NEXT: vadd.vv v8, v8, v1030; CHECK-NEXT: vs2r.v v8, (a0)31; CHECK-NEXT: ret32 %va = load <vscale x 16 x i8>, ptr %pa33 %vb = load <vscale x 16 x i8>, ptr %pb34 %vc = add <vscale x 16 x i8> %va, %vb35 store <vscale x 16 x i8> %vc, ptr %pc36 ret void37}38 39define void @vadd_vint8m4(ptr %pc, ptr %pa, ptr %pb) nounwind {40; CHECK-LABEL: vadd_vint8m4:41; CHECK: # %bb.0:42; CHECK-NEXT: vl4r.v v8, (a1)43; CHECK-NEXT: vl4r.v v12, (a2)44; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma45; CHECK-NEXT: vadd.vv v8, v8, v1246; CHECK-NEXT: vs4r.v v8, (a0)47; CHECK-NEXT: ret48 %va = load <vscale x 32 x i8>, ptr %pa49 %vb = load <vscale x 32 x i8>, ptr %pb50 %vc = add <vscale x 32 x i8> %va, %vb51 store <vscale x 32 x i8> %vc, ptr %pc52 ret void53}54 55define void @vadd_vint8m8(ptr %pc, ptr %pa, ptr %pb) nounwind {56; CHECK-LABEL: vadd_vint8m8:57; CHECK: # %bb.0:58; CHECK-NEXT: vl8r.v v8, (a1)59; CHECK-NEXT: vl8r.v v16, (a2)60; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma61; CHECK-NEXT: vadd.vv v8, v8, v1662; CHECK-NEXT: vs8r.v v8, (a0)63; CHECK-NEXT: ret64 %va = load <vscale x 64 x i8>, ptr %pa65 %vb = load <vscale x 64 x i8>, ptr %pb66 %vc = add <vscale x 64 x i8> %va, %vb67 store <vscale x 64 x i8> %vc, ptr %pc68 ret void69}70 71define void @vadd_vint8mf2(ptr %pc, ptr %pa, ptr %pb) nounwind {72; CHECK-LABEL: vadd_vint8mf2:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma75; CHECK-NEXT: vle8.v v8, (a1)76; CHECK-NEXT: vle8.v v9, (a2)77; CHECK-NEXT: vadd.vv v8, v8, v978; CHECK-NEXT: vse8.v v8, (a0)79; CHECK-NEXT: ret80 %va = load <vscale x 4 x i8>, ptr %pa81 %vb = load <vscale x 4 x i8>, ptr %pb82 %vc = add <vscale x 4 x i8> %va, %vb83 store <vscale x 4 x i8> %vc, ptr %pc84 ret void85}86 87define void @vadd_vint8mf4(ptr %pc, ptr %pa, ptr %pb) nounwind {88; CHECK-LABEL: vadd_vint8mf4:89; CHECK: # %bb.0:90; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma91; CHECK-NEXT: vle8.v v8, (a1)92; CHECK-NEXT: vle8.v v9, (a2)93; CHECK-NEXT: vadd.vv v8, v8, v994; CHECK-NEXT: vse8.v v8, (a0)95; CHECK-NEXT: ret96 %va = load <vscale x 2 x i8>, ptr %pa97 %vb = load <vscale x 2 x i8>, ptr %pb98 %vc = add <vscale x 2 x i8> %va, %vb99 store <vscale x 2 x i8> %vc, ptr %pc100 ret void101}102 103define void @vadd_vint8mf8(ptr %pc, ptr %pa, ptr %pb) nounwind {104; CHECK-LABEL: vadd_vint8mf8:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a3, zero, e8, mf8, ta, ma107; CHECK-NEXT: vle8.v v8, (a1)108; CHECK-NEXT: vle8.v v9, (a2)109; CHECK-NEXT: vadd.vv v8, v8, v9110; CHECK-NEXT: vse8.v v8, (a0)111; CHECK-NEXT: ret112 %va = load <vscale x 1 x i8>, ptr %pa113 %vb = load <vscale x 1 x i8>, ptr %pb114 %vc = add <vscale x 1 x i8> %va, %vb115 store <vscale x 1 x i8> %vc, ptr %pc116 ret void117}118 119define void @vadd_vint16m1(ptr %pc, ptr %pa, ptr %pb) nounwind {120; CHECK-LABEL: vadd_vint16m1:121; CHECK: # %bb.0:122; CHECK-NEXT: vl1re16.v v8, (a1)123; CHECK-NEXT: vl1re16.v v9, (a2)124; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma125; CHECK-NEXT: vadd.vv v8, v8, v9126; CHECK-NEXT: vs1r.v v8, (a0)127; CHECK-NEXT: ret128 %va = load <vscale x 4 x i16>, ptr %pa129 %vb = load <vscale x 4 x i16>, ptr %pb130 %vc = add <vscale x 4 x i16> %va, %vb131 store <vscale x 4 x i16> %vc, ptr %pc132 ret void133}134 135define void @vadd_vint16m2(ptr %pc, ptr %pa, ptr %pb) nounwind {136; CHECK-LABEL: vadd_vint16m2:137; CHECK: # %bb.0:138; CHECK-NEXT: vl2re16.v v8, (a1)139; CHECK-NEXT: vl2re16.v v10, (a2)140; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma141; CHECK-NEXT: vadd.vv v8, v8, v10142; CHECK-NEXT: vs2r.v v8, (a0)143; CHECK-NEXT: ret144 %va = load <vscale x 8 x i16>, ptr %pa145 %vb = load <vscale x 8 x i16>, ptr %pb146 %vc = add <vscale x 8 x i16> %va, %vb147 store <vscale x 8 x i16> %vc, ptr %pc148 ret void149}150 151define void @vadd_vint16m4(ptr %pc, ptr %pa, ptr %pb) nounwind {152; CHECK-LABEL: vadd_vint16m4:153; CHECK: # %bb.0:154; CHECK-NEXT: vl4re16.v v8, (a1)155; CHECK-NEXT: vl4re16.v v12, (a2)156; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma157; CHECK-NEXT: vadd.vv v8, v8, v12158; CHECK-NEXT: vs4r.v v8, (a0)159; CHECK-NEXT: ret160 %va = load <vscale x 16 x i16>, ptr %pa161 %vb = load <vscale x 16 x i16>, ptr %pb162 %vc = add <vscale x 16 x i16> %va, %vb163 store <vscale x 16 x i16> %vc, ptr %pc164 ret void165}166 167define void @vadd_vint16m8(ptr %pc, ptr %pa, ptr %pb) nounwind {168; CHECK-LABEL: vadd_vint16m8:169; CHECK: # %bb.0:170; CHECK-NEXT: vl8re16.v v8, (a1)171; CHECK-NEXT: vl8re16.v v16, (a2)172; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma173; CHECK-NEXT: vadd.vv v8, v8, v16174; CHECK-NEXT: vs8r.v v8, (a0)175; CHECK-NEXT: ret176 %va = load <vscale x 32 x i16>, ptr %pa177 %vb = load <vscale x 32 x i16>, ptr %pb178 %vc = add <vscale x 32 x i16> %va, %vb179 store <vscale x 32 x i16> %vc, ptr %pc180 ret void181}182 183define void @vadd_vint16mf2(ptr %pc, ptr %pa, ptr %pb) nounwind {184; CHECK-LABEL: vadd_vint16mf2:185; CHECK: # %bb.0:186; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, ma187; CHECK-NEXT: vle16.v v8, (a1)188; CHECK-NEXT: vle16.v v9, (a2)189; CHECK-NEXT: vadd.vv v8, v8, v9190; CHECK-NEXT: vse16.v v8, (a0)191; CHECK-NEXT: ret192 %va = load <vscale x 2 x i16>, ptr %pa193 %vb = load <vscale x 2 x i16>, ptr %pb194 %vc = add <vscale x 2 x i16> %va, %vb195 store <vscale x 2 x i16> %vc, ptr %pc196 ret void197}198 199define void @vadd_vint16mf4(ptr %pc, ptr %pa, ptr %pb) nounwind {200; CHECK-LABEL: vadd_vint16mf4:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli a3, zero, e16, mf4, ta, ma203; CHECK-NEXT: vle16.v v8, (a1)204; CHECK-NEXT: vle16.v v9, (a2)205; CHECK-NEXT: vadd.vv v8, v8, v9206; CHECK-NEXT: vse16.v v8, (a0)207; CHECK-NEXT: ret208 %va = load <vscale x 1 x i16>, ptr %pa209 %vb = load <vscale x 1 x i16>, ptr %pb210 %vc = add <vscale x 1 x i16> %va, %vb211 store <vscale x 1 x i16> %vc, ptr %pc212 ret void213}214 215define void @vadd_vint32m1(ptr %pc, ptr %pa, ptr %pb) nounwind {216; CHECK-LABEL: vadd_vint32m1:217; CHECK: # %bb.0:218; CHECK-NEXT: vl1re32.v v8, (a1)219; CHECK-NEXT: vl1re32.v v9, (a2)220; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma221; CHECK-NEXT: vadd.vv v8, v8, v9222; CHECK-NEXT: vs1r.v v8, (a0)223; CHECK-NEXT: ret224 %va = load <vscale x 2 x i32>, ptr %pa225 %vb = load <vscale x 2 x i32>, ptr %pb226 %vc = add <vscale x 2 x i32> %va, %vb227 store <vscale x 2 x i32> %vc, ptr %pc228 ret void229}230 231define void @vadd_vint32m2(ptr %pc, ptr %pa, ptr %pb) nounwind {232; CHECK-LABEL: vadd_vint32m2:233; CHECK: # %bb.0:234; CHECK-NEXT: vl2re32.v v8, (a1)235; CHECK-NEXT: vl2re32.v v10, (a2)236; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma237; CHECK-NEXT: vadd.vv v8, v8, v10238; CHECK-NEXT: vs2r.v v8, (a0)239; CHECK-NEXT: ret240 %va = load <vscale x 4 x i32>, ptr %pa241 %vb = load <vscale x 4 x i32>, ptr %pb242 %vc = add <vscale x 4 x i32> %va, %vb243 store <vscale x 4 x i32> %vc, ptr %pc244 ret void245}246 247define void @vadd_vint32m4(ptr %pc, ptr %pa, ptr %pb) nounwind {248; CHECK-LABEL: vadd_vint32m4:249; CHECK: # %bb.0:250; CHECK-NEXT: vl4re32.v v8, (a1)251; CHECK-NEXT: vl4re32.v v12, (a2)252; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma253; CHECK-NEXT: vadd.vv v8, v8, v12254; CHECK-NEXT: vs4r.v v8, (a0)255; CHECK-NEXT: ret256 %va = load <vscale x 8 x i32>, ptr %pa257 %vb = load <vscale x 8 x i32>, ptr %pb258 %vc = add <vscale x 8 x i32> %va, %vb259 store <vscale x 8 x i32> %vc, ptr %pc260 ret void261}262 263define void @vadd_vint32m8(ptr %pc, ptr %pa, ptr %pb) nounwind {264; CHECK-LABEL: vadd_vint32m8:265; CHECK: # %bb.0:266; CHECK-NEXT: vl8re32.v v8, (a1)267; CHECK-NEXT: vl8re32.v v16, (a2)268; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma269; CHECK-NEXT: vadd.vv v8, v8, v16270; CHECK-NEXT: vs8r.v v8, (a0)271; CHECK-NEXT: ret272 %va = load <vscale x 16 x i32>, ptr %pa273 %vb = load <vscale x 16 x i32>, ptr %pb274 %vc = add <vscale x 16 x i32> %va, %vb275 store <vscale x 16 x i32> %vc, ptr %pc276 ret void277}278 279define void @vadd_vint32mf2(ptr %pc, ptr %pa, ptr %pb) nounwind {280; CHECK-LABEL: vadd_vint32mf2:281; CHECK: # %bb.0:282; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma283; CHECK-NEXT: vle32.v v8, (a1)284; CHECK-NEXT: vle32.v v9, (a2)285; CHECK-NEXT: vadd.vv v8, v8, v9286; CHECK-NEXT: vse32.v v8, (a0)287; CHECK-NEXT: ret288 %va = load <vscale x 1 x i32>, ptr %pa289 %vb = load <vscale x 1 x i32>, ptr %pb290 %vc = add <vscale x 1 x i32> %va, %vb291 store <vscale x 1 x i32> %vc, ptr %pc292 ret void293}294 295define void @vadd_vint64m1(ptr %pc, ptr %pa, ptr %pb) nounwind {296; CHECK-LABEL: vadd_vint64m1:297; CHECK: # %bb.0:298; CHECK-NEXT: vl1re64.v v8, (a1)299; CHECK-NEXT: vl1re64.v v9, (a2)300; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma301; CHECK-NEXT: vadd.vv v8, v8, v9302; CHECK-NEXT: vs1r.v v8, (a0)303; CHECK-NEXT: ret304 %va = load <vscale x 1 x i64>, ptr %pa305 %vb = load <vscale x 1 x i64>, ptr %pb306 %vc = add <vscale x 1 x i64> %va, %vb307 store <vscale x 1 x i64> %vc, ptr %pc308 ret void309}310 311define void @vadd_vint64m2(ptr %pc, ptr %pa, ptr %pb) nounwind {312; CHECK-LABEL: vadd_vint64m2:313; CHECK: # %bb.0:314; CHECK-NEXT: vl2re64.v v8, (a1)315; CHECK-NEXT: vl2re64.v v10, (a2)316; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma317; CHECK-NEXT: vadd.vv v8, v8, v10318; CHECK-NEXT: vs2r.v v8, (a0)319; CHECK-NEXT: ret320 %va = load <vscale x 2 x i64>, ptr %pa321 %vb = load <vscale x 2 x i64>, ptr %pb322 %vc = add <vscale x 2 x i64> %va, %vb323 store <vscale x 2 x i64> %vc, ptr %pc324 ret void325}326 327define void @vadd_vint64m4(ptr %pc, ptr %pa, ptr %pb) nounwind {328; CHECK-LABEL: vadd_vint64m4:329; CHECK: # %bb.0:330; CHECK-NEXT: vl4re64.v v8, (a1)331; CHECK-NEXT: vl4re64.v v12, (a2)332; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma333; CHECK-NEXT: vadd.vv v8, v8, v12334; CHECK-NEXT: vs4r.v v8, (a0)335; CHECK-NEXT: ret336 %va = load <vscale x 4 x i64>, ptr %pa337 %vb = load <vscale x 4 x i64>, ptr %pb338 %vc = add <vscale x 4 x i64> %va, %vb339 store <vscale x 4 x i64> %vc, ptr %pc340 ret void341}342 343define void @vadd_vint64m8(ptr %pc, ptr %pa, ptr %pb) nounwind {344; CHECK-LABEL: vadd_vint64m8:345; CHECK: # %bb.0:346; CHECK-NEXT: vl8re64.v v8, (a1)347; CHECK-NEXT: vl8re64.v v16, (a2)348; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma349; CHECK-NEXT: vadd.vv v8, v8, v16350; CHECK-NEXT: vs8r.v v8, (a0)351; CHECK-NEXT: ret352 %va = load <vscale x 8 x i64>, ptr %pa353 %vb = load <vscale x 8 x i64>, ptr %pb354 %vc = add <vscale x 8 x i64> %va, %vb355 store <vscale x 8 x i64> %vc, ptr %pc356 ret void357}358 359 360define void @exact_vlen_vadd_vint8m1(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {361; CHECK-LABEL: exact_vlen_vadd_vint8m1:362; CHECK: # %bb.0:363; CHECK-NEXT: vl1r.v v8, (a1)364; CHECK-NEXT: vl1r.v v9, (a2)365; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma366; CHECK-NEXT: vadd.vv v8, v8, v9367; CHECK-NEXT: vs1r.v v8, (a0)368; CHECK-NEXT: ret369 %va = load <vscale x 8 x i8>, ptr %pa370 %vb = load <vscale x 8 x i8>, ptr %pb371 %vc = add <vscale x 8 x i8> %va, %vb372 store <vscale x 8 x i8> %vc, ptr %pc373 ret void374}375 376define void @exact_vlen_vadd_vint8m2(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {377; CHECK-LABEL: exact_vlen_vadd_vint8m2:378; CHECK: # %bb.0:379; CHECK-NEXT: vl2r.v v8, (a1)380; CHECK-NEXT: vl2r.v v10, (a2)381; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma382; CHECK-NEXT: vadd.vv v8, v8, v10383; CHECK-NEXT: vs2r.v v8, (a0)384; CHECK-NEXT: ret385 %va = load <vscale x 16 x i8>, ptr %pa386 %vb = load <vscale x 16 x i8>, ptr %pb387 %vc = add <vscale x 16 x i8> %va, %vb388 store <vscale x 16 x i8> %vc, ptr %pc389 ret void390}391 392define void @exact_vlen_vadd_vint8mf2(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {393; CHECK-LABEL: exact_vlen_vadd_vint8mf2:394; CHECK: # %bb.0:395; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma396; CHECK-NEXT: vle8.v v8, (a1)397; CHECK-NEXT: vle8.v v9, (a2)398; CHECK-NEXT: vadd.vv v8, v8, v9399; CHECK-NEXT: vse8.v v8, (a0)400; CHECK-NEXT: ret401 %va = load <vscale x 4 x i8>, ptr %pa402 %vb = load <vscale x 4 x i8>, ptr %pb403 %vc = add <vscale x 4 x i8> %va, %vb404 store <vscale x 4 x i8> %vc, ptr %pc405 ret void406}407 408define void @exact_vlen_vadd_vint8mf4(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {409; CHECK-LABEL: exact_vlen_vadd_vint8mf4:410; CHECK: # %bb.0:411; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma412; CHECK-NEXT: vle8.v v8, (a1)413; CHECK-NEXT: vle8.v v9, (a2)414; CHECK-NEXT: vadd.vv v8, v8, v9415; CHECK-NEXT: vse8.v v8, (a0)416; CHECK-NEXT: ret417 %va = load <vscale x 2 x i8>, ptr %pa418 %vb = load <vscale x 2 x i8>, ptr %pb419 %vc = add <vscale x 2 x i8> %va, %vb420 store <vscale x 2 x i8> %vc, ptr %pc421 ret void422}423 424define void @exact_vlen_vadd_vint8mf8(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {425; CHECK-LABEL: exact_vlen_vadd_vint8mf8:426; CHECK: # %bb.0:427; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma428; CHECK-NEXT: vle8.v v8, (a1)429; CHECK-NEXT: vle8.v v9, (a2)430; CHECK-NEXT: vadd.vv v8, v8, v9431; CHECK-NEXT: vse8.v v8, (a0)432; CHECK-NEXT: ret433 %va = load <vscale x 1 x i8>, ptr %pa434 %vb = load <vscale x 1 x i8>, ptr %pb435 %vc = add <vscale x 1 x i8> %va, %vb436 store <vscale x 1 x i8> %vc, ptr %pc437 ret void438}439 440define void @exact_vlen_vadd_vint32m1(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {441; CHECK-LABEL: exact_vlen_vadd_vint32m1:442; CHECK: # %bb.0:443; CHECK-NEXT: vl1re32.v v8, (a1)444; CHECK-NEXT: vl1re32.v v9, (a2)445; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma446; CHECK-NEXT: vadd.vv v8, v8, v9447; CHECK-NEXT: vs1r.v v8, (a0)448; CHECK-NEXT: ret449 %va = load <vscale x 2 x i32>, ptr %pa450 %vb = load <vscale x 2 x i32>, ptr %pb451 %vc = add <vscale x 2 x i32> %va, %vb452 store <vscale x 2 x i32> %vc, ptr %pc453 ret void454}455 456define void @exact_vlen_vadd_vint32m2(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {457; CHECK-LABEL: exact_vlen_vadd_vint32m2:458; CHECK: # %bb.0:459; CHECK-NEXT: vl2re32.v v8, (a1)460; CHECK-NEXT: vl2re32.v v10, (a2)461; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma462; CHECK-NEXT: vadd.vv v8, v8, v10463; CHECK-NEXT: vs2r.v v8, (a0)464; CHECK-NEXT: ret465 %va = load <vscale x 4 x i32>, ptr %pa466 %vb = load <vscale x 4 x i32>, ptr %pb467 %vc = add <vscale x 4 x i32> %va, %vb468 store <vscale x 4 x i32> %vc, ptr %pc469 ret void470}471 472define void @exact_vlen_vadd_vint32m4(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {473; CHECK-LABEL: exact_vlen_vadd_vint32m4:474; CHECK: # %bb.0:475; CHECK-NEXT: vl4re32.v v8, (a1)476; CHECK-NEXT: vl4re32.v v12, (a2)477; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma478; CHECK-NEXT: vadd.vv v8, v8, v12479; CHECK-NEXT: vs4r.v v8, (a0)480; CHECK-NEXT: ret481 %va = load <vscale x 8 x i32>, ptr %pa482 %vb = load <vscale x 8 x i32>, ptr %pb483 %vc = add <vscale x 8 x i32> %va, %vb484 store <vscale x 8 x i32> %vc, ptr %pc485 ret void486}487 488define void @exact_vlen_vadd_vint32m8(ptr %pc, ptr %pa, ptr %pb) nounwind vscale_range(2,2) {489; CHECK-LABEL: exact_vlen_vadd_vint32m8:490; CHECK: # %bb.0:491; CHECK-NEXT: vl8re32.v v8, (a1)492; CHECK-NEXT: vl8re32.v v16, (a2)493; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma494; CHECK-NEXT: vadd.vv v8, v8, v16495; CHECK-NEXT: vs8r.v v8, (a0)496; CHECK-NEXT: ret497 %va = load <vscale x 16 x i32>, ptr %pa498 %vb = load <vscale x 16 x i32>, ptr %pb499 %vc = add <vscale x 16 x i32> %va, %vb500 store <vscale x 16 x i32> %vc, ptr %pc501 ret void502}503