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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v < %s \3; RUN: | FileCheck %s -check-prefix=RV64IV4 5define void @local_var_mf8() {6; RV64IV-LABEL: local_var_mf8:7; RV64IV: # %bb.0:8; RV64IV-NEXT: addi sp, sp, -169; RV64IV-NEXT: .cfi_def_cfa_offset 1610; RV64IV-NEXT: csrr a0, vlenb11; RV64IV-NEXT: slli a0, a0, 112; RV64IV-NEXT: sub sp, sp, a013; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb14; RV64IV-NEXT: csrr a0, vlenb15; RV64IV-NEXT: add a0, sp, a016; RV64IV-NEXT: addi a0, a0, 1617; RV64IV-NEXT: vsetvli a1, zero, e8, mf8, ta, ma18; RV64IV-NEXT: vle8.v v8, (a0)19; RV64IV-NEXT: addi a0, sp, 1620; RV64IV-NEXT: vle8.v v8, (a0)21; RV64IV-NEXT: csrr a0, vlenb22; RV64IV-NEXT: slli a0, a0, 123; RV64IV-NEXT: add sp, sp, a024; RV64IV-NEXT: .cfi_def_cfa sp, 1625; RV64IV-NEXT: addi sp, sp, 1626; RV64IV-NEXT: .cfi_def_cfa_offset 027; RV64IV-NEXT: ret28 %local0 = alloca <vscale x 1 x i8>29 %local1 = alloca <vscale x 1 x i8>30 load volatile <vscale x 1 x i8>, ptr %local031 load volatile <vscale x 1 x i8>, ptr %local132 ret void33}34 35define void @local_var_m1() {36; RV64IV-LABEL: local_var_m1:37; RV64IV: # %bb.0:38; RV64IV-NEXT: addi sp, sp, -1639; RV64IV-NEXT: .cfi_def_cfa_offset 1640; RV64IV-NEXT: csrr a0, vlenb41; RV64IV-NEXT: slli a0, a0, 142; RV64IV-NEXT: sub sp, sp, a043; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb44; RV64IV-NEXT: csrr a0, vlenb45; RV64IV-NEXT: add a0, sp, a046; RV64IV-NEXT: addi a0, a0, 1647; RV64IV-NEXT: vl1r.v v8, (a0)48; RV64IV-NEXT: addi a0, sp, 1649; RV64IV-NEXT: vl1r.v v8, (a0)50; RV64IV-NEXT: csrr a0, vlenb51; RV64IV-NEXT: slli a0, a0, 152; RV64IV-NEXT: add sp, sp, a053; RV64IV-NEXT: .cfi_def_cfa sp, 1654; RV64IV-NEXT: addi sp, sp, 1655; RV64IV-NEXT: .cfi_def_cfa_offset 056; RV64IV-NEXT: ret57 %local0 = alloca <vscale x 8 x i8>58 %local1 = alloca <vscale x 8 x i8>59 load volatile <vscale x 8 x i8>, ptr %local060 load volatile <vscale x 8 x i8>, ptr %local161 ret void62}63 64define void @local_var_m2() {65; RV64IV-LABEL: local_var_m2:66; RV64IV: # %bb.0:67; RV64IV-NEXT: addi sp, sp, -1668; RV64IV-NEXT: .cfi_def_cfa_offset 1669; RV64IV-NEXT: csrr a0, vlenb70; RV64IV-NEXT: slli a0, a0, 271; RV64IV-NEXT: sub sp, sp, a072; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb73; RV64IV-NEXT: csrr a0, vlenb74; RV64IV-NEXT: slli a0, a0, 175; RV64IV-NEXT: add a0, sp, a076; RV64IV-NEXT: addi a0, a0, 1677; RV64IV-NEXT: vl2r.v v8, (a0)78; RV64IV-NEXT: addi a0, sp, 1679; RV64IV-NEXT: vl2r.v v8, (a0)80; RV64IV-NEXT: csrr a0, vlenb81; RV64IV-NEXT: slli a0, a0, 282; RV64IV-NEXT: add sp, sp, a083; RV64IV-NEXT: .cfi_def_cfa sp, 1684; RV64IV-NEXT: addi sp, sp, 1685; RV64IV-NEXT: .cfi_def_cfa_offset 086; RV64IV-NEXT: ret87 %local0 = alloca <vscale x 16 x i8>88 %local1 = alloca <vscale x 16 x i8>89 load volatile <vscale x 16 x i8>, ptr %local090 load volatile <vscale x 16 x i8>, ptr %local191 ret void92}93 94define void @local_var_m4() {95; RV64IV-LABEL: local_var_m4:96; RV64IV: # %bb.0:97; RV64IV-NEXT: addi sp, sp, -4898; RV64IV-NEXT: .cfi_def_cfa_offset 4899; RV64IV-NEXT: sd ra, 40(sp) # 8-byte Folded Spill100; RV64IV-NEXT: sd s0, 32(sp) # 8-byte Folded Spill101; RV64IV-NEXT: .cfi_offset ra, -8102; RV64IV-NEXT: .cfi_offset s0, -16103; RV64IV-NEXT: addi s0, sp, 48104; RV64IV-NEXT: .cfi_def_cfa s0, 0105; RV64IV-NEXT: csrr a0, vlenb106; RV64IV-NEXT: slli a0, a0, 3107; RV64IV-NEXT: sub sp, sp, a0108; RV64IV-NEXT: andi sp, sp, -32109; RV64IV-NEXT: csrr a0, vlenb110; RV64IV-NEXT: slli a0, a0, 2111; RV64IV-NEXT: add a0, sp, a0112; RV64IV-NEXT: addi a0, a0, 32113; RV64IV-NEXT: vl4r.v v8, (a0)114; RV64IV-NEXT: addi a0, sp, 32115; RV64IV-NEXT: vl4r.v v8, (a0)116; RV64IV-NEXT: addi sp, s0, -48117; RV64IV-NEXT: .cfi_def_cfa sp, 48118; RV64IV-NEXT: ld ra, 40(sp) # 8-byte Folded Reload119; RV64IV-NEXT: ld s0, 32(sp) # 8-byte Folded Reload120; RV64IV-NEXT: .cfi_restore ra121; RV64IV-NEXT: .cfi_restore s0122; RV64IV-NEXT: addi sp, sp, 48123; RV64IV-NEXT: .cfi_def_cfa_offset 0124; RV64IV-NEXT: ret125 %local0 = alloca <vscale x 32 x i8>126 %local1 = alloca <vscale x 32 x i8>127 load volatile <vscale x 32 x i8>, ptr %local0128 load volatile <vscale x 32 x i8>, ptr %local1129 ret void130}131 132define void @local_var_m8() {133; RV64IV-LABEL: local_var_m8:134; RV64IV: # %bb.0:135; RV64IV-NEXT: addi sp, sp, -80136; RV64IV-NEXT: .cfi_def_cfa_offset 80137; RV64IV-NEXT: sd ra, 72(sp) # 8-byte Folded Spill138; RV64IV-NEXT: sd s0, 64(sp) # 8-byte Folded Spill139; RV64IV-NEXT: .cfi_offset ra, -8140; RV64IV-NEXT: .cfi_offset s0, -16141; RV64IV-NEXT: addi s0, sp, 80142; RV64IV-NEXT: .cfi_def_cfa s0, 0143; RV64IV-NEXT: csrr a0, vlenb144; RV64IV-NEXT: slli a0, a0, 4145; RV64IV-NEXT: sub sp, sp, a0146; RV64IV-NEXT: andi sp, sp, -64147; RV64IV-NEXT: csrr a0, vlenb148; RV64IV-NEXT: slli a0, a0, 3149; RV64IV-NEXT: add a0, sp, a0150; RV64IV-NEXT: addi a0, a0, 64151; RV64IV-NEXT: vl8r.v v8, (a0)152; RV64IV-NEXT: addi a0, sp, 64153; RV64IV-NEXT: vl8r.v v8, (a0)154; RV64IV-NEXT: addi sp, s0, -80155; RV64IV-NEXT: .cfi_def_cfa sp, 80156; RV64IV-NEXT: ld ra, 72(sp) # 8-byte Folded Reload157; RV64IV-NEXT: ld s0, 64(sp) # 8-byte Folded Reload158; RV64IV-NEXT: .cfi_restore ra159; RV64IV-NEXT: .cfi_restore s0160; RV64IV-NEXT: addi sp, sp, 80161; RV64IV-NEXT: .cfi_def_cfa_offset 0162; RV64IV-NEXT: ret163 %local0 = alloca <vscale x 64 x i8>164 %local1 = alloca <vscale x 64 x i8>165 load volatile <vscale x 64 x i8>, ptr %local0166 load volatile <vscale x 64 x i8>, ptr %local1167 ret void168}169 170define void @local_var_m2_mix_local_scalar() {171; RV64IV-LABEL: local_var_m2_mix_local_scalar:172; RV64IV: # %bb.0:173; RV64IV-NEXT: addi sp, sp, -16174; RV64IV-NEXT: .cfi_def_cfa_offset 16175; RV64IV-NEXT: csrr a0, vlenb176; RV64IV-NEXT: slli a0, a0, 2177; RV64IV-NEXT: sub sp, sp, a0178; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb179; RV64IV-NEXT: lw zero, 12(sp)180; RV64IV-NEXT: csrr a0, vlenb181; RV64IV-NEXT: slli a0, a0, 1182; RV64IV-NEXT: add a0, sp, a0183; RV64IV-NEXT: addi a0, a0, 16184; RV64IV-NEXT: vl2r.v v8, (a0)185; RV64IV-NEXT: addi a0, sp, 16186; RV64IV-NEXT: vl2r.v v8, (a0)187; RV64IV-NEXT: lw zero, 8(sp)188; RV64IV-NEXT: csrr a0, vlenb189; RV64IV-NEXT: slli a0, a0, 2190; RV64IV-NEXT: add sp, sp, a0191; RV64IV-NEXT: .cfi_def_cfa sp, 16192; RV64IV-NEXT: addi sp, sp, 16193; RV64IV-NEXT: .cfi_def_cfa_offset 0194; RV64IV-NEXT: ret195 %local_scalar0 = alloca i32196 %local0 = alloca <vscale x 16 x i8>197 %local1 = alloca <vscale x 16 x i8>198 %local_scalar1 = alloca i32199 load volatile i32, ptr %local_scalar0200 load volatile <vscale x 16 x i8>, ptr %local0201 load volatile <vscale x 16 x i8>, ptr %local1202 load volatile i32, ptr %local_scalar1203 ret void204}205 206define void @local_var_m2_with_varsize_object(i64 %n) {207; RV64IV-LABEL: local_var_m2_with_varsize_object:208; RV64IV: # %bb.0:209; RV64IV-NEXT: addi sp, sp, -32210; RV64IV-NEXT: .cfi_def_cfa_offset 32211; RV64IV-NEXT: sd ra, 24(sp) # 8-byte Folded Spill212; RV64IV-NEXT: sd s0, 16(sp) # 8-byte Folded Spill213; RV64IV-NEXT: sd s1, 8(sp) # 8-byte Folded Spill214; RV64IV-NEXT: .cfi_offset ra, -8215; RV64IV-NEXT: .cfi_offset s0, -16216; RV64IV-NEXT: .cfi_offset s1, -24217; RV64IV-NEXT: addi s0, sp, 32218; RV64IV-NEXT: .cfi_def_cfa s0, 0219; RV64IV-NEXT: csrr a1, vlenb220; RV64IV-NEXT: slli a1, a1, 2221; RV64IV-NEXT: sub sp, sp, a1222; RV64IV-NEXT: addi a0, a0, 15223; RV64IV-NEXT: andi a0, a0, -16224; RV64IV-NEXT: sub a0, sp, a0225; RV64IV-NEXT: mv sp, a0226; RV64IV-NEXT: csrr a1, vlenb227; RV64IV-NEXT: slli a1, a1, 1228; RV64IV-NEXT: sub a1, s0, a1229; RV64IV-NEXT: addi a1, a1, -32230; RV64IV-NEXT: csrr s1, vlenb231; RV64IV-NEXT: slli s1, s1, 1232; RV64IV-NEXT: sub s1, s0, s1233; RV64IV-NEXT: addi s1, s1, -32234; RV64IV-NEXT: call notdead235; RV64IV-NEXT: vl2r.v v8, (s1)236; RV64IV-NEXT: csrr a0, vlenb237; RV64IV-NEXT: slli a0, a0, 2238; RV64IV-NEXT: sub a0, s0, a0239; RV64IV-NEXT: addi a0, a0, -32240; RV64IV-NEXT: vl2r.v v8, (a0)241; RV64IV-NEXT: addi sp, s0, -32242; RV64IV-NEXT: .cfi_def_cfa sp, 32243; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload244; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload245; RV64IV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload246; RV64IV-NEXT: .cfi_restore ra247; RV64IV-NEXT: .cfi_restore s0248; RV64IV-NEXT: .cfi_restore s1249; RV64IV-NEXT: addi sp, sp, 32250; RV64IV-NEXT: .cfi_def_cfa_offset 0251; RV64IV-NEXT: ret252 %1 = alloca i8, i64 %n253 %2 = alloca <vscale x 16 x i8>254 %3 = alloca <vscale x 16 x i8>255 call void @notdead(ptr %1, ptr %2)256 load volatile <vscale x 16 x i8>, ptr %2257 load volatile <vscale x 16 x i8>, ptr %3258 ret void259}260 261define void @local_var_m2_with_bp(i64 %n) {262; RV64IV-LABEL: local_var_m2_with_bp:263; RV64IV: # %bb.0:264; RV64IV-NEXT: addi sp, sp, -256265; RV64IV-NEXT: .cfi_def_cfa_offset 256266; RV64IV-NEXT: sd ra, 248(sp) # 8-byte Folded Spill267; RV64IV-NEXT: sd s0, 240(sp) # 8-byte Folded Spill268; RV64IV-NEXT: sd s1, 232(sp) # 8-byte Folded Spill269; RV64IV-NEXT: sd s2, 224(sp) # 8-byte Folded Spill270; RV64IV-NEXT: .cfi_offset ra, -8271; RV64IV-NEXT: .cfi_offset s0, -16272; RV64IV-NEXT: .cfi_offset s1, -24273; RV64IV-NEXT: .cfi_offset s2, -32274; RV64IV-NEXT: addi s0, sp, 256275; RV64IV-NEXT: .cfi_def_cfa s0, 0276; RV64IV-NEXT: csrr a1, vlenb277; RV64IV-NEXT: slli a1, a1, 2278; RV64IV-NEXT: sub sp, sp, a1279; RV64IV-NEXT: andi sp, sp, -128280; RV64IV-NEXT: mv s1, sp281; RV64IV-NEXT: addi a0, a0, 15282; RV64IV-NEXT: andi a0, a0, -16283; RV64IV-NEXT: sub a0, sp, a0284; RV64IV-NEXT: mv sp, a0285; RV64IV-NEXT: addi a1, s1, 128286; RV64IV-NEXT: csrr a2, vlenb287; RV64IV-NEXT: slli a2, a2, 1288; RV64IV-NEXT: add a2, s1, a2289; RV64IV-NEXT: addi a2, a2, 224290; RV64IV-NEXT: csrr s2, vlenb291; RV64IV-NEXT: slli s2, s2, 1292; RV64IV-NEXT: add s2, s1, s2293; RV64IV-NEXT: addi s2, s2, 224294; RV64IV-NEXT: call notdead2295; RV64IV-NEXT: lw zero, 124(s1)296; RV64IV-NEXT: vl2r.v v8, (s2)297; RV64IV-NEXT: addi a0, s1, 224298; RV64IV-NEXT: vl2r.v v8, (a0)299; RV64IV-NEXT: lw zero, 120(s1)300; RV64IV-NEXT: addi sp, s0, -256301; RV64IV-NEXT: .cfi_def_cfa sp, 256302; RV64IV-NEXT: ld ra, 248(sp) # 8-byte Folded Reload303; RV64IV-NEXT: ld s0, 240(sp) # 8-byte Folded Reload304; RV64IV-NEXT: ld s1, 232(sp) # 8-byte Folded Reload305; RV64IV-NEXT: ld s2, 224(sp) # 8-byte Folded Reload306; RV64IV-NEXT: .cfi_restore ra307; RV64IV-NEXT: .cfi_restore s0308; RV64IV-NEXT: .cfi_restore s1309; RV64IV-NEXT: .cfi_restore s2310; RV64IV-NEXT: addi sp, sp, 256311; RV64IV-NEXT: .cfi_def_cfa_offset 0312; RV64IV-NEXT: ret313 %1 = alloca i8, i64 %n314 %2 = alloca i32, align 128315 %local_scalar0 = alloca i32316 %local0 = alloca <vscale x 16 x i8>317 %local1 = alloca <vscale x 16 x i8>318 %local_scalar1 = alloca i32319 call void @notdead2(ptr %1, ptr %2, ptr %local0)320 load volatile i32, ptr %local_scalar0321 load volatile <vscale x 16 x i8>, ptr %local0322 load volatile <vscale x 16 x i8>, ptr %local1323 load volatile i32, ptr %local_scalar1324 ret void325}326 327define i64 @fixed_object(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8) nounwind {328; RV64IV-LABEL: fixed_object:329; RV64IV: # %bb.0:330; RV64IV-NEXT: addi sp, sp, -16331; RV64IV-NEXT: csrr a0, vlenb332; RV64IV-NEXT: slli a0, a0, 3333; RV64IV-NEXT: sub sp, sp, a0334; RV64IV-NEXT: csrr a0, vlenb335; RV64IV-NEXT: slli a0, a0, 3336; RV64IV-NEXT: add a0, sp, a0337; RV64IV-NEXT: ld a0, 16(a0)338; RV64IV-NEXT: csrr a1, vlenb339; RV64IV-NEXT: slli a1, a1, 3340; RV64IV-NEXT: add sp, sp, a1341; RV64IV-NEXT: addi sp, sp, 16342; RV64IV-NEXT: ret343 %fixed_size = alloca i32344 %rvv_vector = alloca <vscale x 8 x i64>, align 8345 ret i64 %8346}347 348declare void @notdead(ptr, ptr)349declare void @notdead2(ptr, ptr, ptr)350