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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \3; RUN: -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV324; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \5; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i326; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \7; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i648 9define <vscale x 1 x iXLen> @lrint_nxv1f32(<vscale x 1 x float> %x) {10; RV32-LABEL: lrint_nxv1f32:11; RV32: # %bb.0:12; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma13; RV32-NEXT: vfcvt.x.f.v v8, v814; RV32-NEXT: ret15;16; RV64-i32-LABEL: lrint_nxv1f32:17; RV64-i32: # %bb.0:18; RV64-i32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma19; RV64-i32-NEXT: vfcvt.x.f.v v8, v820; RV64-i32-NEXT: ret21;22; RV64-i64-LABEL: lrint_nxv1f32:23; RV64-i64: # %bb.0:24; RV64-i64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma25; RV64-i64-NEXT: vfwcvt.x.f.v v9, v826; RV64-i64-NEXT: vmv1r.v v8, v927; RV64-i64-NEXT: ret28 %a = call <vscale x 1 x iXLen> @llvm.lrint.nxv1iXLen.nxv1f32(<vscale x 1 x float> %x)29 ret <vscale x 1 x iXLen> %a30}31 32define <vscale x 2 x iXLen> @lrint_nxv2f32(<vscale x 2 x float> %x) {33; RV32-LABEL: lrint_nxv2f32:34; RV32: # %bb.0:35; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma36; RV32-NEXT: vfcvt.x.f.v v8, v837; RV32-NEXT: ret38;39; RV64-i32-LABEL: lrint_nxv2f32:40; RV64-i32: # %bb.0:41; RV64-i32-NEXT: vsetvli a0, zero, e32, m1, ta, ma42; RV64-i32-NEXT: vfcvt.x.f.v v8, v843; RV64-i32-NEXT: ret44;45; RV64-i64-LABEL: lrint_nxv2f32:46; RV64-i64: # %bb.0:47; RV64-i64-NEXT: vsetvli a0, zero, e32, m1, ta, ma48; RV64-i64-NEXT: vmv1r.v v10, v849; RV64-i64-NEXT: vfwcvt.x.f.v v8, v1050; RV64-i64-NEXT: ret51 %a = call <vscale x 2 x iXLen> @llvm.lrint.nxv2iXLen.nxv2f32(<vscale x 2 x float> %x)52 ret <vscale x 2 x iXLen> %a53}54 55define <vscale x 4 x iXLen> @lrint_nxv4f32(<vscale x 4 x float> %x) {56; RV32-LABEL: lrint_nxv4f32:57; RV32: # %bb.0:58; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma59; RV32-NEXT: vfcvt.x.f.v v8, v860; RV32-NEXT: ret61;62; RV64-i32-LABEL: lrint_nxv4f32:63; RV64-i32: # %bb.0:64; RV64-i32-NEXT: vsetvli a0, zero, e32, m2, ta, ma65; RV64-i32-NEXT: vfcvt.x.f.v v8, v866; RV64-i32-NEXT: ret67;68; RV64-i64-LABEL: lrint_nxv4f32:69; RV64-i64: # %bb.0:70; RV64-i64-NEXT: vsetvli a0, zero, e32, m2, ta, ma71; RV64-i64-NEXT: vmv2r.v v12, v872; RV64-i64-NEXT: vfwcvt.x.f.v v8, v1273; RV64-i64-NEXT: ret74 %a = call <vscale x 4 x iXLen> @llvm.lrint.nxv4iXLen.nxv4f32(<vscale x 4 x float> %x)75 ret <vscale x 4 x iXLen> %a76}77 78define <vscale x 8 x iXLen> @lrint_nxv8f32(<vscale x 8 x float> %x) {79; RV32-LABEL: lrint_nxv8f32:80; RV32: # %bb.0:81; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma82; RV32-NEXT: vfcvt.x.f.v v8, v883; RV32-NEXT: ret84;85; RV64-i32-LABEL: lrint_nxv8f32:86; RV64-i32: # %bb.0:87; RV64-i32-NEXT: vsetvli a0, zero, e32, m4, ta, ma88; RV64-i32-NEXT: vfcvt.x.f.v v8, v889; RV64-i32-NEXT: ret90;91; RV64-i64-LABEL: lrint_nxv8f32:92; RV64-i64: # %bb.0:93; RV64-i64-NEXT: vsetvli a0, zero, e32, m4, ta, ma94; RV64-i64-NEXT: vmv4r.v v16, v895; RV64-i64-NEXT: vfwcvt.x.f.v v8, v1696; RV64-i64-NEXT: ret97 %a = call <vscale x 8 x iXLen> @llvm.lrint.nxv8iXLen.nxv8f32(<vscale x 8 x float> %x)98 ret <vscale x 8 x iXLen> %a99}100 101define <vscale x 16 x iXLen> @lrint_nxv16f32(<vscale x 16 x float> %x) {102; RV32-LABEL: lrint_nxv16f32:103; RV32: # %bb.0:104; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma105; RV32-NEXT: vfcvt.x.f.v v8, v8106; RV32-NEXT: ret107;108; RV64-i32-LABEL: lrint_nxv16f32:109; RV64-i32: # %bb.0:110; RV64-i32-NEXT: vsetvli a0, zero, e32, m8, ta, ma111; RV64-i32-NEXT: vfcvt.x.f.v v8, v8112; RV64-i32-NEXT: ret113;114; RV64-i64-LABEL: lrint_nxv16f32:115; RV64-i64: # %bb.0:116; RV64-i64-NEXT: vsetvli a0, zero, e32, m4, ta, ma117; RV64-i64-NEXT: vfwcvt.x.f.v v24, v8118; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12119; RV64-i64-NEXT: vmv8r.v v8, v24120; RV64-i64-NEXT: ret121 %a = call <vscale x 16 x iXLen> @llvm.lrint.nxv16iXLen.nxv16f32(<vscale x 16 x float> %x)122 ret <vscale x 16 x iXLen> %a123}124 125define <vscale x 1 x iXLen> @lrint_nxv1f64(<vscale x 1 x double> %x) {126; RV32-LABEL: lrint_nxv1f64:127; RV32: # %bb.0:128; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma129; RV32-NEXT: vfncvt.x.f.w v9, v8130; RV32-NEXT: vmv1r.v v8, v9131; RV32-NEXT: ret132;133; RV64-i32-LABEL: lrint_nxv1f64:134; RV64-i32: # %bb.0:135; RV64-i32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma136; RV64-i32-NEXT: vfncvt.x.f.w v9, v8137; RV64-i32-NEXT: vmv1r.v v8, v9138; RV64-i32-NEXT: ret139;140; RV64-i64-LABEL: lrint_nxv1f64:141; RV64-i64: # %bb.0:142; RV64-i64-NEXT: vsetvli a0, zero, e64, m1, ta, ma143; RV64-i64-NEXT: vfcvt.x.f.v v8, v8144; RV64-i64-NEXT: ret145 %a = call <vscale x 1 x iXLen> @llvm.lrint.nxv1iXLen.nxv1f64(<vscale x 1 x double> %x)146 ret <vscale x 1 x iXLen> %a147}148 149define <vscale x 2 x iXLen> @lrint_nxv2f64(<vscale x 2 x double> %x) {150; RV32-LABEL: lrint_nxv2f64:151; RV32: # %bb.0:152; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma153; RV32-NEXT: vfncvt.x.f.w v10, v8154; RV32-NEXT: vmv.v.v v8, v10155; RV32-NEXT: ret156;157; RV64-i32-LABEL: lrint_nxv2f64:158; RV64-i32: # %bb.0:159; RV64-i32-NEXT: vsetvli a0, zero, e32, m1, ta, ma160; RV64-i32-NEXT: vfncvt.x.f.w v10, v8161; RV64-i32-NEXT: vmv.v.v v8, v10162; RV64-i32-NEXT: ret163;164; RV64-i64-LABEL: lrint_nxv2f64:165; RV64-i64: # %bb.0:166; RV64-i64-NEXT: vsetvli a0, zero, e64, m2, ta, ma167; RV64-i64-NEXT: vfcvt.x.f.v v8, v8168; RV64-i64-NEXT: ret169 %a = call <vscale x 2 x iXLen> @llvm.lrint.nxv2iXLen.nxv2f64(<vscale x 2 x double> %x)170 ret <vscale x 2 x iXLen> %a171}172 173define <vscale x 4 x iXLen> @lrint_nxv4f64(<vscale x 4 x double> %x) {174; RV32-LABEL: lrint_nxv4f64:175; RV32: # %bb.0:176; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma177; RV32-NEXT: vfncvt.x.f.w v12, v8178; RV32-NEXT: vmv.v.v v8, v12179; RV32-NEXT: ret180;181; RV64-i32-LABEL: lrint_nxv4f64:182; RV64-i32: # %bb.0:183; RV64-i32-NEXT: vsetvli a0, zero, e32, m2, ta, ma184; RV64-i32-NEXT: vfncvt.x.f.w v12, v8185; RV64-i32-NEXT: vmv.v.v v8, v12186; RV64-i32-NEXT: ret187;188; RV64-i64-LABEL: lrint_nxv4f64:189; RV64-i64: # %bb.0:190; RV64-i64-NEXT: vsetvli a0, zero, e64, m4, ta, ma191; RV64-i64-NEXT: vfcvt.x.f.v v8, v8192; RV64-i64-NEXT: ret193 %a = call <vscale x 4 x iXLen> @llvm.lrint.nxv4iXLen.nxv4f64(<vscale x 4 x double> %x)194 ret <vscale x 4 x iXLen> %a195}196 197define <vscale x 8 x iXLen> @lrint_nxv8f64(<vscale x 8 x double> %x) {198; RV32-LABEL: lrint_nxv8f64:199; RV32: # %bb.0:200; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma201; RV32-NEXT: vfncvt.x.f.w v16, v8202; RV32-NEXT: vmv.v.v v8, v16203; RV32-NEXT: ret204;205; RV64-i32-LABEL: lrint_nxv8f64:206; RV64-i32: # %bb.0:207; RV64-i32-NEXT: vsetvli a0, zero, e32, m4, ta, ma208; RV64-i32-NEXT: vfncvt.x.f.w v16, v8209; RV64-i32-NEXT: vmv.v.v v8, v16210; RV64-i32-NEXT: ret211;212; RV64-i64-LABEL: lrint_nxv8f64:213; RV64-i64: # %bb.0:214; RV64-i64-NEXT: vsetvli a0, zero, e64, m8, ta, ma215; RV64-i64-NEXT: vfcvt.x.f.v v8, v8216; RV64-i64-NEXT: ret217 %a = call <vscale x 8 x iXLen> @llvm.lrint.nxv8iXLen.nxv8f64(<vscale x 8 x double> %x)218 ret <vscale x 8 x iXLen> %a219}220 221define <vscale x 1 x iXLen> @lrint_nxv1f16(<vscale x 1 x half> %x) {222; RV32-LABEL: lrint_nxv1f16:223; RV32: # %bb.0:224; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma225; RV32-NEXT: vfwcvt.f.f.v v9, v8226; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma227; RV32-NEXT: vfcvt.x.f.v v8, v9228; RV32-NEXT: ret229;230; RV64-i32-LABEL: lrint_nxv1f16:231; RV64-i32: # %bb.0:232; RV64-i32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma233; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8234; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma235; RV64-i32-NEXT: vfcvt.x.f.v v8, v9236; RV64-i32-NEXT: ret237;238; RV64-i64-LABEL: lrint_nxv1f16:239; RV64-i64: # %bb.0:240; RV64-i64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma241; RV64-i64-NEXT: vfwcvt.f.f.v v9, v8242; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma243; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9244; RV64-i64-NEXT: ret245 %a = call <vscale x 1 x iXLen> @llvm.lrint.nxv1iXLen.nxv1f16(<vscale x 1 x half> %x)246 ret <vscale x 1 x iXLen> %a247}248 249define <vscale x 2 x iXLen> @lrint_nxv2f16(<vscale x 2 x half> %x) {250; RV32-LABEL: lrint_nxv2f16:251; RV32: # %bb.0:252; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, ma253; RV32-NEXT: vfwcvt.f.f.v v9, v8254; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma255; RV32-NEXT: vfcvt.x.f.v v8, v9256; RV32-NEXT: ret257;258; RV64-i32-LABEL: lrint_nxv2f16:259; RV64-i32: # %bb.0:260; RV64-i32-NEXT: vsetvli a0, zero, e16, mf2, ta, ma261; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8262; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma263; RV64-i32-NEXT: vfcvt.x.f.v v8, v9264; RV64-i32-NEXT: ret265;266; RV64-i64-LABEL: lrint_nxv2f16:267; RV64-i64: # %bb.0:268; RV64-i64-NEXT: vsetvli a0, zero, e16, mf2, ta, ma269; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8270; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma271; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10272; RV64-i64-NEXT: ret273 %a = call <vscale x 2 x iXLen> @llvm.lrint.nxv2iXLen.nxv2f16(<vscale x 2 x half> %x)274 ret <vscale x 2 x iXLen> %a275}276 277define <vscale x 4 x iXLen> @lrint_nxv4f16(<vscale x 4 x half> %x) {278; RV32-LABEL: lrint_nxv4f16:279; RV32: # %bb.0:280; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma281; RV32-NEXT: vfwcvt.f.f.v v10, v8282; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma283; RV32-NEXT: vfcvt.x.f.v v8, v10284; RV32-NEXT: ret285;286; RV64-i32-LABEL: lrint_nxv4f16:287; RV64-i32: # %bb.0:288; RV64-i32-NEXT: vsetvli a0, zero, e16, m1, ta, ma289; RV64-i32-NEXT: vfwcvt.f.f.v v10, v8290; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma291; RV64-i32-NEXT: vfcvt.x.f.v v8, v10292; RV64-i32-NEXT: ret293;294; RV64-i64-LABEL: lrint_nxv4f16:295; RV64-i64: # %bb.0:296; RV64-i64-NEXT: vsetvli a0, zero, e16, m1, ta, ma297; RV64-i64-NEXT: vfwcvt.f.f.v v12, v8298; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma299; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12300; RV64-i64-NEXT: ret301 %a = call <vscale x 4 x iXLen> @llvm.lrint.nxv4iXLen.nxv4f16(<vscale x 4 x half> %x)302 ret <vscale x 4 x iXLen> %a303}304 305define <vscale x 8 x iXLen> @lrint_nxv8f16(<vscale x 8 x half> %x) {306; RV32-LABEL: lrint_nxv8f16:307; RV32: # %bb.0:308; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, ma309; RV32-NEXT: vfwcvt.f.f.v v12, v8310; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma311; RV32-NEXT: vfcvt.x.f.v v8, v12312; RV32-NEXT: ret313;314; RV64-i32-LABEL: lrint_nxv8f16:315; RV64-i32: # %bb.0:316; RV64-i32-NEXT: vsetvli a0, zero, e16, m2, ta, ma317; RV64-i32-NEXT: vfwcvt.f.f.v v12, v8318; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma319; RV64-i32-NEXT: vfcvt.x.f.v v8, v12320; RV64-i32-NEXT: ret321;322; RV64-i64-LABEL: lrint_nxv8f16:323; RV64-i64: # %bb.0:324; RV64-i64-NEXT: vsetvli a0, zero, e16, m2, ta, ma325; RV64-i64-NEXT: vfwcvt.f.f.v v16, v8326; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma327; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16328; RV64-i64-NEXT: ret329 %a = call <vscale x 8 x iXLen> @llvm.lrint.nxv8iXLen.nxv8f16(<vscale x 8 x half> %x)330 ret <vscale x 8 x iXLen> %a331}332 333define <vscale x 16 x iXLen> @lrint_nxv16f16(<vscale x 16 x half> %x) {334; RV32-LABEL: lrint_nxv16f16:335; RV32: # %bb.0:336; RV32-NEXT: vsetvli a0, zero, e16, m4, ta, ma337; RV32-NEXT: vfwcvt.f.f.v v16, v8338; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma339; RV32-NEXT: vfcvt.x.f.v v8, v16340; RV32-NEXT: ret341;342; RV64-i32-LABEL: lrint_nxv16f16:343; RV64-i32: # %bb.0:344; RV64-i32-NEXT: vsetvli a0, zero, e16, m4, ta, ma345; RV64-i32-NEXT: vfwcvt.f.f.v v16, v8346; RV64-i32-NEXT: vsetvli zero, zero, e32, m8, ta, ma347; RV64-i32-NEXT: vfcvt.x.f.v v8, v16348; RV64-i32-NEXT: ret349;350; RV64-i64-LABEL: lrint_nxv16f16:351; RV64-i64: # %bb.0:352; RV64-i64-NEXT: vsetvli a0, zero, e16, m2, ta, ma353; RV64-i64-NEXT: vfwcvt.f.f.v v16, v8354; RV64-i64-NEXT: vfwcvt.f.f.v v24, v10355; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma356; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16357; RV64-i64-NEXT: vfwcvt.x.f.v v16, v24358; RV64-i64-NEXT: ret359 %a = call <vscale x 16 x iXLen> @llvm.lrint.nxv16iXLen.nxv16f16(<vscale x 16 x half> %x)360 ret <vscale x 16 x iXLen> %a361}362 363define <vscale x 1 x iXLen> @lrint_nxv1bf16(<vscale x 1 x bfloat> %x) {364; RV32-LABEL: lrint_nxv1bf16:365; RV32: # %bb.0:366; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma367; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8368; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma369; RV32-NEXT: vfcvt.x.f.v v8, v9370; RV32-NEXT: ret371;372; RV64-i32-LABEL: lrint_nxv1bf16:373; RV64-i32: # %bb.0:374; RV64-i32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma375; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8376; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma377; RV64-i32-NEXT: vfcvt.x.f.v v8, v9378; RV64-i32-NEXT: ret379;380; RV64-i64-LABEL: lrint_nxv1bf16:381; RV64-i64: # %bb.0:382; RV64-i64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma383; RV64-i64-NEXT: vfwcvtbf16.f.f.v v9, v8384; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma385; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9386; RV64-i64-NEXT: ret387 %a = call <vscale x 1 x iXLen> @llvm.lrint.nxv1iXLen.nxv1bf16(<vscale x 1 x bfloat> %x)388 ret <vscale x 1 x iXLen> %a389}390 391define <vscale x 2 x iXLen> @lrint_nxv2bf16(<vscale x 2 x bfloat> %x) {392; RV32-LABEL: lrint_nxv2bf16:393; RV32: # %bb.0:394; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, ma395; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8396; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma397; RV32-NEXT: vfcvt.x.f.v v8, v9398; RV32-NEXT: ret399;400; RV64-i32-LABEL: lrint_nxv2bf16:401; RV64-i32: # %bb.0:402; RV64-i32-NEXT: vsetvli a0, zero, e16, mf2, ta, ma403; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8404; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma405; RV64-i32-NEXT: vfcvt.x.f.v v8, v9406; RV64-i32-NEXT: ret407;408; RV64-i64-LABEL: lrint_nxv2bf16:409; RV64-i64: # %bb.0:410; RV64-i64-NEXT: vsetvli a0, zero, e16, mf2, ta, ma411; RV64-i64-NEXT: vfwcvtbf16.f.f.v v10, v8412; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma413; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10414; RV64-i64-NEXT: ret415 %a = call <vscale x 2 x iXLen> @llvm.lrint.nxv2iXLen.nxv2bf16(<vscale x 2 x bfloat> %x)416 ret <vscale x 2 x iXLen> %a417}418 419define <vscale x 4 x iXLen> @lrint_nxv4bf16(<vscale x 4 x bfloat> %x) {420; RV32-LABEL: lrint_nxv4bf16:421; RV32: # %bb.0:422; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma423; RV32-NEXT: vfwcvtbf16.f.f.v v10, v8424; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma425; RV32-NEXT: vfcvt.x.f.v v8, v10426; RV32-NEXT: ret427;428; RV64-i32-LABEL: lrint_nxv4bf16:429; RV64-i32: # %bb.0:430; RV64-i32-NEXT: vsetvli a0, zero, e16, m1, ta, ma431; RV64-i32-NEXT: vfwcvtbf16.f.f.v v10, v8432; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma433; RV64-i32-NEXT: vfcvt.x.f.v v8, v10434; RV64-i32-NEXT: ret435;436; RV64-i64-LABEL: lrint_nxv4bf16:437; RV64-i64: # %bb.0:438; RV64-i64-NEXT: vsetvli a0, zero, e16, m1, ta, ma439; RV64-i64-NEXT: vfwcvtbf16.f.f.v v12, v8440; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma441; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12442; RV64-i64-NEXT: ret443 %a = call <vscale x 4 x iXLen> @llvm.lrint.nxv4iXLen.nxv4bf16(<vscale x 4 x bfloat> %x)444 ret <vscale x 4 x iXLen> %a445}446 447define <vscale x 8 x iXLen> @lrint_nxv8bf16(<vscale x 8 x bfloat> %x) {448; RV32-LABEL: lrint_nxv8bf16:449; RV32: # %bb.0:450; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, ma451; RV32-NEXT: vfwcvtbf16.f.f.v v12, v8452; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma453; RV32-NEXT: vfcvt.x.f.v v8, v12454; RV32-NEXT: ret455;456; RV64-i32-LABEL: lrint_nxv8bf16:457; RV64-i32: # %bb.0:458; RV64-i32-NEXT: vsetvli a0, zero, e16, m2, ta, ma459; RV64-i32-NEXT: vfwcvtbf16.f.f.v v12, v8460; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma461; RV64-i32-NEXT: vfcvt.x.f.v v8, v12462; RV64-i32-NEXT: ret463;464; RV64-i64-LABEL: lrint_nxv8bf16:465; RV64-i64: # %bb.0:466; RV64-i64-NEXT: vsetvli a0, zero, e16, m2, ta, ma467; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8468; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma469; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16470; RV64-i64-NEXT: ret471 %a = call <vscale x 8 x iXLen> @llvm.lrint.nxv8iXLen.nxv8bf16(<vscale x 8 x bfloat> %x)472 ret <vscale x 8 x iXLen> %a473}474 475define <vscale x 16 x iXLen> @lrint_nxv16bf16(<vscale x 16 x bfloat> %x) {476; RV32-LABEL: lrint_nxv16bf16:477; RV32: # %bb.0:478; RV32-NEXT: vsetvli a0, zero, e16, m4, ta, ma479; RV32-NEXT: vfwcvtbf16.f.f.v v16, v8480; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma481; RV32-NEXT: vfcvt.x.f.v v8, v16482; RV32-NEXT: ret483;484; RV64-i32-LABEL: lrint_nxv16bf16:485; RV64-i32: # %bb.0:486; RV64-i32-NEXT: vsetvli a0, zero, e16, m4, ta, ma487; RV64-i32-NEXT: vfwcvtbf16.f.f.v v16, v8488; RV64-i32-NEXT: vsetvli zero, zero, e32, m8, ta, ma489; RV64-i32-NEXT: vfcvt.x.f.v v8, v16490; RV64-i32-NEXT: ret491;492; RV64-i64-LABEL: lrint_nxv16bf16:493; RV64-i64: # %bb.0:494; RV64-i64-NEXT: vsetvli a0, zero, e16, m2, ta, ma495; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8496; RV64-i64-NEXT: vfwcvtbf16.f.f.v v24, v10497; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma498; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16499; RV64-i64-NEXT: vfwcvt.x.f.v v16, v24500; RV64-i64-NEXT: ret501 %a = call <vscale x 16 x iXLen> @llvm.lrint.nxv16iXLen.nxv16bf16(<vscale x 16 x bfloat> %x)502 ret <vscale x 16 x iXLen> %a503}504 505define <vscale x 32 x iXLen> @lrint_nxv32bf16(<vscale x 32 x bfloat> %x) {506; RV32-LABEL: lrint_nxv32bf16:507; RV32: # %bb.0:508; RV32-NEXT: vsetvli a0, zero, e16, m4, ta, ma509; RV32-NEXT: vfwcvtbf16.f.f.v v16, v8510; RV32-NEXT: vfwcvtbf16.f.f.v v24, v12511; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma512; RV32-NEXT: vfcvt.x.f.v v8, v16513; RV32-NEXT: vfcvt.x.f.v v16, v24514; RV32-NEXT: ret515;516; RV64-i32-LABEL: lrint_nxv32bf16:517; RV64-i32: # %bb.0:518; RV64-i32-NEXT: vsetvli a0, zero, e16, m4, ta, ma519; RV64-i32-NEXT: vfwcvtbf16.f.f.v v16, v8520; RV64-i32-NEXT: vfwcvtbf16.f.f.v v24, v12521; RV64-i32-NEXT: vsetvli zero, zero, e32, m8, ta, ma522; RV64-i32-NEXT: vfcvt.x.f.v v8, v16523; RV64-i32-NEXT: vfcvt.x.f.v v16, v24524; RV64-i32-NEXT: ret525;526; RV64-i64-LABEL: lrint_nxv32bf16:527; RV64-i64: # %bb.0:528; RV64-i64-NEXT: addi sp, sp, -64529; RV64-i64-NEXT: .cfi_def_cfa_offset 64530; RV64-i64-NEXT: sd ra, 56(sp) # 8-byte Folded Spill531; RV64-i64-NEXT: sd s0, 48(sp) # 8-byte Folded Spill532; RV64-i64-NEXT: sd s1, 40(sp) # 8-byte Folded Spill533; RV64-i64-NEXT: .cfi_offset ra, -8534; RV64-i64-NEXT: .cfi_offset s0, -16535; RV64-i64-NEXT: .cfi_offset s1, -24536; RV64-i64-NEXT: csrr a1, vlenb537; RV64-i64-NEXT: slli a1, a1, 5538; RV64-i64-NEXT: sub sp, sp, a1539; RV64-i64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 32 * vlenb540; RV64-i64-NEXT: mv s0, a0541; RV64-i64-NEXT: vsetvli a0, zero, e16, m2, ta, ma542; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8543; RV64-i64-NEXT: vfwcvtbf16.f.f.v v20, v10544; RV64-i64-NEXT: vfwcvtbf16.f.f.v v8, v12545; RV64-i64-NEXT: vfwcvtbf16.f.f.v v24, v14546; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma547; RV64-i64-NEXT: vfwcvt.x.f.v v0, v16548; RV64-i64-NEXT: csrr a0, vlenb549; RV64-i64-NEXT: slli a0, a0, 3550; RV64-i64-NEXT: mv a1, a0551; RV64-i64-NEXT: slli a0, a0, 1552; RV64-i64-NEXT: add a0, a0, a1553; RV64-i64-NEXT: add a0, sp, a0554; RV64-i64-NEXT: addi a0, a0, 32555; RV64-i64-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill556; RV64-i64-NEXT: vfwcvt.x.f.v v0, v20557; RV64-i64-NEXT: csrr a0, vlenb558; RV64-i64-NEXT: slli a0, a0, 4559; RV64-i64-NEXT: add a0, sp, a0560; RV64-i64-NEXT: addi a0, a0, 32561; RV64-i64-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill562; RV64-i64-NEXT: vfwcvt.x.f.v v16, v8563; RV64-i64-NEXT: csrr a0, vlenb564; RV64-i64-NEXT: slli a0, a0, 3565; RV64-i64-NEXT: add a0, sp, a0566; RV64-i64-NEXT: addi a0, a0, 32567; RV64-i64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill568; RV64-i64-NEXT: vfwcvt.x.f.v v8, v24569; RV64-i64-NEXT: addi a0, sp, 32570; RV64-i64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill571; RV64-i64-NEXT: csrr s1, vlenb572; RV64-i64-NEXT: li a1, 24573; RV64-i64-NEXT: mv a0, s1574; RV64-i64-NEXT: call __muldi3575; RV64-i64-NEXT: add a0, s0, a0576; RV64-i64-NEXT: addi a1, sp, 32577; RV64-i64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload578; RV64-i64-NEXT: vs8r.v v8, (a0)579; RV64-i64-NEXT: slli a0, s1, 4580; RV64-i64-NEXT: slli s1, s1, 3581; RV64-i64-NEXT: add a0, s0, a0582; RV64-i64-NEXT: add s1, s0, s1583; RV64-i64-NEXT: csrr a1, vlenb584; RV64-i64-NEXT: slli a1, a1, 3585; RV64-i64-NEXT: add a1, sp, a1586; RV64-i64-NEXT: addi a1, a1, 32587; RV64-i64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload588; RV64-i64-NEXT: vs8r.v v8, (a0)589; RV64-i64-NEXT: csrr a0, vlenb590; RV64-i64-NEXT: slli a0, a0, 4591; RV64-i64-NEXT: add a0, sp, a0592; RV64-i64-NEXT: addi a0, a0, 32593; RV64-i64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload594; RV64-i64-NEXT: vs8r.v v8, (s1)595; RV64-i64-NEXT: csrr a0, vlenb596; RV64-i64-NEXT: slli a0, a0, 3597; RV64-i64-NEXT: mv a1, a0598; RV64-i64-NEXT: slli a0, a0, 1599; RV64-i64-NEXT: add a0, a0, a1600; RV64-i64-NEXT: add a0, sp, a0601; RV64-i64-NEXT: addi a0, a0, 32602; RV64-i64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload603; RV64-i64-NEXT: vs8r.v v8, (s0)604; RV64-i64-NEXT: csrr a0, vlenb605; RV64-i64-NEXT: slli a0, a0, 5606; RV64-i64-NEXT: add sp, sp, a0607; RV64-i64-NEXT: .cfi_def_cfa sp, 64608; RV64-i64-NEXT: ld ra, 56(sp) # 8-byte Folded Reload609; RV64-i64-NEXT: ld s0, 48(sp) # 8-byte Folded Reload610; RV64-i64-NEXT: ld s1, 40(sp) # 8-byte Folded Reload611; RV64-i64-NEXT: .cfi_restore ra612; RV64-i64-NEXT: .cfi_restore s0613; RV64-i64-NEXT: .cfi_restore s1614; RV64-i64-NEXT: addi sp, sp, 64615; RV64-i64-NEXT: .cfi_def_cfa_offset 0616; RV64-i64-NEXT: ret617 %a = call <vscale x 32 x iXLen> @llvm.lrint.nxv32iXLen.nxv32bf16(<vscale x 32 x bfloat> %x)618 ret <vscale x 32 x iXLen> %a619}620