235 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d \3; RUN: -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV324; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \5; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i326; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \7; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i648 9define <vscale x 1 x iXLen> @lrint_nxv1f32(<vscale x 1 x float> %x, <vscale x 1 x i1> %m, i32 zeroext %evl) {10; RV32-LABEL: lrint_nxv1f32:11; RV32: # %bb.0:12; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma13; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t14; RV32-NEXT: ret15;16; RV64-i32-LABEL: lrint_nxv1f32:17; RV64-i32: # %bb.0:18; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma19; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t20; RV64-i32-NEXT: ret21;22; RV64-i64-LABEL: lrint_nxv1f32:23; RV64-i64: # %bb.0:24; RV64-i64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma25; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8, v0.t26; RV64-i64-NEXT: vmv1r.v v8, v927; RV64-i64-NEXT: ret28 %a = call <vscale x 1 x iXLen> @llvm.vp.lrint.nxv1iXLen.nxv1f32(<vscale x 1 x float> %x, <vscale x 1 x i1> %m, i32 %evl)29 ret <vscale x 1 x iXLen> %a30}31 32define <vscale x 2 x iXLen> @lrint_nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {33; RV32-LABEL: lrint_nxv2f32:34; RV32: # %bb.0:35; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma36; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t37; RV32-NEXT: ret38;39; RV64-i32-LABEL: lrint_nxv2f32:40; RV64-i32: # %bb.0:41; RV64-i32-NEXT: vsetvli zero, a0, e32, m1, ta, ma42; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t43; RV64-i32-NEXT: ret44;45; RV64-i64-LABEL: lrint_nxv2f32:46; RV64-i64: # %bb.0:47; RV64-i64-NEXT: vsetvli zero, a0, e32, m1, ta, ma48; RV64-i64-NEXT: vmv1r.v v10, v849; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10, v0.t50; RV64-i64-NEXT: ret51 %a = call <vscale x 2 x iXLen> @llvm.vp.lrint.nxv2iXLen.nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 %evl)52 ret <vscale x 2 x iXLen> %a53}54 55define <vscale x 4 x iXLen> @lrint_nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {56; RV32-LABEL: lrint_nxv4f32:57; RV32: # %bb.0:58; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma59; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t60; RV32-NEXT: ret61;62; RV64-i32-LABEL: lrint_nxv4f32:63; RV64-i32: # %bb.0:64; RV64-i32-NEXT: vsetvli zero, a0, e32, m2, ta, ma65; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t66; RV64-i32-NEXT: ret67;68; RV64-i64-LABEL: lrint_nxv4f32:69; RV64-i64: # %bb.0:70; RV64-i64-NEXT: vsetvli zero, a0, e32, m2, ta, ma71; RV64-i64-NEXT: vmv2r.v v12, v872; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12, v0.t73; RV64-i64-NEXT: ret74 %a = call <vscale x 4 x iXLen> @llvm.vp.lrint.nxv4iXLen.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 %evl)75 ret <vscale x 4 x iXLen> %a76}77 78define <vscale x 8 x iXLen> @lrint_nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {79; RV32-LABEL: lrint_nxv8f32:80; RV32: # %bb.0:81; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma82; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t83; RV32-NEXT: ret84;85; RV64-i32-LABEL: lrint_nxv8f32:86; RV64-i32: # %bb.0:87; RV64-i32-NEXT: vsetvli zero, a0, e32, m4, ta, ma88; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t89; RV64-i32-NEXT: ret90;91; RV64-i64-LABEL: lrint_nxv8f32:92; RV64-i64: # %bb.0:93; RV64-i64-NEXT: vsetvli zero, a0, e32, m4, ta, ma94; RV64-i64-NEXT: vmv4r.v v16, v895; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16, v0.t96; RV64-i64-NEXT: ret97 %a = call <vscale x 8 x iXLen> @llvm.vp.lrint.nxv8iXLen.nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 %evl)98 ret <vscale x 8 x iXLen> %a99}100 101define <vscale x 16 x iXLen> @lrint_nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 zeroext %evl) {102; RV32-LABEL: lrint_nxv16f32:103; RV32: # %bb.0:104; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma105; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t106; RV32-NEXT: ret107;108; RV64-i32-LABEL: lrint_nxv16f32:109; RV64-i32: # %bb.0:110; RV64-i32-NEXT: vsetvli zero, a0, e32, m8, ta, ma111; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t112; RV64-i32-NEXT: ret113;114; RV64-i64-LABEL: lrint_nxv16f32:115; RV64-i64: # %bb.0:116; RV64-i64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma117; RV64-i64-NEXT: vmv1r.v v24, v0118; RV64-i64-NEXT: csrr a1, vlenb119; RV64-i64-NEXT: srli a2, a1, 3120; RV64-i64-NEXT: sub a3, a0, a1121; RV64-i64-NEXT: vslidedown.vx v0, v0, a2122; RV64-i64-NEXT: sltu a2, a0, a3123; RV64-i64-NEXT: addi a2, a2, -1124; RV64-i64-NEXT: and a2, a2, a3125; RV64-i64-NEXT: vsetvli zero, a2, e32, m4, ta, ma126; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12, v0.t127; RV64-i64-NEXT: bltu a0, a1, .LBB4_2128; RV64-i64-NEXT: # %bb.1:129; RV64-i64-NEXT: mv a0, a1130; RV64-i64-NEXT: .LBB4_2:131; RV64-i64-NEXT: vmv1r.v v0, v24132; RV64-i64-NEXT: vsetvli zero, a0, e32, m4, ta, ma133; RV64-i64-NEXT: vfwcvt.x.f.v v24, v8, v0.t134; RV64-i64-NEXT: vmv8r.v v8, v24135; RV64-i64-NEXT: ret136 %a = call <vscale x 16 x iXLen> @llvm.vp.lrint.nxv16iXLen.nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 %evl)137 ret <vscale x 16 x iXLen> %a138}139 140define <vscale x 1 x iXLen> @lrint_nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x i1> %m, i32 zeroext %evl) {141; RV32-LABEL: lrint_nxv1f64:142; RV32: # %bb.0:143; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma144; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t145; RV32-NEXT: vmv1r.v v8, v9146; RV32-NEXT: ret147;148; RV64-i32-LABEL: lrint_nxv1f64:149; RV64-i32: # %bb.0:150; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma151; RV64-i32-NEXT: vfncvt.x.f.w v9, v8, v0.t152; RV64-i32-NEXT: vmv1r.v v8, v9153; RV64-i32-NEXT: ret154;155; RV64-i64-LABEL: lrint_nxv1f64:156; RV64-i64: # %bb.0:157; RV64-i64-NEXT: vsetvli zero, a0, e64, m1, ta, ma158; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t159; RV64-i64-NEXT: ret160 %a = call <vscale x 1 x iXLen> @llvm.vp.lrint.nxv1iXLen.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x i1> %m, i32 %evl)161 ret <vscale x 1 x iXLen> %a162}163 164define <vscale x 2 x iXLen> @lrint_nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {165; RV32-LABEL: lrint_nxv2f64:166; RV32: # %bb.0:167; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma168; RV32-NEXT: vfncvt.x.f.w v10, v8, v0.t169; RV32-NEXT: vmv.v.v v8, v10170; RV32-NEXT: ret171;172; RV64-i32-LABEL: lrint_nxv2f64:173; RV64-i32: # %bb.0:174; RV64-i32-NEXT: vsetvli zero, a0, e32, m1, ta, ma175; RV64-i32-NEXT: vfncvt.x.f.w v10, v8, v0.t176; RV64-i32-NEXT: vmv.v.v v8, v10177; RV64-i32-NEXT: ret178;179; RV64-i64-LABEL: lrint_nxv2f64:180; RV64-i64: # %bb.0:181; RV64-i64-NEXT: vsetvli zero, a0, e64, m2, ta, ma182; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t183; RV64-i64-NEXT: ret184 %a = call <vscale x 2 x iXLen> @llvm.vp.lrint.nxv2iXLen.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 %evl)185 ret <vscale x 2 x iXLen> %a186}187 188define <vscale x 4 x iXLen> @lrint_nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {189; RV32-LABEL: lrint_nxv4f64:190; RV32: # %bb.0:191; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma192; RV32-NEXT: vfncvt.x.f.w v12, v8, v0.t193; RV32-NEXT: vmv.v.v v8, v12194; RV32-NEXT: ret195;196; RV64-i32-LABEL: lrint_nxv4f64:197; RV64-i32: # %bb.0:198; RV64-i32-NEXT: vsetvli zero, a0, e32, m2, ta, ma199; RV64-i32-NEXT: vfncvt.x.f.w v12, v8, v0.t200; RV64-i32-NEXT: vmv.v.v v8, v12201; RV64-i32-NEXT: ret202;203; RV64-i64-LABEL: lrint_nxv4f64:204; RV64-i64: # %bb.0:205; RV64-i64-NEXT: vsetvli zero, a0, e64, m4, ta, ma206; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t207; RV64-i64-NEXT: ret208 %a = call <vscale x 4 x iXLen> @llvm.vp.lrint.nxv4iXLen.nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 %evl)209 ret <vscale x 4 x iXLen> %a210}211 212define <vscale x 8 x iXLen> @lrint_nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {213; RV32-LABEL: lrint_nxv8f64:214; RV32: # %bb.0:215; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma216; RV32-NEXT: vfncvt.x.f.w v16, v8, v0.t217; RV32-NEXT: vmv.v.v v8, v16218; RV32-NEXT: ret219;220; RV64-i32-LABEL: lrint_nxv8f64:221; RV64-i32: # %bb.0:222; RV64-i32-NEXT: vsetvli zero, a0, e32, m4, ta, ma223; RV64-i32-NEXT: vfncvt.x.f.w v16, v8, v0.t224; RV64-i32-NEXT: vmv.v.v v8, v16225; RV64-i32-NEXT: ret226;227; RV64-i64-LABEL: lrint_nxv8f64:228; RV64-i64: # %bb.0:229; RV64-i64-NEXT: vsetvli zero, a0, e64, m8, ta, ma230; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t231; RV64-i64-NEXT: ret232 %a = call <vscale x 8 x iXLen> @llvm.vp.lrint.nxv8iXLen.nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 %evl)233 ret <vscale x 8 x iXLen> %a234}235