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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \3; RUN: -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV324; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \5; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i326; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin \7; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i648 9define <vscale x 1 x iXLen> @lround_nxv1f32(<vscale x 1 x float> %x) {10; RV32-LABEL: lround_nxv1f32:11; RV32: # %bb.0:12; RV32-NEXT: fsrmi a0, 413; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma14; RV32-NEXT: vfcvt.x.f.v v8, v815; RV32-NEXT: fsrm a016; RV32-NEXT: ret17;18; RV64-i32-LABEL: lround_nxv1f32:19; RV64-i32: # %bb.0:20; RV64-i32-NEXT: fsrmi a0, 421; RV64-i32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma22; RV64-i32-NEXT: vfcvt.x.f.v v8, v823; RV64-i32-NEXT: fsrm a024; RV64-i32-NEXT: ret25;26; RV64-i64-LABEL: lround_nxv1f32:27; RV64-i64: # %bb.0:28; RV64-i64-NEXT: fsrmi a0, 429; RV64-i64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma30; RV64-i64-NEXT: vfwcvt.x.f.v v9, v831; RV64-i64-NEXT: fsrm a032; RV64-i64-NEXT: vmv1r.v v8, v933; RV64-i64-NEXT: ret34 %a = call <vscale x 1 x iXLen> @llvm.lround.nxv1iXLen.nxv1f32(<vscale x 1 x float> %x)35 ret <vscale x 1 x iXLen> %a36}37 38define <vscale x 2 x iXLen> @lround_nxv2f32(<vscale x 2 x float> %x) {39; RV32-LABEL: lround_nxv2f32:40; RV32: # %bb.0:41; RV32-NEXT: fsrmi a0, 442; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma43; RV32-NEXT: vfcvt.x.f.v v8, v844; RV32-NEXT: fsrm a045; RV32-NEXT: ret46;47; RV64-i32-LABEL: lround_nxv2f32:48; RV64-i32: # %bb.0:49; RV64-i32-NEXT: fsrmi a0, 450; RV64-i32-NEXT: vsetvli a1, zero, e32, m1, ta, ma51; RV64-i32-NEXT: vfcvt.x.f.v v8, v852; RV64-i32-NEXT: fsrm a053; RV64-i32-NEXT: ret54;55; RV64-i64-LABEL: lround_nxv2f32:56; RV64-i64: # %bb.0:57; RV64-i64-NEXT: vsetvli a0, zero, e32, m1, ta, ma58; RV64-i64-NEXT: vmv1r.v v10, v859; RV64-i64-NEXT: fsrmi a0, 460; RV64-i64-NEXT: vfwcvt.x.f.v v8, v1061; RV64-i64-NEXT: fsrm a062; RV64-i64-NEXT: ret63 %a = call <vscale x 2 x iXLen> @llvm.lround.nxv2iXLen.nxv2f32(<vscale x 2 x float> %x)64 ret <vscale x 2 x iXLen> %a65}66 67define <vscale x 4 x iXLen> @lround_nxv4f32(<vscale x 4 x float> %x) {68; RV32-LABEL: lround_nxv4f32:69; RV32: # %bb.0:70; RV32-NEXT: fsrmi a0, 471; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma72; RV32-NEXT: vfcvt.x.f.v v8, v873; RV32-NEXT: fsrm a074; RV32-NEXT: ret75;76; RV64-i32-LABEL: lround_nxv4f32:77; RV64-i32: # %bb.0:78; RV64-i32-NEXT: fsrmi a0, 479; RV64-i32-NEXT: vsetvli a1, zero, e32, m2, ta, ma80; RV64-i32-NEXT: vfcvt.x.f.v v8, v881; RV64-i32-NEXT: fsrm a082; RV64-i32-NEXT: ret83;84; RV64-i64-LABEL: lround_nxv4f32:85; RV64-i64: # %bb.0:86; RV64-i64-NEXT: vsetvli a0, zero, e32, m2, ta, ma87; RV64-i64-NEXT: vmv2r.v v12, v888; RV64-i64-NEXT: fsrmi a0, 489; RV64-i64-NEXT: vfwcvt.x.f.v v8, v1290; RV64-i64-NEXT: fsrm a091; RV64-i64-NEXT: ret92 %a = call <vscale x 4 x iXLen> @llvm.lround.nxv4iXLen.nxv4f32(<vscale x 4 x float> %x)93 ret <vscale x 4 x iXLen> %a94}95 96define <vscale x 8 x iXLen> @lround_nxv8f32(<vscale x 8 x float> %x) {97; RV32-LABEL: lround_nxv8f32:98; RV32: # %bb.0:99; RV32-NEXT: fsrmi a0, 4100; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma101; RV32-NEXT: vfcvt.x.f.v v8, v8102; RV32-NEXT: fsrm a0103; RV32-NEXT: ret104;105; RV64-i32-LABEL: lround_nxv8f32:106; RV64-i32: # %bb.0:107; RV64-i32-NEXT: fsrmi a0, 4108; RV64-i32-NEXT: vsetvli a1, zero, e32, m4, ta, ma109; RV64-i32-NEXT: vfcvt.x.f.v v8, v8110; RV64-i32-NEXT: fsrm a0111; RV64-i32-NEXT: ret112;113; RV64-i64-LABEL: lround_nxv8f32:114; RV64-i64: # %bb.0:115; RV64-i64-NEXT: vsetvli a0, zero, e32, m4, ta, ma116; RV64-i64-NEXT: vmv4r.v v16, v8117; RV64-i64-NEXT: fsrmi a0, 4118; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16119; RV64-i64-NEXT: fsrm a0120; RV64-i64-NEXT: ret121 %a = call <vscale x 8 x iXLen> @llvm.lround.nxv8iXLen.nxv8f32(<vscale x 8 x float> %x)122 ret <vscale x 8 x iXLen> %a123}124 125define <vscale x 16 x iXLen> @lround_nxv16f32(<vscale x 16 x float> %x) {126; RV32-LABEL: lround_nxv16f32:127; RV32: # %bb.0:128; RV32-NEXT: fsrmi a0, 4129; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma130; RV32-NEXT: vfcvt.x.f.v v8, v8131; RV32-NEXT: fsrm a0132; RV32-NEXT: ret133;134; RV64-i32-LABEL: lround_nxv16f32:135; RV64-i32: # %bb.0:136; RV64-i32-NEXT: fsrmi a0, 4137; RV64-i32-NEXT: vsetvli a1, zero, e32, m8, ta, ma138; RV64-i32-NEXT: vfcvt.x.f.v v8, v8139; RV64-i32-NEXT: fsrm a0140; RV64-i32-NEXT: ret141;142; RV64-i64-LABEL: lround_nxv16f32:143; RV64-i64: # %bb.0:144; RV64-i64-NEXT: fsrmi a0, 4145; RV64-i64-NEXT: vsetvli a1, zero, e32, m4, ta, ma146; RV64-i64-NEXT: vfwcvt.x.f.v v24, v8147; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12148; RV64-i64-NEXT: fsrm a0149; RV64-i64-NEXT: vmv8r.v v8, v24150; RV64-i64-NEXT: ret151 %a = call <vscale x 16 x iXLen> @llvm.lround.nxv16iXLen.nxv16f32(<vscale x 16 x float> %x)152 ret <vscale x 16 x iXLen> %a153}154 155define <vscale x 1 x iXLen> @lround_nxv1f64(<vscale x 1 x double> %x) {156; RV32-LABEL: lround_nxv1f64:157; RV32: # %bb.0:158; RV32-NEXT: fsrmi a0, 4159; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma160; RV32-NEXT: vfncvt.x.f.w v9, v8161; RV32-NEXT: fsrm a0162; RV32-NEXT: vmv1r.v v8, v9163; RV32-NEXT: ret164;165; RV64-i32-LABEL: lround_nxv1f64:166; RV64-i32: # %bb.0:167; RV64-i32-NEXT: fsrmi a0, 4168; RV64-i32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma169; RV64-i32-NEXT: vfncvt.x.f.w v9, v8170; RV64-i32-NEXT: fsrm a0171; RV64-i32-NEXT: vmv1r.v v8, v9172; RV64-i32-NEXT: ret173;174; RV64-i64-LABEL: lround_nxv1f64:175; RV64-i64: # %bb.0:176; RV64-i64-NEXT: fsrmi a0, 4177; RV64-i64-NEXT: vsetvli a1, zero, e64, m1, ta, ma178; RV64-i64-NEXT: vfcvt.x.f.v v8, v8179; RV64-i64-NEXT: fsrm a0180; RV64-i64-NEXT: ret181 %a = call <vscale x 1 x iXLen> @llvm.lround.nxv1iXLen.nxv1f64(<vscale x 1 x double> %x)182 ret <vscale x 1 x iXLen> %a183}184 185define <vscale x 2 x iXLen> @lround_nxv2f64(<vscale x 2 x double> %x) {186; RV32-LABEL: lround_nxv2f64:187; RV32: # %bb.0:188; RV32-NEXT: fsrmi a0, 4189; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma190; RV32-NEXT: vfncvt.x.f.w v10, v8191; RV32-NEXT: fsrm a0192; RV32-NEXT: vmv.v.v v8, v10193; RV32-NEXT: ret194;195; RV64-i32-LABEL: lround_nxv2f64:196; RV64-i32: # %bb.0:197; RV64-i32-NEXT: fsrmi a0, 4198; RV64-i32-NEXT: vsetvli a1, zero, e32, m1, ta, ma199; RV64-i32-NEXT: vfncvt.x.f.w v10, v8200; RV64-i32-NEXT: fsrm a0201; RV64-i32-NEXT: vmv.v.v v8, v10202; RV64-i32-NEXT: ret203;204; RV64-i64-LABEL: lround_nxv2f64:205; RV64-i64: # %bb.0:206; RV64-i64-NEXT: fsrmi a0, 4207; RV64-i64-NEXT: vsetvli a1, zero, e64, m2, ta, ma208; RV64-i64-NEXT: vfcvt.x.f.v v8, v8209; RV64-i64-NEXT: fsrm a0210; RV64-i64-NEXT: ret211 %a = call <vscale x 2 x iXLen> @llvm.lround.nxv2iXLen.nxv2f64(<vscale x 2 x double> %x)212 ret <vscale x 2 x iXLen> %a213}214 215define <vscale x 4 x iXLen> @lround_nxv4f64(<vscale x 4 x double> %x) {216; RV32-LABEL: lround_nxv4f64:217; RV32: # %bb.0:218; RV32-NEXT: fsrmi a0, 4219; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma220; RV32-NEXT: vfncvt.x.f.w v12, v8221; RV32-NEXT: fsrm a0222; RV32-NEXT: vmv.v.v v8, v12223; RV32-NEXT: ret224;225; RV64-i32-LABEL: lround_nxv4f64:226; RV64-i32: # %bb.0:227; RV64-i32-NEXT: fsrmi a0, 4228; RV64-i32-NEXT: vsetvli a1, zero, e32, m2, ta, ma229; RV64-i32-NEXT: vfncvt.x.f.w v12, v8230; RV64-i32-NEXT: fsrm a0231; RV64-i32-NEXT: vmv.v.v v8, v12232; RV64-i32-NEXT: ret233;234; RV64-i64-LABEL: lround_nxv4f64:235; RV64-i64: # %bb.0:236; RV64-i64-NEXT: fsrmi a0, 4237; RV64-i64-NEXT: vsetvli a1, zero, e64, m4, ta, ma238; RV64-i64-NEXT: vfcvt.x.f.v v8, v8239; RV64-i64-NEXT: fsrm a0240; RV64-i64-NEXT: ret241 %a = call <vscale x 4 x iXLen> @llvm.lround.nxv4iXLen.nxv4f64(<vscale x 4 x double> %x)242 ret <vscale x 4 x iXLen> %a243}244 245define <vscale x 8 x iXLen> @lround_nxv8f64(<vscale x 8 x double> %x) {246; RV32-LABEL: lround_nxv8f64:247; RV32: # %bb.0:248; RV32-NEXT: fsrmi a0, 4249; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma250; RV32-NEXT: vfncvt.x.f.w v16, v8251; RV32-NEXT: fsrm a0252; RV32-NEXT: vmv.v.v v8, v16253; RV32-NEXT: ret254;255; RV64-i32-LABEL: lround_nxv8f64:256; RV64-i32: # %bb.0:257; RV64-i32-NEXT: fsrmi a0, 4258; RV64-i32-NEXT: vsetvli a1, zero, e32, m4, ta, ma259; RV64-i32-NEXT: vfncvt.x.f.w v16, v8260; RV64-i32-NEXT: fsrm a0261; RV64-i32-NEXT: vmv.v.v v8, v16262; RV64-i32-NEXT: ret263;264; RV64-i64-LABEL: lround_nxv8f64:265; RV64-i64: # %bb.0:266; RV64-i64-NEXT: fsrmi a0, 4267; RV64-i64-NEXT: vsetvli a1, zero, e64, m8, ta, ma268; RV64-i64-NEXT: vfcvt.x.f.v v8, v8269; RV64-i64-NEXT: fsrm a0270; RV64-i64-NEXT: ret271 %a = call <vscale x 8 x iXLen> @llvm.lround.nxv8iXLen.nxv8f64(<vscale x 8 x double> %x)272 ret <vscale x 8 x iXLen> %a273}274 275define <vscale x 1 x iXLen> @lround_nxv1f16(<vscale x 1 x half> %x) {276; RV32-LABEL: lround_nxv1f16:277; RV32: # %bb.0:278; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma279; RV32-NEXT: vfwcvt.f.f.v v9, v8280; RV32-NEXT: fsrmi a0, 4281; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma282; RV32-NEXT: vfcvt.x.f.v v8, v9283; RV32-NEXT: fsrm a0284; RV32-NEXT: ret285;286; RV64-i32-LABEL: lround_nxv1f16:287; RV64-i32: # %bb.0:288; RV64-i32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma289; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8290; RV64-i32-NEXT: fsrmi a0, 4291; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma292; RV64-i32-NEXT: vfcvt.x.f.v v8, v9293; RV64-i32-NEXT: fsrm a0294; RV64-i32-NEXT: ret295;296; RV64-i64-LABEL: lround_nxv1f16:297; RV64-i64: # %bb.0:298; RV64-i64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma299; RV64-i64-NEXT: vfwcvt.f.f.v v9, v8300; RV64-i64-NEXT: fsrmi a0, 4301; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma302; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9303; RV64-i64-NEXT: fsrm a0304; RV64-i64-NEXT: ret305 %a = call <vscale x 1 x iXLen> @llvm.lround.nxv1iXLen.nxv1f16(<vscale x 1 x half> %x)306 ret <vscale x 1 x iXLen> %a307}308 309define <vscale x 2 x iXLen> @lround_nxv2f16(<vscale x 2 x half> %x) {310; RV32-LABEL: lround_nxv2f16:311; RV32: # %bb.0:312; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, ma313; RV32-NEXT: vfwcvt.f.f.v v9, v8314; RV32-NEXT: fsrmi a0, 4315; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma316; RV32-NEXT: vfcvt.x.f.v v8, v9317; RV32-NEXT: fsrm a0318; RV32-NEXT: ret319;320; RV64-i32-LABEL: lround_nxv2f16:321; RV64-i32: # %bb.0:322; RV64-i32-NEXT: vsetvli a0, zero, e16, mf2, ta, ma323; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8324; RV64-i32-NEXT: fsrmi a0, 4325; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma326; RV64-i32-NEXT: vfcvt.x.f.v v8, v9327; RV64-i32-NEXT: fsrm a0328; RV64-i32-NEXT: ret329;330; RV64-i64-LABEL: lround_nxv2f16:331; RV64-i64: # %bb.0:332; RV64-i64-NEXT: vsetvli a0, zero, e16, mf2, ta, ma333; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8334; RV64-i64-NEXT: fsrmi a0, 4335; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma336; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10337; RV64-i64-NEXT: fsrm a0338; RV64-i64-NEXT: ret339 %a = call <vscale x 2 x iXLen> @llvm.lround.nxv2iXLen.nxv2f16(<vscale x 2 x half> %x)340 ret <vscale x 2 x iXLen> %a341}342 343define <vscale x 4 x iXLen> @lround_nxv4f16(<vscale x 4 x half> %x) {344; RV32-LABEL: lround_nxv4f16:345; RV32: # %bb.0:346; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma347; RV32-NEXT: vfwcvt.f.f.v v10, v8348; RV32-NEXT: fsrmi a0, 4349; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma350; RV32-NEXT: vfcvt.x.f.v v8, v10351; RV32-NEXT: fsrm a0352; RV32-NEXT: ret353;354; RV64-i32-LABEL: lround_nxv4f16:355; RV64-i32: # %bb.0:356; RV64-i32-NEXT: vsetvli a0, zero, e16, m1, ta, ma357; RV64-i32-NEXT: vfwcvt.f.f.v v10, v8358; RV64-i32-NEXT: fsrmi a0, 4359; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma360; RV64-i32-NEXT: vfcvt.x.f.v v8, v10361; RV64-i32-NEXT: fsrm a0362; RV64-i32-NEXT: ret363;364; RV64-i64-LABEL: lround_nxv4f16:365; RV64-i64: # %bb.0:366; RV64-i64-NEXT: vsetvli a0, zero, e16, m1, ta, ma367; RV64-i64-NEXT: vfwcvt.f.f.v v12, v8368; RV64-i64-NEXT: fsrmi a0, 4369; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma370; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12371; RV64-i64-NEXT: fsrm a0372; RV64-i64-NEXT: ret373 %a = call <vscale x 4 x iXLen> @llvm.lround.nxv4iXLen.nxv4f16(<vscale x 4 x half> %x)374 ret <vscale x 4 x iXLen> %a375}376 377define <vscale x 8 x iXLen> @lround_nxv8f16(<vscale x 8 x half> %x) {378; RV32-LABEL: lround_nxv8f16:379; RV32: # %bb.0:380; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, ma381; RV32-NEXT: vfwcvt.f.f.v v12, v8382; RV32-NEXT: fsrmi a0, 4383; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma384; RV32-NEXT: vfcvt.x.f.v v8, v12385; RV32-NEXT: fsrm a0386; RV32-NEXT: ret387;388; RV64-i32-LABEL: lround_nxv8f16:389; RV64-i32: # %bb.0:390; RV64-i32-NEXT: vsetvli a0, zero, e16, m2, ta, ma391; RV64-i32-NEXT: vfwcvt.f.f.v v12, v8392; RV64-i32-NEXT: fsrmi a0, 4393; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma394; RV64-i32-NEXT: vfcvt.x.f.v v8, v12395; RV64-i32-NEXT: fsrm a0396; RV64-i32-NEXT: ret397;398; RV64-i64-LABEL: lround_nxv8f16:399; RV64-i64: # %bb.0:400; RV64-i64-NEXT: vsetvli a0, zero, e16, m2, ta, ma401; RV64-i64-NEXT: vfwcvt.f.f.v v16, v8402; RV64-i64-NEXT: fsrmi a0, 4403; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma404; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16405; RV64-i64-NEXT: fsrm a0406; RV64-i64-NEXT: ret407 %a = call <vscale x 8 x iXLen> @llvm.lround.nxv8iXLen.nxv8f16(<vscale x 8 x half> %x)408 ret <vscale x 8 x iXLen> %a409}410 411define <vscale x 16 x iXLen> @lround_nxv16f16(<vscale x 16 x half> %x) {412; RV32-LABEL: lround_nxv16f16:413; RV32: # %bb.0:414; RV32-NEXT: vsetvli a0, zero, e16, m4, ta, ma415; RV32-NEXT: vfwcvt.f.f.v v16, v8416; RV32-NEXT: fsrmi a0, 4417; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma418; RV32-NEXT: vfcvt.x.f.v v8, v16419; RV32-NEXT: fsrm a0420; RV32-NEXT: ret421;422; RV64-i32-LABEL: lround_nxv16f16:423; RV64-i32: # %bb.0:424; RV64-i32-NEXT: vsetvli a0, zero, e16, m4, ta, ma425; RV64-i32-NEXT: vfwcvt.f.f.v v16, v8426; RV64-i32-NEXT: fsrmi a0, 4427; RV64-i32-NEXT: vsetvli zero, zero, e32, m8, ta, ma428; RV64-i32-NEXT: vfcvt.x.f.v v8, v16429; RV64-i32-NEXT: fsrm a0430; RV64-i32-NEXT: ret431;432; RV64-i64-LABEL: lround_nxv16f16:433; RV64-i64: # %bb.0:434; RV64-i64-NEXT: vsetvli a0, zero, e16, m2, ta, ma435; RV64-i64-NEXT: vfwcvt.f.f.v v16, v8436; RV64-i64-NEXT: fsrmi a0, 4437; RV64-i64-NEXT: vfwcvt.f.f.v v24, v10438; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma439; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16440; RV64-i64-NEXT: vfwcvt.x.f.v v16, v24441; RV64-i64-NEXT: fsrm a0442; RV64-i64-NEXT: ret443 %a = call <vscale x 16 x iXLen> @llvm.lround.nxv16iXLen.nxv16f16(<vscale x 16 x half> %x)444 ret <vscale x 16 x iXLen> %a445}446 447define <vscale x 1 x iXLen> @lround_nxv1bf16(<vscale x 1 x bfloat> %x) {448; RV32-LABEL: lround_nxv1bf16:449; RV32: # %bb.0:450; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma451; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8452; RV32-NEXT: fsrmi a0, 4453; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma454; RV32-NEXT: vfcvt.x.f.v v8, v9455; RV32-NEXT: fsrm a0456; RV32-NEXT: ret457;458; RV64-i32-LABEL: lround_nxv1bf16:459; RV64-i32: # %bb.0:460; RV64-i32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma461; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8462; RV64-i32-NEXT: fsrmi a0, 4463; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma464; RV64-i32-NEXT: vfcvt.x.f.v v8, v9465; RV64-i32-NEXT: fsrm a0466; RV64-i32-NEXT: ret467;468; RV64-i64-LABEL: lround_nxv1bf16:469; RV64-i64: # %bb.0:470; RV64-i64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma471; RV64-i64-NEXT: vfwcvtbf16.f.f.v v9, v8472; RV64-i64-NEXT: fsrmi a0, 4473; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma474; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9475; RV64-i64-NEXT: fsrm a0476; RV64-i64-NEXT: ret477 %a = call <vscale x 1 x iXLen> @llvm.lround.nxv1iXLen.nxv1bf16(<vscale x 1 x bfloat> %x)478 ret <vscale x 1 x iXLen> %a479}480 481define <vscale x 2 x iXLen> @lround_nxv2bf16(<vscale x 2 x bfloat> %x) {482; RV32-LABEL: lround_nxv2bf16:483; RV32: # %bb.0:484; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, ma485; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8486; RV32-NEXT: fsrmi a0, 4487; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma488; RV32-NEXT: vfcvt.x.f.v v8, v9489; RV32-NEXT: fsrm a0490; RV32-NEXT: ret491;492; RV64-i32-LABEL: lround_nxv2bf16:493; RV64-i32: # %bb.0:494; RV64-i32-NEXT: vsetvli a0, zero, e16, mf2, ta, ma495; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8496; RV64-i32-NEXT: fsrmi a0, 4497; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma498; RV64-i32-NEXT: vfcvt.x.f.v v8, v9499; RV64-i32-NEXT: fsrm a0500; RV64-i32-NEXT: ret501;502; RV64-i64-LABEL: lround_nxv2bf16:503; RV64-i64: # %bb.0:504; RV64-i64-NEXT: vsetvli a0, zero, e16, mf2, ta, ma505; RV64-i64-NEXT: vfwcvtbf16.f.f.v v10, v8506; RV64-i64-NEXT: fsrmi a0, 4507; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma508; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10509; RV64-i64-NEXT: fsrm a0510; RV64-i64-NEXT: ret511 %a = call <vscale x 2 x iXLen> @llvm.lround.nxv2iXLen.nxv2bf16(<vscale x 2 x bfloat> %x)512 ret <vscale x 2 x iXLen> %a513}514 515define <vscale x 4 x iXLen> @lround_nxv4bf16(<vscale x 4 x bfloat> %x) {516; RV32-LABEL: lround_nxv4bf16:517; RV32: # %bb.0:518; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma519; RV32-NEXT: vfwcvtbf16.f.f.v v10, v8520; RV32-NEXT: fsrmi a0, 4521; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma522; RV32-NEXT: vfcvt.x.f.v v8, v10523; RV32-NEXT: fsrm a0524; RV32-NEXT: ret525;526; RV64-i32-LABEL: lround_nxv4bf16:527; RV64-i32: # %bb.0:528; RV64-i32-NEXT: vsetvli a0, zero, e16, m1, ta, ma529; RV64-i32-NEXT: vfwcvtbf16.f.f.v v10, v8530; RV64-i32-NEXT: fsrmi a0, 4531; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma532; RV64-i32-NEXT: vfcvt.x.f.v v8, v10533; RV64-i32-NEXT: fsrm a0534; RV64-i32-NEXT: ret535;536; RV64-i64-LABEL: lround_nxv4bf16:537; RV64-i64: # %bb.0:538; RV64-i64-NEXT: vsetvli a0, zero, e16, m1, ta, ma539; RV64-i64-NEXT: vfwcvtbf16.f.f.v v12, v8540; RV64-i64-NEXT: fsrmi a0, 4541; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma542; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12543; RV64-i64-NEXT: fsrm a0544; RV64-i64-NEXT: ret545 %a = call <vscale x 4 x iXLen> @llvm.lround.nxv4iXLen.nxv4bf16(<vscale x 4 x bfloat> %x)546 ret <vscale x 4 x iXLen> %a547}548 549define <vscale x 8 x iXLen> @lround_nxv8bf16(<vscale x 8 x bfloat> %x) {550; RV32-LABEL: lround_nxv8bf16:551; RV32: # %bb.0:552; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, ma553; RV32-NEXT: vfwcvtbf16.f.f.v v12, v8554; RV32-NEXT: fsrmi a0, 4555; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma556; RV32-NEXT: vfcvt.x.f.v v8, v12557; RV32-NEXT: fsrm a0558; RV32-NEXT: ret559;560; RV64-i32-LABEL: lround_nxv8bf16:561; RV64-i32: # %bb.0:562; RV64-i32-NEXT: vsetvli a0, zero, e16, m2, ta, ma563; RV64-i32-NEXT: vfwcvtbf16.f.f.v v12, v8564; RV64-i32-NEXT: fsrmi a0, 4565; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma566; RV64-i32-NEXT: vfcvt.x.f.v v8, v12567; RV64-i32-NEXT: fsrm a0568; RV64-i32-NEXT: ret569;570; RV64-i64-LABEL: lround_nxv8bf16:571; RV64-i64: # %bb.0:572; RV64-i64-NEXT: vsetvli a0, zero, e16, m2, ta, ma573; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8574; RV64-i64-NEXT: fsrmi a0, 4575; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma576; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16577; RV64-i64-NEXT: fsrm a0578; RV64-i64-NEXT: ret579 %a = call <vscale x 8 x iXLen> @llvm.lround.nxv8iXLen.nxv8bf16(<vscale x 8 x bfloat> %x)580 ret <vscale x 8 x iXLen> %a581}582 583define <vscale x 16 x iXLen> @lround_nxv16bf16(<vscale x 16 x bfloat> %x) {584; RV32-LABEL: lround_nxv16bf16:585; RV32: # %bb.0:586; RV32-NEXT: vsetvli a0, zero, e16, m4, ta, ma587; RV32-NEXT: vfwcvtbf16.f.f.v v16, v8588; RV32-NEXT: fsrmi a0, 4589; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma590; RV32-NEXT: vfcvt.x.f.v v8, v16591; RV32-NEXT: fsrm a0592; RV32-NEXT: ret593;594; RV64-i32-LABEL: lround_nxv16bf16:595; RV64-i32: # %bb.0:596; RV64-i32-NEXT: vsetvli a0, zero, e16, m4, ta, ma597; RV64-i32-NEXT: vfwcvtbf16.f.f.v v16, v8598; RV64-i32-NEXT: fsrmi a0, 4599; RV64-i32-NEXT: vsetvli zero, zero, e32, m8, ta, ma600; RV64-i32-NEXT: vfcvt.x.f.v v8, v16601; RV64-i32-NEXT: fsrm a0602; RV64-i32-NEXT: ret603;604; RV64-i64-LABEL: lround_nxv16bf16:605; RV64-i64: # %bb.0:606; RV64-i64-NEXT: vsetvli a0, zero, e16, m2, ta, ma607; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8608; RV64-i64-NEXT: fsrmi a0, 4609; RV64-i64-NEXT: vfwcvtbf16.f.f.v v24, v10610; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma611; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16612; RV64-i64-NEXT: vfwcvt.x.f.v v16, v24613; RV64-i64-NEXT: fsrm a0614; RV64-i64-NEXT: ret615 %a = call <vscale x 16 x iXLen> @llvm.lround.nxv16iXLen.nxv16bf16(<vscale x 16 x bfloat> %x)616 ret <vscale x 16 x iXLen> %a617}618 619define <vscale x 32 x iXLen> @lround_nxv32bf16(<vscale x 32 x bfloat> %x) {620; RV32-LABEL: lround_nxv32bf16:621; RV32: # %bb.0:622; RV32-NEXT: vsetvli a0, zero, e16, m4, ta, ma623; RV32-NEXT: vfwcvtbf16.f.f.v v16, v8624; RV32-NEXT: fsrmi a0, 4625; RV32-NEXT: vfwcvtbf16.f.f.v v24, v12626; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma627; RV32-NEXT: vfcvt.x.f.v v8, v16628; RV32-NEXT: vfcvt.x.f.v v16, v24629; RV32-NEXT: fsrm a0630; RV32-NEXT: ret631;632; RV64-i32-LABEL: lround_nxv32bf16:633; RV64-i32: # %bb.0:634; RV64-i32-NEXT: vsetvli a0, zero, e16, m4, ta, ma635; RV64-i32-NEXT: vfwcvtbf16.f.f.v v16, v8636; RV64-i32-NEXT: fsrmi a0, 4637; RV64-i32-NEXT: vfwcvtbf16.f.f.v v24, v12638; RV64-i32-NEXT: vsetvli zero, zero, e32, m8, ta, ma639; RV64-i32-NEXT: vfcvt.x.f.v v8, v16640; RV64-i32-NEXT: vfcvt.x.f.v v16, v24641; RV64-i32-NEXT: fsrm a0642; RV64-i32-NEXT: ret643;644; RV64-i64-LABEL: lround_nxv32bf16:645; RV64-i64: # %bb.0:646; RV64-i64-NEXT: addi sp, sp, -64647; RV64-i64-NEXT: .cfi_def_cfa_offset 64648; RV64-i64-NEXT: sd ra, 56(sp) # 8-byte Folded Spill649; RV64-i64-NEXT: sd s0, 48(sp) # 8-byte Folded Spill650; RV64-i64-NEXT: sd s1, 40(sp) # 8-byte Folded Spill651; RV64-i64-NEXT: .cfi_offset ra, -8652; RV64-i64-NEXT: .cfi_offset s0, -16653; RV64-i64-NEXT: .cfi_offset s1, -24654; RV64-i64-NEXT: csrr a1, vlenb655; RV64-i64-NEXT: slli a1, a1, 5656; RV64-i64-NEXT: sub sp, sp, a1657; RV64-i64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 32 * vlenb658; RV64-i64-NEXT: mv s0, a0659; RV64-i64-NEXT: vsetvli a0, zero, e16, m2, ta, ma660; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8661; RV64-i64-NEXT: fsrmi a0, 4662; RV64-i64-NEXT: vfwcvtbf16.f.f.v v20, v10663; RV64-i64-NEXT: vfwcvtbf16.f.f.v v8, v12664; RV64-i64-NEXT: vfwcvtbf16.f.f.v v24, v14665; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma666; RV64-i64-NEXT: vfwcvt.x.f.v v0, v16667; RV64-i64-NEXT: csrr a1, vlenb668; RV64-i64-NEXT: slli a1, a1, 3669; RV64-i64-NEXT: mv a2, a1670; RV64-i64-NEXT: slli a1, a1, 1671; RV64-i64-NEXT: add a1, a1, a2672; RV64-i64-NEXT: add a1, sp, a1673; RV64-i64-NEXT: addi a1, a1, 32674; RV64-i64-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill675; RV64-i64-NEXT: vfwcvt.x.f.v v0, v20676; RV64-i64-NEXT: csrr a1, vlenb677; RV64-i64-NEXT: slli a1, a1, 4678; RV64-i64-NEXT: add a1, sp, a1679; RV64-i64-NEXT: addi a1, a1, 32680; RV64-i64-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill681; RV64-i64-NEXT: vfwcvt.x.f.v v16, v8682; RV64-i64-NEXT: csrr a1, vlenb683; RV64-i64-NEXT: slli a1, a1, 3684; RV64-i64-NEXT: add a1, sp, a1685; RV64-i64-NEXT: addi a1, a1, 32686; RV64-i64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill687; RV64-i64-NEXT: vfwcvt.x.f.v v8, v24688; RV64-i64-NEXT: addi a1, sp, 32689; RV64-i64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill690; RV64-i64-NEXT: csrr s1, vlenb691; RV64-i64-NEXT: li a1, 24692; RV64-i64-NEXT: fsrm a0693; RV64-i64-NEXT: mv a0, s1694; RV64-i64-NEXT: call __muldi3695; RV64-i64-NEXT: add a0, s0, a0696; RV64-i64-NEXT: addi a1, sp, 32697; RV64-i64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload698; RV64-i64-NEXT: vs8r.v v8, (a0)699; RV64-i64-NEXT: slli a0, s1, 4700; RV64-i64-NEXT: slli s1, s1, 3701; RV64-i64-NEXT: add a0, s0, a0702; RV64-i64-NEXT: add s1, s0, s1703; RV64-i64-NEXT: csrr a1, vlenb704; RV64-i64-NEXT: slli a1, a1, 3705; RV64-i64-NEXT: add a1, sp, a1706; RV64-i64-NEXT: addi a1, a1, 32707; RV64-i64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload708; RV64-i64-NEXT: vs8r.v v8, (a0)709; RV64-i64-NEXT: csrr a0, vlenb710; RV64-i64-NEXT: slli a0, a0, 4711; RV64-i64-NEXT: add a0, sp, a0712; RV64-i64-NEXT: addi a0, a0, 32713; RV64-i64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload714; RV64-i64-NEXT: vs8r.v v8, (s1)715; RV64-i64-NEXT: csrr a0, vlenb716; RV64-i64-NEXT: slli a0, a0, 3717; RV64-i64-NEXT: mv a1, a0718; RV64-i64-NEXT: slli a0, a0, 1719; RV64-i64-NEXT: add a0, a0, a1720; RV64-i64-NEXT: add a0, sp, a0721; RV64-i64-NEXT: addi a0, a0, 32722; RV64-i64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload723; RV64-i64-NEXT: vs8r.v v8, (s0)724; RV64-i64-NEXT: csrr a0, vlenb725; RV64-i64-NEXT: slli a0, a0, 5726; RV64-i64-NEXT: add sp, sp, a0727; RV64-i64-NEXT: .cfi_def_cfa sp, 64728; RV64-i64-NEXT: ld ra, 56(sp) # 8-byte Folded Reload729; RV64-i64-NEXT: ld s0, 48(sp) # 8-byte Folded Reload730; RV64-i64-NEXT: ld s1, 40(sp) # 8-byte Folded Reload731; RV64-i64-NEXT: .cfi_restore ra732; RV64-i64-NEXT: .cfi_restore s0733; RV64-i64-NEXT: .cfi_restore s1734; RV64-i64-NEXT: addi sp, sp, 64735; RV64-i64-NEXT: .cfi_def_cfa_offset 0736; RV64-i64-NEXT: ret737 %a = call <vscale x 32 x iXLen> @llvm.lround.nxv32iXLen.nxv32bf16(<vscale x 32 x bfloat> %x)738 ret <vscale x 32 x iXLen> %a739}740