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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <1 x i1> @and_v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 zeroext %evl) {6; CHECK-LABEL: and_v1i1:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma9; CHECK-NEXT: vmand.mm v0, v0, v810; CHECK-NEXT: ret11 %v = call <1 x i1> @llvm.vp.and.v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 %evl)12 ret <1 x i1> %v13}14 15define <2 x i1> @and_v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 zeroext %evl) {16; CHECK-LABEL: and_v2i1:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma19; CHECK-NEXT: vmand.mm v0, v0, v820; CHECK-NEXT: ret21 %v = call <2 x i1> @llvm.vp.and.v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 %evl)22 ret <2 x i1> %v23}24 25define <4 x i1> @and_v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 zeroext %evl) {26; CHECK-LABEL: and_v4i1:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma29; CHECK-NEXT: vmand.mm v0, v0, v830; CHECK-NEXT: ret31 %v = call <4 x i1> @llvm.vp.and.v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 %evl)32 ret <4 x i1> %v33}34 35define <8 x i1> @and_v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 zeroext %evl) {36; CHECK-LABEL: and_v8i1:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma39; CHECK-NEXT: vmand.mm v0, v0, v840; CHECK-NEXT: ret41 %v = call <8 x i1> @llvm.vp.and.v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 %evl)42 ret <8 x i1> %v43}44 45define <16 x i1> @and_v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 zeroext %evl) {46; CHECK-LABEL: and_v16i1:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma49; CHECK-NEXT: vmand.mm v0, v0, v850; CHECK-NEXT: ret51 %v = call <16 x i1> @llvm.vp.and.v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 %evl)52 ret <16 x i1> %v53}54 55define <vscale x 1 x i1> @and_nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 zeroext %evl) {56; CHECK-LABEL: and_nxv1i1:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma59; CHECK-NEXT: vmand.mm v0, v0, v860; CHECK-NEXT: ret61 %v = call <vscale x 1 x i1> @llvm.vp.and.nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 %evl)62 ret <vscale x 1 x i1> %v63}64 65define <vscale x 2 x i1> @and_nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 zeroext %evl) {66; CHECK-LABEL: and_nxv2i1:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma69; CHECK-NEXT: vmand.mm v0, v0, v870; CHECK-NEXT: ret71 %v = call <vscale x 2 x i1> @llvm.vp.and.nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 %evl)72 ret <vscale x 2 x i1> %v73}74 75define <vscale x 4 x i1> @and_nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 zeroext %evl) {76; CHECK-LABEL: and_nxv4i1:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma79; CHECK-NEXT: vmand.mm v0, v0, v880; CHECK-NEXT: ret81 %v = call <vscale x 4 x i1> @llvm.vp.and.nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 %evl)82 ret <vscale x 4 x i1> %v83}84 85define <vscale x 8 x i1> @and_nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 zeroext %evl) {86; CHECK-LABEL: and_nxv8i1:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma89; CHECK-NEXT: vmand.mm v0, v0, v890; CHECK-NEXT: ret91 %v = call <vscale x 8 x i1> @llvm.vp.and.nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 %evl)92 ret <vscale x 8 x i1> %v93}94 95define <vscale x 16 x i1> @and_nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 zeroext %evl) {96; CHECK-LABEL: and_nxv16i1:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma99; CHECK-NEXT: vmand.mm v0, v0, v8100; CHECK-NEXT: ret101 %v = call <vscale x 16 x i1> @llvm.vp.and.nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 %evl)102 ret <vscale x 16 x i1> %v103}104 105define <vscale x 32 x i1> @and_nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 zeroext %evl) {106; CHECK-LABEL: and_nxv32i1:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma109; CHECK-NEXT: vmand.mm v0, v0, v8110; CHECK-NEXT: ret111 %v = call <vscale x 32 x i1> @llvm.vp.and.nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 %evl)112 ret <vscale x 32 x i1> %v113}114 115define <vscale x 64 x i1> @and_nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 zeroext %evl) {116; CHECK-LABEL: and_nxv64i1:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma119; CHECK-NEXT: vmand.mm v0, v0, v8120; CHECK-NEXT: ret121 %v = call <vscale x 64 x i1> @llvm.vp.and.nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 %evl)122 ret <vscale x 64 x i1> %v123}124 125define <1 x i1> @or_v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 zeroext %evl) {126; CHECK-LABEL: or_v1i1:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma129; CHECK-NEXT: vmor.mm v0, v0, v8130; CHECK-NEXT: ret131 %v = call <1 x i1> @llvm.vp.or.v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 %evl)132 ret <1 x i1> %v133}134 135define <2 x i1> @or_v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 zeroext %evl) {136; CHECK-LABEL: or_v2i1:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma139; CHECK-NEXT: vmor.mm v0, v0, v8140; CHECK-NEXT: ret141 %v = call <2 x i1> @llvm.vp.or.v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 %evl)142 ret <2 x i1> %v143}144 145define <4 x i1> @or_v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 zeroext %evl) {146; CHECK-LABEL: or_v4i1:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma149; CHECK-NEXT: vmor.mm v0, v0, v8150; CHECK-NEXT: ret151 %v = call <4 x i1> @llvm.vp.or.v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 %evl)152 ret <4 x i1> %v153}154 155define <8 x i1> @or_v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 zeroext %evl) {156; CHECK-LABEL: or_v8i1:157; CHECK: # %bb.0:158; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma159; CHECK-NEXT: vmor.mm v0, v0, v8160; CHECK-NEXT: ret161 %v = call <8 x i1> @llvm.vp.or.v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 %evl)162 ret <8 x i1> %v163}164 165define <16 x i1> @or_v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 zeroext %evl) {166; CHECK-LABEL: or_v16i1:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma169; CHECK-NEXT: vmor.mm v0, v0, v8170; CHECK-NEXT: ret171 %v = call <16 x i1> @llvm.vp.or.v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 %evl)172 ret <16 x i1> %v173}174 175define <vscale x 1 x i1> @or_nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 zeroext %evl) {176; CHECK-LABEL: or_nxv1i1:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma179; CHECK-NEXT: vmor.mm v0, v0, v8180; CHECK-NEXT: ret181 %v = call <vscale x 1 x i1> @llvm.vp.or.nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 %evl)182 ret <vscale x 1 x i1> %v183}184 185define <vscale x 2 x i1> @or_nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 zeroext %evl) {186; CHECK-LABEL: or_nxv2i1:187; CHECK: # %bb.0:188; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma189; CHECK-NEXT: vmor.mm v0, v0, v8190; CHECK-NEXT: ret191 %v = call <vscale x 2 x i1> @llvm.vp.or.nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 %evl)192 ret <vscale x 2 x i1> %v193}194 195define <vscale x 4 x i1> @or_nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 zeroext %evl) {196; CHECK-LABEL: or_nxv4i1:197; CHECK: # %bb.0:198; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma199; CHECK-NEXT: vmor.mm v0, v0, v8200; CHECK-NEXT: ret201 %v = call <vscale x 4 x i1> @llvm.vp.or.nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 %evl)202 ret <vscale x 4 x i1> %v203}204 205define <vscale x 8 x i1> @or_nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 zeroext %evl) {206; CHECK-LABEL: or_nxv8i1:207; CHECK: # %bb.0:208; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma209; CHECK-NEXT: vmor.mm v0, v0, v8210; CHECK-NEXT: ret211 %v = call <vscale x 8 x i1> @llvm.vp.or.nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 %evl)212 ret <vscale x 8 x i1> %v213}214 215define <vscale x 16 x i1> @or_nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 zeroext %evl) {216; CHECK-LABEL: or_nxv16i1:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma219; CHECK-NEXT: vmor.mm v0, v0, v8220; CHECK-NEXT: ret221 %v = call <vscale x 16 x i1> @llvm.vp.or.nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 %evl)222 ret <vscale x 16 x i1> %v223}224 225define <vscale x 32 x i1> @or_nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 zeroext %evl) {226; CHECK-LABEL: or_nxv32i1:227; CHECK: # %bb.0:228; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma229; CHECK-NEXT: vmor.mm v0, v0, v8230; CHECK-NEXT: ret231 %v = call <vscale x 32 x i1> @llvm.vp.or.nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 %evl)232 ret <vscale x 32 x i1> %v233}234 235define <vscale x 64 x i1> @or_nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 zeroext %evl) {236; CHECK-LABEL: or_nxv64i1:237; CHECK: # %bb.0:238; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma239; CHECK-NEXT: vmor.mm v0, v0, v8240; CHECK-NEXT: ret241 %v = call <vscale x 64 x i1> @llvm.vp.or.nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 %evl)242 ret <vscale x 64 x i1> %v243}244 245define <1 x i1> @xor_v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 zeroext %evl) {246; CHECK-LABEL: xor_v1i1:247; CHECK: # %bb.0:248; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma249; CHECK-NEXT: vmxor.mm v0, v0, v8250; CHECK-NEXT: ret251 %v = call <1 x i1> @llvm.vp.xor.v1i1(<1 x i1> %b, <1 x i1> %c, <1 x i1> %a, i32 %evl)252 ret <1 x i1> %v253}254 255define <2 x i1> @xor_v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 zeroext %evl) {256; CHECK-LABEL: xor_v2i1:257; CHECK: # %bb.0:258; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma259; CHECK-NEXT: vmxor.mm v0, v0, v8260; CHECK-NEXT: ret261 %v = call <2 x i1> @llvm.vp.xor.v2i1(<2 x i1> %b, <2 x i1> %c, <2 x i1> %a, i32 %evl)262 ret <2 x i1> %v263}264 265define <4 x i1> @xor_v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 zeroext %evl) {266; CHECK-LABEL: xor_v4i1:267; CHECK: # %bb.0:268; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma269; CHECK-NEXT: vmxor.mm v0, v0, v8270; CHECK-NEXT: ret271 %v = call <4 x i1> @llvm.vp.xor.v4i1(<4 x i1> %b, <4 x i1> %c, <4 x i1> %a, i32 %evl)272 ret <4 x i1> %v273}274 275define <8 x i1> @xor_v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 zeroext %evl) {276; CHECK-LABEL: xor_v8i1:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma279; CHECK-NEXT: vmxor.mm v0, v0, v8280; CHECK-NEXT: ret281 %v = call <8 x i1> @llvm.vp.xor.v8i1(<8 x i1> %b, <8 x i1> %c, <8 x i1> %a, i32 %evl)282 ret <8 x i1> %v283}284 285define <16 x i1> @xor_v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 zeroext %evl) {286; CHECK-LABEL: xor_v16i1:287; CHECK: # %bb.0:288; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma289; CHECK-NEXT: vmxor.mm v0, v0, v8290; CHECK-NEXT: ret291 %v = call <16 x i1> @llvm.vp.xor.v16i1(<16 x i1> %b, <16 x i1> %c, <16 x i1> %a, i32 %evl)292 ret <16 x i1> %v293}294 295define <vscale x 1 x i1> @xor_nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 zeroext %evl) {296; CHECK-LABEL: xor_nxv1i1:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma299; CHECK-NEXT: vmxor.mm v0, v0, v8300; CHECK-NEXT: ret301 %v = call <vscale x 1 x i1> @llvm.vp.xor.nxv1i1(<vscale x 1 x i1> %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %a, i32 %evl)302 ret <vscale x 1 x i1> %v303}304 305define <vscale x 2 x i1> @xor_nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 zeroext %evl) {306; CHECK-LABEL: xor_nxv2i1:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma309; CHECK-NEXT: vmxor.mm v0, v0, v8310; CHECK-NEXT: ret311 %v = call <vscale x 2 x i1> @llvm.vp.xor.nxv2i1(<vscale x 2 x i1> %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %a, i32 %evl)312 ret <vscale x 2 x i1> %v313}314 315define <vscale x 4 x i1> @xor_nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 zeroext %evl) {316; CHECK-LABEL: xor_nxv4i1:317; CHECK: # %bb.0:318; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma319; CHECK-NEXT: vmxor.mm v0, v0, v8320; CHECK-NEXT: ret321 %v = call <vscale x 4 x i1> @llvm.vp.xor.nxv4i1(<vscale x 4 x i1> %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %a, i32 %evl)322 ret <vscale x 4 x i1> %v323}324 325define <vscale x 8 x i1> @xor_nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 zeroext %evl) {326; CHECK-LABEL: xor_nxv8i1:327; CHECK: # %bb.0:328; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma329; CHECK-NEXT: vmxor.mm v0, v0, v8330; CHECK-NEXT: ret331 %v = call <vscale x 8 x i1> @llvm.vp.xor.nxv8i1(<vscale x 8 x i1> %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %a, i32 %evl)332 ret <vscale x 8 x i1> %v333}334 335define <vscale x 16 x i1> @xor_nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 zeroext %evl) {336; CHECK-LABEL: xor_nxv16i1:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma339; CHECK-NEXT: vmxor.mm v0, v0, v8340; CHECK-NEXT: ret341 %v = call <vscale x 16 x i1> @llvm.vp.xor.nxv16i1(<vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %a, i32 %evl)342 ret <vscale x 16 x i1> %v343}344 345define <vscale x 32 x i1> @xor_nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 zeroext %evl) {346; CHECK-LABEL: xor_nxv32i1:347; CHECK: # %bb.0:348; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma349; CHECK-NEXT: vmxor.mm v0, v0, v8350; CHECK-NEXT: ret351 %v = call <vscale x 32 x i1> @llvm.vp.xor.nxv32i1(<vscale x 32 x i1> %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %a, i32 %evl)352 ret <vscale x 32 x i1> %v353}354 355define <vscale x 64 x i1> @xor_nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 zeroext %evl) {356; CHECK-LABEL: xor_nxv64i1:357; CHECK: # %bb.0:358; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma359; CHECK-NEXT: vmxor.mm v0, v0, v8360; CHECK-NEXT: ret361 %v = call <vscale x 64 x i1> @llvm.vp.xor.nxv64i1(<vscale x 64 x i1> %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %a, i32 %evl)362 ret <vscale x 64 x i1> %v363}364