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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i64> @masked_load_nxv1i64(ptr %a, <vscale x 1 x i1> %mask) nounwind {6; CHECK-LABEL: masked_load_nxv1i64:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma9; CHECK-NEXT: vle64.v v8, (a0), v0.t10; CHECK-NEXT: ret11 %load = call <vscale x 1 x i64> @llvm.masked.load.nxv1i64(ptr %a, i32 8, <vscale x 1 x i1> %mask, <vscale x 1 x i64> poison)12 ret <vscale x 1 x i64> %load13}14 15define <vscale x 2 x i64> @masked_load_nxv2i64(ptr %a, <vscale x 2 x i1> %mask) nounwind {16; CHECK-LABEL: masked_load_nxv2i64:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma19; CHECK-NEXT: vle64.v v8, (a0), v0.t20; CHECK-NEXT: ret21 %load = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr %a, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x i64> poison)22 ret <vscale x 2 x i64> %load23}24 25define <vscale x 4 x i64> @masked_load_nxv4i64(ptr %a, <vscale x 4 x i1> %mask) nounwind {26; CHECK-LABEL: masked_load_nxv4i64:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma29; CHECK-NEXT: vle64.v v8, (a0), v0.t30; CHECK-NEXT: ret31 %load = call <vscale x 4 x i64> @llvm.masked.load.nxv4i64(ptr %a, i32 8, <vscale x 4 x i1> %mask, <vscale x 4 x i64> poison)32 ret <vscale x 4 x i64> %load33}34 35define <vscale x 8 x i64> @masked_load_nxv8i64(ptr %a, <vscale x 8 x i1> %mask) nounwind {36; CHECK-LABEL: masked_load_nxv8i64:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma39; CHECK-NEXT: vle64.v v8, (a0), v0.t40; CHECK-NEXT: ret41 %load = call <vscale x 8 x i64> @llvm.masked.load.nxv8i64(ptr %a, i32 8, <vscale x 8 x i1> %mask, <vscale x 8 x i64> poison)42 ret <vscale x 8 x i64> %load43}44