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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V4; RUN: llc -mtriple=riscv32 -mattr=+zve32x,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE325; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE326 7define <vscale x 1 x i8> @masked_load_nxv1i8(ptr %a, <vscale x 1 x i1> %mask) nounwind {8; V-LABEL: masked_load_nxv1i8:9; V: # %bb.0:10; V-NEXT: vsetvli a1, zero, e8, mf8, ta, ma11; V-NEXT: vle8.v v8, (a0), v0.t12; V-NEXT: ret13;14; ZVE32-LABEL: masked_load_nxv1i8:15; ZVE32: # %bb.0:16; ZVE32-NEXT: csrr a1, vlenb17; ZVE32-NEXT: srli a1, a1, 318; ZVE32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma19; ZVE32-NEXT: vle8.v v8, (a0), v0.t20; ZVE32-NEXT: ret21 %load = call <vscale x 1 x i8> @llvm.masked.load.nxv1i8(ptr %a, i32 1, <vscale x 1 x i1> %mask, <vscale x 1 x i8> poison)22 ret <vscale x 1 x i8> %load23}24 25define <vscale x 1 x i8> @masked_load_passthru_nxv1i8(ptr %a, <vscale x 1 x i1> %mask) nounwind {26; V-LABEL: masked_load_passthru_nxv1i8:27; V: # %bb.0:28; V-NEXT: vsetvli a1, zero, e8, mf8, ta, mu29; V-NEXT: vmv.v.i v8, 030; V-NEXT: vle8.v v8, (a0), v0.t31; V-NEXT: ret32;33; ZVE32-LABEL: masked_load_passthru_nxv1i8:34; ZVE32: # %bb.0:35; ZVE32-NEXT: csrr a1, vlenb36; ZVE32-NEXT: srli a1, a1, 337; ZVE32-NEXT: vsetvli zero, a1, e8, mf4, ta, mu38; ZVE32-NEXT: vmv.v.i v8, 039; ZVE32-NEXT: vle8.v v8, (a0), v0.t40; ZVE32-NEXT: ret41 %load = call <vscale x 1 x i8> @llvm.masked.load.nxv1i8(ptr %a, i32 1, <vscale x 1 x i1> %mask, <vscale x 1 x i8> zeroinitializer)42 ret <vscale x 1 x i8> %load43}44 45define <vscale x 1 x i16> @masked_load_nxv1i16(ptr %a, <vscale x 1 x i1> %mask) nounwind {46; V-LABEL: masked_load_nxv1i16:47; V: # %bb.0:48; V-NEXT: vsetvli a1, zero, e16, mf4, ta, ma49; V-NEXT: vle16.v v8, (a0), v0.t50; V-NEXT: ret51;52; ZVE32-LABEL: masked_load_nxv1i16:53; ZVE32: # %bb.0:54; ZVE32-NEXT: csrr a1, vlenb55; ZVE32-NEXT: srli a1, a1, 356; ZVE32-NEXT: vsetvli zero, a1, e16, mf2, ta, ma57; ZVE32-NEXT: vle16.v v8, (a0), v0.t58; ZVE32-NEXT: ret59 %load = call <vscale x 1 x i16> @llvm.masked.load.nxv1i16(ptr %a, i32 2, <vscale x 1 x i1> %mask, <vscale x 1 x i16> poison)60 ret <vscale x 1 x i16> %load61}62 63define <vscale x 1 x i32> @masked_load_nxv1i32(ptr %a, <vscale x 1 x i1> %mask) nounwind {64; V-LABEL: masked_load_nxv1i32:65; V: # %bb.0:66; V-NEXT: vsetvli a1, zero, e32, mf2, ta, ma67; V-NEXT: vle32.v v8, (a0), v0.t68; V-NEXT: ret69;70; ZVE32-LABEL: masked_load_nxv1i32:71; ZVE32: # %bb.0:72; ZVE32-NEXT: csrr a1, vlenb73; ZVE32-NEXT: srli a1, a1, 374; ZVE32-NEXT: vsetvli zero, a1, e32, m1, ta, ma75; ZVE32-NEXT: vle32.v v8, (a0), v0.t76; ZVE32-NEXT: ret77 %load = call <vscale x 1 x i32> @llvm.masked.load.nxv1i32(ptr %a, i32 4, <vscale x 1 x i1> %mask, <vscale x 1 x i32> poison)78 ret <vscale x 1 x i32> %load79}80 81define <vscale x 2 x i8> @masked_load_nxv2i8(ptr %a, <vscale x 2 x i1> %mask) nounwind {82; CHECK-LABEL: masked_load_nxv2i8:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma85; CHECK-NEXT: vle8.v v8, (a0), v0.t86; CHECK-NEXT: ret87 %load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(ptr %a, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i8> poison)88 ret <vscale x 2 x i8> %load89}90 91define <vscale x 2 x i16> @masked_load_nxv2i16(ptr %a, <vscale x 2 x i1> %mask) nounwind {92; CHECK-LABEL: masked_load_nxv2i16:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma95; CHECK-NEXT: vle16.v v8, (a0), v0.t96; CHECK-NEXT: ret97 %load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(ptr %a, i32 2, <vscale x 2 x i1> %mask, <vscale x 2 x i16> poison)98 ret <vscale x 2 x i16> %load99}100 101define <vscale x 2 x i32> @masked_load_nxv2i32(ptr %a, <vscale x 2 x i1> %mask) nounwind {102; CHECK-LABEL: masked_load_nxv2i32:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma105; CHECK-NEXT: vle32.v v8, (a0), v0.t106; CHECK-NEXT: ret107 %load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(ptr %a, i32 4, <vscale x 2 x i1> %mask, <vscale x 2 x i32> poison)108 ret <vscale x 2 x i32> %load109}110 111define <vscale x 4 x i8> @masked_load_nxv4i8(ptr %a, <vscale x 4 x i1> %mask) nounwind {112; CHECK-LABEL: masked_load_nxv4i8:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma115; CHECK-NEXT: vle8.v v8, (a0), v0.t116; CHECK-NEXT: ret117 %load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(ptr %a, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i8> poison)118 ret <vscale x 4 x i8> %load119}120 121define <vscale x 4 x i16> @masked_load_nxv4i16(ptr %a, <vscale x 4 x i1> %mask) nounwind {122; CHECK-LABEL: masked_load_nxv4i16:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma125; CHECK-NEXT: vle16.v v8, (a0), v0.t126; CHECK-NEXT: ret127 %load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(ptr %a, i32 2, <vscale x 4 x i1> %mask, <vscale x 4 x i16> poison)128 ret <vscale x 4 x i16> %load129}130 131define <vscale x 4 x i32> @masked_load_nxv4i32(ptr %a, <vscale x 4 x i1> %mask) nounwind {132; CHECK-LABEL: masked_load_nxv4i32:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma135; CHECK-NEXT: vle32.v v8, (a0), v0.t136; CHECK-NEXT: ret137 %load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr %a, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> poison)138 ret <vscale x 4 x i32> %load139}140 141define <vscale x 8 x i8> @masked_load_nxv8i8(ptr %a, <vscale x 8 x i1> %mask) nounwind {142; CHECK-LABEL: masked_load_nxv8i8:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma145; CHECK-NEXT: vle8.v v8, (a0), v0.t146; CHECK-NEXT: ret147 %load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(ptr %a, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x i8> poison)148 ret <vscale x 8 x i8> %load149}150 151define <vscale x 8 x i16> @masked_load_nxv8i16(ptr %a, <vscale x 8 x i1> %mask) nounwind {152; CHECK-LABEL: masked_load_nxv8i16:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma155; CHECK-NEXT: vle16.v v8, (a0), v0.t156; CHECK-NEXT: ret157 %load = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16(ptr %a, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x i16> poison)158 ret <vscale x 8 x i16> %load159}160 161define <vscale x 8 x i32> @masked_load_nxv8i32(ptr %a, <vscale x 8 x i1> %mask) nounwind {162; CHECK-LABEL: masked_load_nxv8i32:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma165; CHECK-NEXT: vle32.v v8, (a0), v0.t166; CHECK-NEXT: ret167 %load = call <vscale x 8 x i32> @llvm.masked.load.nxv8i32(ptr %a, i32 4, <vscale x 8 x i1> %mask, <vscale x 8 x i32> poison)168 ret <vscale x 8 x i32> %load169}170 171define <vscale x 16 x i8> @masked_load_nxv16i8(ptr %a, <vscale x 16 x i1> %mask) nounwind {172; CHECK-LABEL: masked_load_nxv16i8:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma175; CHECK-NEXT: vle8.v v8, (a0), v0.t176; CHECK-NEXT: ret177 %load = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8(ptr %a, i32 1, <vscale x 16 x i1> %mask, <vscale x 16 x i8> poison)178 ret <vscale x 16 x i8> %load179}180 181define <vscale x 16 x i16> @masked_load_nxv16i16(ptr %a, <vscale x 16 x i1> %mask) nounwind {182; CHECK-LABEL: masked_load_nxv16i16:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma185; CHECK-NEXT: vle16.v v8, (a0), v0.t186; CHECK-NEXT: ret187 %load = call <vscale x 16 x i16> @llvm.masked.load.nxv16i16(ptr %a, i32 2, <vscale x 16 x i1> %mask, <vscale x 16 x i16> poison)188 ret <vscale x 16 x i16> %load189}190 191define <vscale x 16 x i32> @masked_load_nxv16i32(ptr %a, <vscale x 16 x i1> %mask) nounwind {192; CHECK-LABEL: masked_load_nxv16i32:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma195; CHECK-NEXT: vle32.v v8, (a0), v0.t196; CHECK-NEXT: ret197 %load = call <vscale x 16 x i32> @llvm.masked.load.nxv16i32(ptr %a, i32 4, <vscale x 16 x i1> %mask, <vscale x 16 x i32> poison)198 ret <vscale x 16 x i32> %load199}200 201define <vscale x 32 x i8> @masked_load_nxv32i8(ptr %a, <vscale x 32 x i1> %mask) nounwind {202; CHECK-LABEL: masked_load_nxv32i8:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma205; CHECK-NEXT: vle8.v v8, (a0), v0.t206; CHECK-NEXT: ret207 %load = call <vscale x 32 x i8> @llvm.masked.load.nxv32i8(ptr %a, i32 1, <vscale x 32 x i1> %mask, <vscale x 32 x i8> poison)208 ret <vscale x 32 x i8> %load209}210 211define <vscale x 32 x i16> @masked_load_nxv32i16(ptr %a, <vscale x 32 x i1> %mask) nounwind {212; CHECK-LABEL: masked_load_nxv32i16:213; CHECK: # %bb.0:214; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma215; CHECK-NEXT: vle16.v v8, (a0), v0.t216; CHECK-NEXT: ret217 %load = call <vscale x 32 x i16> @llvm.masked.load.nxv32i16(ptr %a, i32 2, <vscale x 32 x i1> %mask, <vscale x 32 x i16> poison)218 ret <vscale x 32 x i16> %load219}220 221define <vscale x 64 x i8> @masked_load_nxv64i8(ptr %a, <vscale x 64 x i1> %mask) nounwind {222; CHECK-LABEL: masked_load_nxv64i8:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma225; CHECK-NEXT: vle8.v v8, (a0), v0.t226; CHECK-NEXT: ret227 %load = call <vscale x 64 x i8> @llvm.masked.load.nxv64i8(ptr %a, i32 1, <vscale x 64 x i1> %mask, <vscale x 64 x i8> poison)228 ret <vscale x 64 x i8> %load229}230 231define <vscale x 2 x i8> @masked_load_zero_mask(ptr %a) nounwind {232; CHECK-LABEL: masked_load_zero_mask:233; CHECK: # %bb.0:234; CHECK-NEXT: ret235 %load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(ptr %a, i32 1, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i8> poison)236 ret <vscale x 2 x i8> %load237}238 239define <vscale x 2 x i8> @masked_load_allones_mask(ptr %a, <vscale x 2 x i8> %maskedoff) nounwind {240; CHECK-LABEL: masked_load_allones_mask:241; CHECK: # %bb.0:242; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma243; CHECK-NEXT: vle8.v v8, (a0)244; CHECK-NEXT: ret245 %load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(ptr %a, i32 1, <vscale x 2 x i1> splat (i1 1), <vscale x 2 x i8> %maskedoff)246 ret <vscale x 2 x i8> %load247}248