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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s6 7define void @masked_store_nxv1bf16(<vscale x 1 x bfloat> %val, ptr %a, <vscale x 1 x i1> %mask) nounwind {8; CHECK-LABEL: masked_store_nxv1bf16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma11; CHECK-NEXT: vse16.v v8, (a0), v0.t12; CHECK-NEXT: ret13 call void @llvm.masked.store.nxv1bf16.p0(<vscale x 1 x bfloat> %val, ptr %a, i32 2, <vscale x 1 x i1> %mask)14 ret void15}16 17define void @masked_store_nxv1f16(<vscale x 1 x half> %val, ptr %a, <vscale x 1 x i1> %mask) nounwind {18; CHECK-LABEL: masked_store_nxv1f16:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma21; CHECK-NEXT: vse16.v v8, (a0), v0.t22; CHECK-NEXT: ret23 call void @llvm.masked.store.nxv1f16.p0(<vscale x 1 x half> %val, ptr %a, i32 2, <vscale x 1 x i1> %mask)24 ret void25}26 27define void @masked_store_nxv1f32(<vscale x 1 x float> %val, ptr %a, <vscale x 1 x i1> %mask) nounwind {28; CHECK-LABEL: masked_store_nxv1f32:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma31; CHECK-NEXT: vse32.v v8, (a0), v0.t32; CHECK-NEXT: ret33 call void @llvm.masked.store.nxv1f32.p0(<vscale x 1 x float> %val, ptr %a, i32 4, <vscale x 1 x i1> %mask)34 ret void35}36 37define void @masked_store_nxv1f64(<vscale x 1 x double> %val, ptr %a, <vscale x 1 x i1> %mask) nounwind {38; CHECK-LABEL: masked_store_nxv1f64:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma41; CHECK-NEXT: vse64.v v8, (a0), v0.t42; CHECK-NEXT: ret43 call void @llvm.masked.store.nxv1f64.p0(<vscale x 1 x double> %val, ptr %a, i32 8, <vscale x 1 x i1> %mask)44 ret void45}46 47define void @masked_store_nxv2bf16(<vscale x 2 x bfloat> %val, ptr %a, <vscale x 2 x i1> %mask) nounwind {48; CHECK-LABEL: masked_store_nxv2bf16:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma51; CHECK-NEXT: vse16.v v8, (a0), v0.t52; CHECK-NEXT: ret53 call void @llvm.masked.store.nxv2bf16.p0(<vscale x 2 x bfloat> %val, ptr %a, i32 2, <vscale x 2 x i1> %mask)54 ret void55}56 57define void @masked_store_nxv2f16(<vscale x 2 x half> %val, ptr %a, <vscale x 2 x i1> %mask) nounwind {58; CHECK-LABEL: masked_store_nxv2f16:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma61; CHECK-NEXT: vse16.v v8, (a0), v0.t62; CHECK-NEXT: ret63 call void @llvm.masked.store.nxv2f16.p0(<vscale x 2 x half> %val, ptr %a, i32 2, <vscale x 2 x i1> %mask)64 ret void65}66 67define void @masked_store_nxv2f32(<vscale x 2 x float> %val, ptr %a, <vscale x 2 x i1> %mask) nounwind {68; CHECK-LABEL: masked_store_nxv2f32:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma71; CHECK-NEXT: vse32.v v8, (a0), v0.t72; CHECK-NEXT: ret73 call void @llvm.masked.store.nxv2f32.p0(<vscale x 2 x float> %val, ptr %a, i32 4, <vscale x 2 x i1> %mask)74 ret void75}76 77define void @masked_store_nxv2f64(<vscale x 2 x double> %val, ptr %a, <vscale x 2 x i1> %mask) nounwind {78; CHECK-LABEL: masked_store_nxv2f64:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma81; CHECK-NEXT: vse64.v v8, (a0), v0.t82; CHECK-NEXT: ret83 call void @llvm.masked.store.nxv2f64.p0(<vscale x 2 x double> %val, ptr %a, i32 8, <vscale x 2 x i1> %mask)84 ret void85}86 87define void @masked_store_nxv4bf16(<vscale x 4 x bfloat> %val, ptr %a, <vscale x 4 x i1> %mask) nounwind {88; CHECK-LABEL: masked_store_nxv4bf16:89; CHECK: # %bb.0:90; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma91; CHECK-NEXT: vse16.v v8, (a0), v0.t92; CHECK-NEXT: ret93 call void @llvm.masked.store.nxv4bf16.p0(<vscale x 4 x bfloat> %val, ptr %a, i32 2, <vscale x 4 x i1> %mask)94 ret void95}96 97define void @masked_store_nxv4f16(<vscale x 4 x half> %val, ptr %a, <vscale x 4 x i1> %mask) nounwind {98; CHECK-LABEL: masked_store_nxv4f16:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma101; CHECK-NEXT: vse16.v v8, (a0), v0.t102; CHECK-NEXT: ret103 call void @llvm.masked.store.nxv4f16.p0(<vscale x 4 x half> %val, ptr %a, i32 2, <vscale x 4 x i1> %mask)104 ret void105}106 107define void @masked_store_nxv4f32(<vscale x 4 x float> %val, ptr %a, <vscale x 4 x i1> %mask) nounwind {108; CHECK-LABEL: masked_store_nxv4f32:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma111; CHECK-NEXT: vse32.v v8, (a0), v0.t112; CHECK-NEXT: ret113 call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)114 ret void115}116 117define void @masked_store_nxv4f64(<vscale x 4 x double> %val, ptr %a, <vscale x 4 x i1> %mask) nounwind {118; CHECK-LABEL: masked_store_nxv4f64:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma121; CHECK-NEXT: vse64.v v8, (a0), v0.t122; CHECK-NEXT: ret123 call void @llvm.masked.store.nxv4f64.p0(<vscale x 4 x double> %val, ptr %a, i32 8, <vscale x 4 x i1> %mask)124 ret void125}126 127define void @masked_store_nxv8bf16(<vscale x 8 x bfloat> %val, ptr %a, <vscale x 8 x i1> %mask) nounwind {128; CHECK-LABEL: masked_store_nxv8bf16:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma131; CHECK-NEXT: vse16.v v8, (a0), v0.t132; CHECK-NEXT: ret133 call void @llvm.masked.store.nxv8bf16.p0(<vscale x 8 x bfloat> %val, ptr %a, i32 2, <vscale x 8 x i1> %mask)134 ret void135}136 137define void @masked_store_nxv8f16(<vscale x 8 x half> %val, ptr %a, <vscale x 8 x i1> %mask) nounwind {138; CHECK-LABEL: masked_store_nxv8f16:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma141; CHECK-NEXT: vse16.v v8, (a0), v0.t142; CHECK-NEXT: ret143 call void @llvm.masked.store.nxv8f16.p0(<vscale x 8 x half> %val, ptr %a, i32 2, <vscale x 8 x i1> %mask)144 ret void145}146 147define void @masked_store_nxv8f32(<vscale x 8 x float> %val, ptr %a, <vscale x 8 x i1> %mask) nounwind {148; CHECK-LABEL: masked_store_nxv8f32:149; CHECK: # %bb.0:150; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma151; CHECK-NEXT: vse32.v v8, (a0), v0.t152; CHECK-NEXT: ret153 call void @llvm.masked.store.nxv8f32.p0(<vscale x 8 x float> %val, ptr %a, i32 4, <vscale x 8 x i1> %mask)154 ret void155}156 157define void @masked_store_nxv8f64(<vscale x 8 x double> %val, ptr %a, <vscale x 8 x i1> %mask) nounwind {158; CHECK-LABEL: masked_store_nxv8f64:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma161; CHECK-NEXT: vse64.v v8, (a0), v0.t162; CHECK-NEXT: ret163 call void @llvm.masked.store.nxv8f64.p0(<vscale x 8 x double> %val, ptr %a, i32 8, <vscale x 8 x i1> %mask)164 ret void165}166 167define void @masked_store_nxv16bf16(<vscale x 16 x bfloat> %val, ptr %a, <vscale x 16 x i1> %mask) nounwind {168; CHECK-LABEL: masked_store_nxv16bf16:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma171; CHECK-NEXT: vse16.v v8, (a0), v0.t172; CHECK-NEXT: ret173 call void @llvm.masked.store.nxv16bf16.p0(<vscale x 16 x bfloat> %val, ptr %a, i32 2, <vscale x 16 x i1> %mask)174 ret void175}176 177define void @masked_store_nxv16f16(<vscale x 16 x half> %val, ptr %a, <vscale x 16 x i1> %mask) nounwind {178; CHECK-LABEL: masked_store_nxv16f16:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma181; CHECK-NEXT: vse16.v v8, (a0), v0.t182; CHECK-NEXT: ret183 call void @llvm.masked.store.nxv16f16.p0(<vscale x 16 x half> %val, ptr %a, i32 2, <vscale x 16 x i1> %mask)184 ret void185}186 187define void @masked_store_nxv16f32(<vscale x 16 x float> %val, ptr %a, <vscale x 16 x i1> %mask) nounwind {188; CHECK-LABEL: masked_store_nxv16f32:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma191; CHECK-NEXT: vse32.v v8, (a0), v0.t192; CHECK-NEXT: ret193 call void @llvm.masked.store.nxv16f32.p0(<vscale x 16 x float> %val, ptr %a, i32 4, <vscale x 16 x i1> %mask)194 ret void195}196 197define void @masked_store_nxv32bf16(<vscale x 32 x bfloat> %val, ptr %a, <vscale x 32 x i1> %mask) nounwind {198; CHECK-LABEL: masked_store_nxv32bf16:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma201; CHECK-NEXT: vse16.v v8, (a0), v0.t202; CHECK-NEXT: ret203 call void @llvm.masked.store.nxv32bf16.p0(<vscale x 32 x bfloat> %val, ptr %a, i32 2, <vscale x 32 x i1> %mask)204 ret void205}206 207define void @masked_store_nxv32f16(<vscale x 32 x half> %val, ptr %a, <vscale x 32 x i1> %mask) nounwind {208; CHECK-LABEL: masked_store_nxv32f16:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma211; CHECK-NEXT: vse16.v v8, (a0), v0.t212; CHECK-NEXT: ret213 call void @llvm.masked.store.nxv32f16.p0(<vscale x 32 x half> %val, ptr %a, i32 2, <vscale x 32 x i1> %mask)214 ret void215}216