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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V4; RUN: llc -mtriple=riscv32 -mattr=+zve32x,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE325; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE326 7define void @masked_store_nxv1i8(<vscale x 1 x i8> %val, ptr %a, <vscale x 1 x i1> %mask) nounwind {8; V-LABEL: masked_store_nxv1i8:9; V: # %bb.0:10; V-NEXT: vsetvli a1, zero, e8, mf8, ta, ma11; V-NEXT: vse8.v v8, (a0), v0.t12; V-NEXT: ret13;14; ZVE32-LABEL: masked_store_nxv1i8:15; ZVE32: # %bb.0:16; ZVE32-NEXT: csrr a1, vlenb17; ZVE32-NEXT: srli a1, a1, 318; ZVE32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma19; ZVE32-NEXT: vse8.v v8, (a0), v0.t20; ZVE32-NEXT: ret21 call void @llvm.masked.store.v1i8.p0(<vscale x 1 x i8> %val, ptr %a, i32 1, <vscale x 1 x i1> %mask)22 ret void23}24 25define void @masked_store_nxv1i16(<vscale x 1 x i16> %val, ptr %a, <vscale x 1 x i1> %mask) nounwind {26; V-LABEL: masked_store_nxv1i16:27; V: # %bb.0:28; V-NEXT: vsetvli a1, zero, e16, mf4, ta, ma29; V-NEXT: vse16.v v8, (a0), v0.t30; V-NEXT: ret31;32; ZVE32-LABEL: masked_store_nxv1i16:33; ZVE32: # %bb.0:34; ZVE32-NEXT: csrr a1, vlenb35; ZVE32-NEXT: srli a1, a1, 336; ZVE32-NEXT: vsetvli zero, a1, e16, mf2, ta, ma37; ZVE32-NEXT: vse16.v v8, (a0), v0.t38; ZVE32-NEXT: ret39 call void @llvm.masked.store.v1i16.p0(<vscale x 1 x i16> %val, ptr %a, i32 2, <vscale x 1 x i1> %mask)40 ret void41}42 43define void @masked_store_nxv1i32(<vscale x 1 x i32> %val, ptr %a, <vscale x 1 x i1> %mask) nounwind {44; V-LABEL: masked_store_nxv1i32:45; V: # %bb.0:46; V-NEXT: vsetvli a1, zero, e32, mf2, ta, ma47; V-NEXT: vse32.v v8, (a0), v0.t48; V-NEXT: ret49;50; ZVE32-LABEL: masked_store_nxv1i32:51; ZVE32: # %bb.0:52; ZVE32-NEXT: csrr a1, vlenb53; ZVE32-NEXT: srli a1, a1, 354; ZVE32-NEXT: vsetvli zero, a1, e32, m1, ta, ma55; ZVE32-NEXT: vse32.v v8, (a0), v0.t56; ZVE32-NEXT: ret57 call void @llvm.masked.store.v1i32.p0(<vscale x 1 x i32> %val, ptr %a, i32 4, <vscale x 1 x i1> %mask)58 ret void59}60 61define void @masked_store_nxv2i8(<vscale x 2 x i8> %val, ptr %a, <vscale x 2 x i1> %mask) nounwind {62; CHECK-LABEL: masked_store_nxv2i8:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma65; CHECK-NEXT: vse8.v v8, (a0), v0.t66; CHECK-NEXT: ret67 call void @llvm.masked.store.v2i8.p0(<vscale x 2 x i8> %val, ptr %a, i32 1, <vscale x 2 x i1> %mask)68 ret void69}70 71define void @masked_store_nxv2i16(<vscale x 2 x i16> %val, ptr %a, <vscale x 2 x i1> %mask) nounwind {72; CHECK-LABEL: masked_store_nxv2i16:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma75; CHECK-NEXT: vse16.v v8, (a0), v0.t76; CHECK-NEXT: ret77 call void @llvm.masked.store.v2i16.p0(<vscale x 2 x i16> %val, ptr %a, i32 2, <vscale x 2 x i1> %mask)78 ret void79}80 81define void @masked_store_nxv2i32(<vscale x 2 x i32> %val, ptr %a, <vscale x 2 x i1> %mask) nounwind {82; CHECK-LABEL: masked_store_nxv2i32:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma85; CHECK-NEXT: vse32.v v8, (a0), v0.t86; CHECK-NEXT: ret87 call void @llvm.masked.store.v2i32.p0(<vscale x 2 x i32> %val, ptr %a, i32 4, <vscale x 2 x i1> %mask)88 ret void89}90 91define void @masked_store_nxv4i8(<vscale x 4 x i8> %val, ptr %a, <vscale x 4 x i1> %mask) nounwind {92; CHECK-LABEL: masked_store_nxv4i8:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma95; CHECK-NEXT: vse8.v v8, (a0), v0.t96; CHECK-NEXT: ret97 call void @llvm.masked.store.v4i8.p0(<vscale x 4 x i8> %val, ptr %a, i32 1, <vscale x 4 x i1> %mask)98 ret void99}100 101define void @masked_store_nxv4i16(<vscale x 4 x i16> %val, ptr %a, <vscale x 4 x i1> %mask) nounwind {102; CHECK-LABEL: masked_store_nxv4i16:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma105; CHECK-NEXT: vse16.v v8, (a0), v0.t106; CHECK-NEXT: ret107 call void @llvm.masked.store.v4i16.p0(<vscale x 4 x i16> %val, ptr %a, i32 2, <vscale x 4 x i1> %mask)108 ret void109}110 111define void @masked_store_nxv4i32(<vscale x 4 x i32> %val, ptr %a, <vscale x 4 x i1> %mask) nounwind {112; CHECK-LABEL: masked_store_nxv4i32:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma115; CHECK-NEXT: vse32.v v8, (a0), v0.t116; CHECK-NEXT: ret117 call void @llvm.masked.store.v4i32.p0(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)118 ret void119}120 121define void @masked_store_nxv8i8(<vscale x 8 x i8> %val, ptr %a, <vscale x 8 x i1> %mask) nounwind {122; CHECK-LABEL: masked_store_nxv8i8:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma125; CHECK-NEXT: vse8.v v8, (a0), v0.t126; CHECK-NEXT: ret127 call void @llvm.masked.store.v8i8.p0(<vscale x 8 x i8> %val, ptr %a, i32 1, <vscale x 8 x i1> %mask)128 ret void129}130 131define void @masked_store_nxv8i16(<vscale x 8 x i16> %val, ptr %a, <vscale x 8 x i1> %mask) nounwind {132; CHECK-LABEL: masked_store_nxv8i16:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma135; CHECK-NEXT: vse16.v v8, (a0), v0.t136; CHECK-NEXT: ret137 call void @llvm.masked.store.v8i16.p0(<vscale x 8 x i16> %val, ptr %a, i32 2, <vscale x 8 x i1> %mask)138 ret void139}140 141define void @masked_store_nxv8i32(<vscale x 8 x i32> %val, ptr %a, <vscale x 8 x i1> %mask) nounwind {142; CHECK-LABEL: masked_store_nxv8i32:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma145; CHECK-NEXT: vse32.v v8, (a0), v0.t146; CHECK-NEXT: ret147 call void @llvm.masked.store.v8i32.p0(<vscale x 8 x i32> %val, ptr %a, i32 4, <vscale x 8 x i1> %mask)148 ret void149}150 151define void @masked_store_nxv16i8(<vscale x 16 x i8> %val, ptr %a, <vscale x 16 x i1> %mask) nounwind {152; CHECK-LABEL: masked_store_nxv16i8:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma155; CHECK-NEXT: vse8.v v8, (a0), v0.t156; CHECK-NEXT: ret157 call void @llvm.masked.store.v16i8.p0(<vscale x 16 x i8> %val, ptr %a, i32 1, <vscale x 16 x i1> %mask)158 ret void159}160 161define void @masked_store_nxv16i16(<vscale x 16 x i16> %val, ptr %a, <vscale x 16 x i1> %mask) nounwind {162; CHECK-LABEL: masked_store_nxv16i16:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma165; CHECK-NEXT: vse16.v v8, (a0), v0.t166; CHECK-NEXT: ret167 call void @llvm.masked.store.v16i16.p0(<vscale x 16 x i16> %val, ptr %a, i32 2, <vscale x 16 x i1> %mask)168 ret void169}170 171define void @masked_store_nxv16i32(<vscale x 16 x i32> %val, ptr %a, <vscale x 16 x i1> %mask) nounwind {172; CHECK-LABEL: masked_store_nxv16i32:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma175; CHECK-NEXT: vse32.v v8, (a0), v0.t176; CHECK-NEXT: ret177 call void @llvm.masked.store.v16i32.p0(<vscale x 16 x i32> %val, ptr %a, i32 4, <vscale x 16 x i1> %mask)178 ret void179}180 181define void @masked_store_nxv32i8(<vscale x 32 x i8> %val, ptr %a, <vscale x 32 x i1> %mask) nounwind {182; CHECK-LABEL: masked_store_nxv32i8:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma185; CHECK-NEXT: vse8.v v8, (a0), v0.t186; CHECK-NEXT: ret187 call void @llvm.masked.store.v32i8.p0(<vscale x 32 x i8> %val, ptr %a, i32 1, <vscale x 32 x i1> %mask)188 ret void189}190 191define void @masked_store_nxv32i16(<vscale x 32 x i16> %val, ptr %a, <vscale x 32 x i1> %mask) nounwind {192; CHECK-LABEL: masked_store_nxv32i16:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma195; CHECK-NEXT: vse16.v v8, (a0), v0.t196; CHECK-NEXT: ret197 call void @llvm.masked.store.v32i16.p0(<vscale x 32 x i16> %val, ptr %a, i32 2, <vscale x 32 x i1> %mask)198 ret void199}200 201define void @masked_store_nxv64i8(<vscale x 64 x i8> %val, ptr %a, <vscale x 64 x i1> %mask) nounwind {202; CHECK-LABEL: masked_store_nxv64i8:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma205; CHECK-NEXT: vse8.v v8, (a0), v0.t206; CHECK-NEXT: ret207 call void @llvm.masked.store.v64i8.p0(<vscale x 64 x i8> %val, ptr %a, i32 4, <vscale x 64 x i1> %mask)208 ret void209}210 211define void @masked_store_zero_mask(<vscale x 2 x i8> %val, ptr %a) nounwind {212; CHECK-LABEL: masked_store_zero_mask:213; CHECK: # %bb.0:214; CHECK-NEXT: ret215 call void @llvm.masked.store.v2i8.p0(<vscale x 2 x i8> %val, ptr %a, i32 1, <vscale x 2 x i1> zeroinitializer)216 ret void217}218 219define void @masked_store_allones_mask(<vscale x 2 x i8> %val, ptr %a) nounwind {220; CHECK-LABEL: masked_store_allones_mask:221; CHECK: # %bb.0:222; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma223; CHECK-NEXT: vse8.v v8, (a0)224; CHECK-NEXT: ret225 call void @llvm.masked.store.v2i8.p0(<vscale x 2 x i8> %val, ptr %a, i32 1, <vscale x 2 x i1> splat (i1 1))226 ret void227}228