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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i64> @intrinsic_vle_mask_nxv1i64_nxv1i64(ptr %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vle_mask_nxv1i64_nxv1i64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11; CHECK-NEXT: vle64.v v8, (a0), v0.t12; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(15 <vscale x 1 x i64> poison,16 ptr %0,17 <vscale x 1 x i1> %1,18 iXLen %2, iXLen 3)19 20 ret <vscale x 1 x i64> %a21}22 23define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(ptr %0, <vscale x 1 x i1> %1, iXLen %2, ptr %3) nounwind {24; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64:25; RV32: # %bb.0: # %entry26; RV32-NEXT: vsetvli zero, a1, e64, m1, ta, ma27; RV32-NEXT: vle64ff.v v8, (a0), v0.t28; RV32-NEXT: csrr a0, vl29; RV32-NEXT: sw a0, 0(a2)30; RV32-NEXT: ret31;32; RV64-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64:33; RV64: # %bb.0: # %entry34; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma35; RV64-NEXT: vle64ff.v v8, (a0), v0.t36; RV64-NEXT: csrr a0, vl37; RV64-NEXT: sd a0, 0(a2)38; RV64-NEXT: ret39entry:40 %a = call { <vscale x 1 x i64>, iXLen } @llvm.riscv.vleff.mask.nxv1i64(41 <vscale x 1 x i64> poison,42 ptr %0,43 <vscale x 1 x i1> %1,44 iXLen %2, iXLen 3)45 %b = extractvalue { <vscale x 1 x i64>, iXLen } %a, 046 %c = extractvalue { <vscale x 1 x i64>, iXLen } %a, 147 store iXLen %c, ptr %348 49 ret <vscale x 1 x i64> %b50}51 52define <vscale x 1 x i64> @intrinsic_vlse_mask_v_nxv1i64_nxv1i64(ptr %0, iXLen %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {53; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i64_nxv1i64:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma56; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t57; CHECK-NEXT: ret58entry:59 %a = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64(60 <vscale x 1 x i64> poison,61 ptr %0,62 iXLen %1,63 <vscale x 1 x i1> %2,64 iXLen %3, iXLen 3)65 66 ret <vscale x 1 x i64> %a67}68 69define <vscale x 1 x i8> @intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1iXLen(ptr %0, <vscale x 1 x iXLen> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {70entry:71 %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1iXLen(72 <vscale x 1 x i8> poison,73 ptr %0,74 <vscale x 1 x iXLen> %1,75 <vscale x 1 x i1> %2,76 iXLen %3, iXLen 3)77 78 ret <vscale x 1 x i8> %a79}80 81define <vscale x 1 x i8> @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {82; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma85; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t86; CHECK-NEXT: ret87entry:88 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(89 <vscale x 1 x i8> poison,90 <vscale x 1 x i8> %0,91 <vscale x 1 x i8> %1,92 <vscale x 1 x i1> %2,93 iXLen %3, iXLen 3)94 95 ret <vscale x 1 x i8> %a96}97 98define <vscale x 1 x i16> @intrinsic_vwadd_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {99; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i16_nxv1i8_nxv1i8:100; CHECK: # %bb.0: # %entry101; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma102; CHECK-NEXT: vwadd.vv v10, v8, v9, v0.t103; CHECK-NEXT: vmv1r.v v8, v10104; CHECK-NEXT: ret105entry:106 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.mask.nxv1i16.nxv1i8.nxv1i8(107 <vscale x 1 x i16> poison,108 <vscale x 1 x i8> %0,109 <vscale x 1 x i8> %1,110 <vscale x 1 x i1> %2,111 iXLen %3, iXLen 3)112 113 ret <vscale x 1 x i16> %a114}115 116define <vscale x 1 x i8> @intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {117; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8:118; CHECK: # %bb.0: # %entry119; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma120; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t121; CHECK-NEXT: ret122entry:123 %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(124 <vscale x 1 x i8> poison,125 <vscale x 1 x i8> %0,126 i8 %1,127 <vscale x 1 x i1> %2,128 iXLen %3, iXLen 3)129 130 ret <vscale x 1 x i8> %a131}132 133define <vscale x 1 x i8> @intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {134; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8:135; CHECK: # %bb.0: # %entry136; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma137; CHECK-NEXT: vadd.vi v8, v8, 9, v0.t138; CHECK-NEXT: ret139entry:140 %a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(141 <vscale x 1 x i8> poison,142 <vscale x 1 x i8> %0,143 i8 -9,144 <vscale x 1 x i1> %1,145 iXLen %2, iXLen 3)146 147 ret <vscale x 1 x i8> %a148}149 150define <vscale x 1 x i64> @intrinsic_vzext_mask_vf2_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {151; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv1i64:152; CHECK: # %bb.0: # %entry153; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma154; CHECK-NEXT: vzext.vf2 v9, v8, v0.t155; CHECK-NEXT: vmv.v.v v8, v9156; CHECK-NEXT: ret157entry:158 %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32(159 <vscale x 1 x i64> poison,160 <vscale x 1 x i32> %0,161 <vscale x 1 x i1> %1,162 iXLen %2, iXLen 3)163 164 ret <vscale x 1 x i64> %a165}166 167define <vscale x 1 x i64> @intrinsic_vzext_mask_vf4_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {168; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv1i64:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma171; CHECK-NEXT: vzext.vf4 v9, v8, v0.t172; CHECK-NEXT: vmv.v.v v8, v9173; CHECK-NEXT: ret174entry:175 %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i16(176 <vscale x 1 x i64> poison,177 <vscale x 1 x i16> %0,178 <vscale x 1 x i1> %1,179 iXLen %2, iXLen 3)180 181 ret <vscale x 1 x i64> %a182}183 184define <vscale x 1 x i64> @intrinsic_vzext_mask_vf8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {185; CHECK-LABEL: intrinsic_vzext_mask_vf8_nxv1i64:186; CHECK: # %bb.0: # %entry187; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma188; CHECK-NEXT: vzext.vf8 v9, v8, v0.t189; CHECK-NEXT: vmv.v.v v8, v9190; CHECK-NEXT: ret191entry:192 %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8(193 <vscale x 1 x i64> poison,194 <vscale x 1 x i8> %0,195 <vscale x 1 x i1> %1,196 iXLen %2, iXLen 3)197 198 ret <vscale x 1 x i64> %a199}200 201define <vscale x 1 x i8> @intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {202; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8:203; CHECK: # %bb.0: # %entry204; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma205; CHECK-NEXT: vand.vv v8, v8, v9, v0.t206; CHECK-NEXT: ret207entry:208 %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.nxv1i8(209 <vscale x 1 x i8> poison,210 <vscale x 1 x i8> %0,211 <vscale x 1 x i8> %1,212 <vscale x 1 x i1> %2,213 iXLen %3, iXLen 3)214 215 ret <vscale x 1 x i8> %a216}217 218define <vscale x 1 x i8> @intrinsic_vsll_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {219; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i8_nxv1i8_nxv1i8:220; CHECK: # %bb.0: # %entry221; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma222; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t223; CHECK-NEXT: ret224entry:225 %a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8(226 <vscale x 1 x i8> poison,227 <vscale x 1 x i8> %0,228 <vscale x 1 x i8> %1,229 <vscale x 1 x i1> %2,230 iXLen %3, iXLen 3)231 232 ret <vscale x 1 x i8> %a233}234 235define <vscale x 1 x i8> @intrinsic_vnsra_mask_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {236; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i8_nxv1i16_nxv1i8:237; CHECK: # %bb.0: # %entry238; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma239; CHECK-NEXT: vnsra.wv v8, v8, v9, v0.t240; CHECK-NEXT: ret241entry:242 %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.nxv1i8(243 <vscale x 1 x i8> poison,244 <vscale x 1 x i16> %0,245 <vscale x 1 x i8> %1,246 <vscale x 1 x i1> %2,247 iXLen %3, iXLen 3)248 249 ret <vscale x 1 x i8> %a250}251 252define <vscale x 1 x i8> @intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {253; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8:254; CHECK: # %bb.0: # %entry255; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma256; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t257; CHECK-NEXT: ret258entry:259 %a = call <vscale x 1 x i8> @llvm.riscv.vmin.mask.nxv1i8.nxv1i8(260 <vscale x 1 x i8> poison,261 <vscale x 1 x i8> %0,262 <vscale x 1 x i8> %1,263 <vscale x 1 x i1> %2,264 iXLen %3, iXLen 3)265 266 ret <vscale x 1 x i8> %a267}268 269define <vscale x 1 x i8> @intrinsic_vdiv_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {270; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i8_nxv1i8_nxv1i8:271; CHECK: # %bb.0: # %entry272; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma273; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t274; CHECK-NEXT: ret275entry:276 %a = call <vscale x 1 x i8> @llvm.riscv.vdiv.mask.nxv1i8.nxv1i8(277 <vscale x 1 x i8> poison,278 <vscale x 1 x i8> %0,279 <vscale x 1 x i8> %1,280 <vscale x 1 x i1> %2,281 iXLen %3, iXLen 3)282 283 ret <vscale x 1 x i8> %a284}285 286define <vscale x 1 x i16> @intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {287; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8:288; CHECK: # %bb.0: # %entry289; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma290; CHECK-NEXT: vwmul.vv v10, v8, v9, v0.t291; CHECK-NEXT: vmv1r.v v8, v10292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.nxv1i8(295 <vscale x 1 x i16> poison,296 <vscale x 1 x i8> %0,297 <vscale x 1 x i8> %1,298 <vscale x 1 x i1> %2,299 iXLen %3, iXLen 3)300 301 ret <vscale x 1 x i16> %a302}303 304define <vscale x 1 x i8> @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {305; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma308; CHECK-NEXT: vmacc.vv v8, v8, v9, v0.t309; CHECK-NEXT: ret310entry:311 %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(312 <vscale x 1 x i8> poison,313 <vscale x 1 x i8> %0,314 <vscale x 1 x i8> %1,315 <vscale x 1 x i1> %2,316 iXLen %3, iXLen 3)317 318 ret <vscale x 1 x i8> %a319}320 321define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {322; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma325; CHECK-NEXT: vwmacc.vv v10, v8, v9, v0.t326; CHECK-NEXT: vmv1r.v v8, v10327; CHECK-NEXT: ret328entry:329 %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8(330 <vscale x 1 x i16> poison,331 <vscale x 1 x i8> %0,332 <vscale x 1 x i8> %1,333 <vscale x 1 x i1> %2,334 iXLen %3, iXLen 3)335 336 ret <vscale x 1 x i16> %a337}338 339define <vscale x 1 x i8> @intrinsic_vsadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {340; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:341; CHECK: # %bb.0: # %entry342; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma343; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t344; CHECK-NEXT: ret345entry:346 %a = call <vscale x 1 x i8> @llvm.riscv.vsadd.mask.nxv1i8.nxv1i8(347 <vscale x 1 x i8> poison,348 <vscale x 1 x i8> %0,349 <vscale x 1 x i8> %1,350 <vscale x 1 x i1> %2,351 iXLen %3, iXLen 3)352 353 ret <vscale x 1 x i8> %a354}355 356define <vscale x 1 x i8> @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {357; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:358; CHECK: # %bb.0: # %entry359; CHECK-NEXT: csrwi vxrm, 1360; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma361; CHECK-NEXT: vaadd.vv v8, v8, v9, v0.t362; CHECK-NEXT: ret363entry:364 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8(365 <vscale x 1 x i8> poison,366 <vscale x 1 x i8> %0,367 <vscale x 1 x i8> %1,368 <vscale x 1 x i1> %2,369 iXLen 1, iXLen %3, iXLen 3)370 371 ret <vscale x 1 x i8> %a372}373 374define <vscale x 1 x i8> @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {375; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8:376; CHECK: # %bb.0: # %entry377; CHECK-NEXT: csrwi vxrm, 0378; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma379; CHECK-NEXT: vsmul.vv v8, v8, v9, v0.t380; CHECK-NEXT: ret381entry:382 %a = call <vscale x 1 x i8> @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8(383 <vscale x 1 x i8> poison,384 <vscale x 1 x i8> %0,385 <vscale x 1 x i8> %1,386 <vscale x 1 x i1> %2,387 iXLen 0, iXLen %3, iXLen 3)388 389 ret <vscale x 1 x i8> %a390}391 392define <vscale x 1 x i8> @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {393; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8:394; CHECK: # %bb.0: # %entry395; CHECK-NEXT: csrwi vxrm, 0396; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma397; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t398; CHECK-NEXT: ret399entry:400 %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8(401 <vscale x 1 x i8> poison,402 <vscale x 1 x i8> %0,403 <vscale x 1 x i8> %1,404 <vscale x 1 x i1> %2,405 iXLen 0, iXLen %3, iXLen 3)406 407 ret <vscale x 1 x i8> %a408}409 410define <vscale x 1 x i8> @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {411; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8:412; CHECK: # %bb.0: # %entry413; CHECK-NEXT: csrwi vxrm, 0414; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma415; CHECK-NEXT: vnclip.wv v8, v8, v9, v0.t416; CHECK-NEXT: ret417entry:418 %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8(419 <vscale x 1 x i8> poison,420 <vscale x 1 x i16> %0,421 <vscale x 1 x i8> %1,422 <vscale x 1 x i1> %2,423 iXLen 0, iXLen %3, iXLen 3)424 425 ret <vscale x 1 x i8> %a426}427 428define <vscale x 1 x half> @intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {429; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:430; CHECK: # %bb.0: # %entry431; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma432; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t433; CHECK-NEXT: ret434entry:435 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16(436 <vscale x 1 x half> poison,437 <vscale x 1 x half> %0,438 <vscale x 1 x half> %1,439 <vscale x 1 x i1> %2,440 iXLen 7, iXLen %3, iXLen 3)441 442 ret <vscale x 1 x half> %a443}444 445define <vscale x 1 x float> @intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {446; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16:447; CHECK: # %bb.0: # %entry448; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma449; CHECK-NEXT: vfwadd.vv v10, v8, v9, v0.t450; CHECK-NEXT: vmv1r.v v8, v10451; CHECK-NEXT: ret452entry:453 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16(454 <vscale x 1 x float> poison,455 <vscale x 1 x half> %0,456 <vscale x 1 x half> %1,457 <vscale x 1 x i1> %2,458 iXLen 7, iXLen %3, iXLen 3)459 460 ret <vscale x 1 x float> %a461}462 463define <vscale x 1 x half> @intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {464; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16:465; CHECK: # %bb.0: # %entry466; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma467; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t468; CHECK-NEXT: ret469entry:470 %a = call <vscale x 1 x half> @llvm.riscv.vfmul.mask.nxv1f16.nxv1f16(471 <vscale x 1 x half> poison,472 <vscale x 1 x half> %0,473 <vscale x 1 x half> %1,474 <vscale x 1 x i1> %2,475 iXLen 7, iXLen %3, iXLen 3)476 477 ret <vscale x 1 x half> %a478}479 480define <vscale x 1 x half> @intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {481; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16_nxv1f16:482; CHECK: # %bb.0: # %entry483; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma484; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t485; CHECK-NEXT: ret486entry:487 %a = call <vscale x 1 x half> @llvm.riscv.vfdiv.mask.nxv1f16.nxv1f16(488 <vscale x 1 x half> poison,489 <vscale x 1 x half> %0,490 <vscale x 1 x half> %1,491 <vscale x 1 x i1> %2,492 iXLen 7, iXLen %3, iXLen 3)493 494 ret <vscale x 1 x half> %a495}496 497define <vscale x 1 x half> @intrinsic_vfrdiv_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {498; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f16_nxv1f16_f16:499; CHECK: # %bb.0: # %entry500; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma501; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t502; CHECK-NEXT: ret503entry:504 %a = call <vscale x 1 x half> @llvm.riscv.vfrdiv.mask.nxv1f16.f16(505 <vscale x 1 x half> poison,506 <vscale x 1 x half> %0,507 half %1,508 <vscale x 1 x i1> %2,509 iXLen 7, iXLen %3, iXLen 3)510 511 ret <vscale x 1 x half> %a512}513 514define <vscale x 1 x float> @intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {515; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16:516; CHECK: # %bb.0: # %entry517; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma518; CHECK-NEXT: vfwmul.vv v10, v8, v9, v0.t519; CHECK-NEXT: vmv1r.v v8, v10520; CHECK-NEXT: ret521entry:522 %a = call <vscale x 1 x float> @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.nxv1f16(523 <vscale x 1 x float> poison,524 <vscale x 1 x half> %0,525 <vscale x 1 x half> %1,526 <vscale x 1 x i1> %2,527 iXLen 7, iXLen %3, iXLen 3)528 529 ret <vscale x 1 x float> %a530}531 532define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {533; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:534; CHECK: # %bb.0: # %entry535; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma536; CHECK-NEXT: vfmacc.vv v8, v8, v9, v0.t537; CHECK-NEXT: ret538entry:539 %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(540 <vscale x 1 x half> poison,541 <vscale x 1 x half> %0,542 <vscale x 1 x half> %1,543 <vscale x 1 x i1> %2,544 iXLen 7, iXLen %3, iXLen 3)545 546 ret <vscale x 1 x half> %a547}548 549define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {550; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:551; CHECK: # %bb.0: # %entry552; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma553; CHECK-NEXT: vfwmacc.vv v10, v8, v9, v0.t554; CHECK-NEXT: vmv1r.v v8, v10555; CHECK-NEXT: ret556entry:557 %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(558 <vscale x 1 x float> poison,559 <vscale x 1 x half> %0,560 <vscale x 1 x half> %1,561 <vscale x 1 x i1> %2,562 iXLen 7, iXLen %3, iXLen 3);563 564 ret <vscale x 1 x float> %a565}566 567define <vscale x 1 x half> @intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {568; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16:569; CHECK: # %bb.0: # %entry570; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma571; CHECK-NEXT: vfsqrt.v v8, v8, v0.t572; CHECK-NEXT: ret573entry:574 %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(575 <vscale x 1 x half> poison,576 <vscale x 1 x half> %0,577 <vscale x 1 x i1> %1,578 iXLen 7, iXLen %2, iXLen 3)579 580 ret <vscale x 1 x half> %a581}582 583define <vscale x 1 x half> @intrinsic_vfrsqrt7_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {584; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv1f16_nxv1f16:585; CHECK: # %bb.0: # %entry586; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma587; CHECK-NEXT: vfrsqrt7.v v8, v8, v0.t588; CHECK-NEXT: ret589entry:590 %a = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.mask.nxv1f16(591 <vscale x 1 x half> poison,592 <vscale x 1 x half> %0,593 <vscale x 1 x i1> %1,594 iXLen %2, iXLen 3)595 596 ret <vscale x 1 x half> %a597}598 599define <vscale x 1 x half> @intrinsic_vfrec7_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {600; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f16_nxv1f16:601; CHECK: # %bb.0: # %entry602; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma603; CHECK-NEXT: vfrec7.v v8, v8, v0.t604; CHECK-NEXT: ret605entry:606 %a = call <vscale x 1 x half> @llvm.riscv.vfrec7.mask.nxv1f16(607 <vscale x 1 x half> poison,608 <vscale x 1 x half> %0,609 <vscale x 1 x i1> %1,610 iXLen 7, iXLen %2, iXLen 3)611 612 ret <vscale x 1 x half> %a613}614 615define <vscale x 1 x half> @intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {616; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16:617; CHECK: # %bb.0: # %entry618; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma619; CHECK-NEXT: vfmin.vv v8, v8, v9, v0.t620; CHECK-NEXT: ret621entry:622 %a = call <vscale x 1 x half> @llvm.riscv.vfmin.mask.nxv1f16.nxv1f16(623 <vscale x 1 x half> poison,624 <vscale x 1 x half> %0,625 <vscale x 1 x half> %1,626 <vscale x 1 x i1> %2,627 iXLen %3, iXLen 3)628 629 ret <vscale x 1 x half> %a630}631 632define <vscale x 1 x half> @intrinsic_vfsgnj_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {633; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f16_nxv1f16_nxv1f16:634; CHECK: # %bb.0: # %entry635; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma636; CHECK-NEXT: vfsgnj.vv v8, v8, v9, v0.t637; CHECK-NEXT: ret638entry:639 %a = call <vscale x 1 x half> @llvm.riscv.vfsgnj.mask.nxv1f16.nxv1f16(640 <vscale x 1 x half> poison,641 <vscale x 1 x half> %0,642 <vscale x 1 x half> %1,643 <vscale x 1 x i1> %2,644 iXLen %3, iXLen 3)645 646 ret <vscale x 1 x half> %a647}648 649define <vscale x 1 x i16> @intrinsic_vfclass_mask_v_nxv1i16_nxv1f16(650; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1f16:651; CHECK: # %bb.0: # %entry652; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma653; CHECK-NEXT: vfclass.v v8, v8, v0.t654; CHECK-NEXT: ret655 <vscale x 1 x half> %0,656 <vscale x 1 x i1> %1,657 iXLen %2) nounwind {658entry:659 %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16(660 <vscale x 1 x i16> poison,661 <vscale x 1 x half> %0,662 <vscale x 1 x i1> %1,663 iXLen %2, iXLen 3)664 665 ret <vscale x 1 x i16> %a666}667 668define <vscale x 1 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {669; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16:670; CHECK: # %bb.0: # %entry671; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma672; CHECK-NEXT: vfcvt.xu.f.v v8, v8, v0.t673; CHECK-NEXT: ret674entry:675 %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16(676 <vscale x 1 x i16> poison,677 <vscale x 1 x half> %0,678 <vscale x 1 x i1> %1,679 iXLen 7, iXLen %2, iXLen 3)680 681 ret <vscale x 1 x i16> %a682}683 684define <vscale x 1 x half> @intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {685; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16:686; CHECK: # %bb.0: # %entry687; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma688; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t689; CHECK-NEXT: ret690entry:691 %a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16(692 <vscale x 1 x half> poison,693 <vscale x 1 x i16> %0,694 <vscale x 1 x i1> %1,695 iXLen 7, iXLen %2, iXLen 3)696 697 ret <vscale x 1 x half> %a698}699 700define <vscale x 1 x i32> @intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {701; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma704; CHECK-NEXT: vfwcvt.xu.f.v v9, v8, v0.t705; CHECK-NEXT: vmv1r.v v8, v9706; CHECK-NEXT: ret707entry:708 %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16(709 <vscale x 1 x i32> poison,710 <vscale x 1 x half> %0,711 <vscale x 1 x i1> %1,712 iXLen 7, iXLen %2, iXLen 3)713 714 ret <vscale x 1 x i32> %a715}716 717define <vscale x 1 x half> @intrinsic_vfwcvt_mask_f.x.v_nxv1f16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {718; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f16_nxv1i8:719; CHECK: # %bb.0: # %entry720; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma721; CHECK-NEXT: vfwcvt.f.x.v v9, v8, v0.t722; CHECK-NEXT: vmv1r.v v8, v9723; CHECK-NEXT: ret724entry:725 %a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f16.nxv1i8(726 <vscale x 1 x half> poison,727 <vscale x 1 x i8> %0,728 <vscale x 1 x i1> %1,729 iXLen %2, iXLen 3)730 731 ret <vscale x 1 x half> %a732}733 734define <vscale x 1 x float> @intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {735; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16:736; CHECK: # %bb.0: # %entry737; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma738; CHECK-NEXT: vfwcvt.f.f.v v9, v8, v0.t739; CHECK-NEXT: vmv1r.v v8, v9740; CHECK-NEXT: ret741entry:742 %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16(743 <vscale x 1 x float> poison,744 <vscale x 1 x half> %0,745 <vscale x 1 x i1> %1,746 iXLen %2, iXLen 3)747 748 ret <vscale x 1 x float> %a749}750 751define <vscale x 1 x i8> @intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {752; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16:753; CHECK: # %bb.0: # %entry754; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma755; CHECK-NEXT: vfncvt.xu.f.w v9, v8, v0.t756; CHECK-NEXT: vmv1r.v v8, v9757; CHECK-NEXT: ret758entry:759 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16(760 <vscale x 1 x i8> poison,761 <vscale x 1 x half> %0,762 <vscale x 1 x i1> %1,763 iXLen 7, iXLen %2, iXLen 3)764 765 ret <vscale x 1 x i8> %a766}767 768define <vscale x 1 x half> @intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {769; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32:770; CHECK: # %bb.0: # %entry771; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma772; CHECK-NEXT: vfncvt.f.x.w v9, v8, v0.t773; CHECK-NEXT: vmv1r.v v8, v9774; CHECK-NEXT: ret775entry:776 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32(777 <vscale x 1 x half> poison,778 <vscale x 1 x i32> %0,779 <vscale x 1 x i1> %1,780 iXLen 7, iXLen %2, iXLen 3)781 782 ret <vscale x 1 x half> %a783}784 785define <vscale x 1 x half> @intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {786; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32:787; CHECK: # %bb.0: # %entry788; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma789; CHECK-NEXT: vfncvt.f.f.w v9, v8, v0.t790; CHECK-NEXT: vmv1r.v v8, v9791; CHECK-NEXT: ret792entry:793 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32(794 <vscale x 1 x half> poison,795 <vscale x 1 x float> %0,796 <vscale x 1 x i1> %1,797 iXLen 7, iXLen %2, iXLen 3)798 799 ret <vscale x 1 x half> %a800}801 802define <vscale x 1 x i8> @intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {803; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8:804; CHECK: # %bb.0: # %entry805; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma806; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t807; CHECK-NEXT: ret808entry:809 %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(810 <vscale x 1 x i8> %0,811 <vscale x 1 x i8> %1,812 iXLen %2,813 <vscale x 1 x i1> %3,814 iXLen %4, iXLen 3)815 816 ret <vscale x 1 x i8> %a817}818 819define <vscale x 1 x i8> @intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {820; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8:821; CHECK: # %bb.0: # %entry822; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma823; CHECK-NEXT: vslide1up.vx v9, v8, a0, v0.t824; CHECK-NEXT: vmv1r.v v8, v9825; CHECK-NEXT: ret826entry:827 %a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8(828 <vscale x 1 x i8> poison,829 <vscale x 1 x i8> %0,830 i8 %1,831 <vscale x 1 x i1> %2,832 iXLen %3, iXLen 3)833 834 ret <vscale x 1 x i8> %a835}836 837define <vscale x 1 x half> @intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {838; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16:839; CHECK: # %bb.0: # %entry840; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma841; CHECK-NEXT: vfslide1up.vf v9, v8, fa0, v0.t842; CHECK-NEXT: vmv1r.v v8, v9843; CHECK-NEXT: ret844entry:845 %a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(846 <vscale x 1 x half> poison,847 <vscale x 1 x half> %0,848 half %1,849 <vscale x 1 x i1> %2,850 iXLen %3, iXLen 3)851 852 ret <vscale x 1 x half> %a853}854 855define <vscale x 1 x i8> @intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {856; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8:857; CHECK: # %bb.0: # %entry858; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma859; CHECK-NEXT: vrgather.vv v10, v8, v9, v0.t860; CHECK-NEXT: vmv1r.v v8, v10861; CHECK-NEXT: ret862entry:863 %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.iXLen(864 <vscale x 1 x i8> poison,865 <vscale x 1 x i8> %0,866 <vscale x 1 x i8> %1,867 <vscale x 1 x i1> %2,868 iXLen %3, iXLen 3)869 870 ret <vscale x 1 x i8> %a871}872 873define <vscale x 1 x i8> @intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {874; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8:875; CHECK: # %bb.0: # %entry876; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma877; CHECK-NEXT: vrgatherei16.vv v10, v8, v9, v0.t878; CHECK-NEXT: vmv1r.v v8, v10879; CHECK-NEXT: ret880entry:881 %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(882 <vscale x 1 x i8> poison,883 <vscale x 1 x i8> %0,884 <vscale x 1 x i16> %1,885 <vscale x 1 x i1> %2,886 iXLen %3, iXLen 3)887 888 ret <vscale x 1 x i8> %a889}890 891define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i1> %0, iXLen %1) nounwind {892; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8:893; CHECK: # %bb.0: # %entry894; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma895; CHECK-NEXT: vid.v v8, v0.t896; CHECK-NEXT: ret897entry:898 %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(899 <vscale x 1 x i8> poison,900 <vscale x 1 x i1> %0,901 iXLen %1, iXLen 3)902 903 ret <vscale x 1 x i8> %a904}905 906define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {907; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:908; CHECK: # %bb.0: # %entry909; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma910; CHECK-NEXT: vmv1r.v v9, v0911; CHECK-NEXT: vmv1r.v v0, v8912; CHECK-NEXT: viota.m v8, v9, v0.t913; CHECK-NEXT: ret914entry:915 %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(916 <vscale x 1 x i8> poison,917 <vscale x 1 x i1> %0,918 <vscale x 1 x i1> %1,919 iXLen %2, iXLen 3)920 921 ret <vscale x 1 x i8> %a922}923 924define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {925; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1:926; CHECK: # %bb.0: # %entry927; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma928; CHECK-NEXT: vmv1r.v v9, v0929; CHECK-NEXT: vmv1r.v v0, v8930; CHECK-NEXT: vmsbf.m v8, v9, v0.t931; CHECK-NEXT: vmv1r.v v0, v8932; CHECK-NEXT: ret933entry:934 %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(935 <vscale x 1 x i1> poison,936 <vscale x 1 x i1> %0,937 <vscale x 1 x i1> %1,938 iXLen %2)939 ret <vscale x 1 x i1> %a940}941 942define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {943; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16:944; CHECK: # %bb.0: # %entry945; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma946; CHECK-NEXT: vmfeq.vv v0, v9, v10947; CHECK-NEXT: vmfeq.vv v0, v9, v10, v0.t948; CHECK-NEXT: ret949entry:950 %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(951 <vscale x 1 x half> %1,952 <vscale x 1 x half> %2,953 iXLen %3)954 %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(955 <vscale x 1 x i1> poison,956 <vscale x 1 x half> %1,957 <vscale x 1 x half> %2,958 <vscale x 1 x i1> %mask,959 iXLen %3)960 961 ret <vscale x 1 x i1> %a962}963 964define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {965; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:966; RV32: # %bb.0: # %entry967; RV32-NEXT: addi sp, sp, -16968; RV32-NEXT: sw a0, 8(sp)969; RV32-NEXT: sw a1, 12(sp)970; RV32-NEXT: addi a0, sp, 8971; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma972; RV32-NEXT: vlse64.v v9, (a0), zero973; RV32-NEXT: vmseq.vv v0, v8, v9, v0.t974; RV32-NEXT: addi sp, sp, 16975; RV32-NEXT: ret976;977; RV64-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:978; RV64: # %bb.0: # %entry979; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma980; RV64-NEXT: vmseq.vx v0, v8, a0, v0.t981; RV64-NEXT: ret982entry:983 %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(984 <vscale x 1 x i1> poison,985 <vscale x 1 x i64> %0,986 i64 %1,987 <vscale x 1 x i1> %2,988 iXLen %3)989 990 ret <vscale x 1 x i1> %a991}992 993define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {994; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:995; RV32: # %bb.0: # %entry996; RV32-NEXT: addi sp, sp, -16997; RV32-NEXT: sw a0, 8(sp)998; RV32-NEXT: sw a1, 12(sp)999; RV32-NEXT: addi a0, sp, 81000; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1001; RV32-NEXT: vlse64.v v9, (a0), zero1002; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t1003; RV32-NEXT: addi sp, sp, 161004; RV32-NEXT: ret1005;1006; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:1007; RV64: # %bb.0: # %entry1008; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1009; RV64-NEXT: vmslt.vx v8, v8, a0, v0.t1010; RV64-NEXT: vmxor.mm v0, v8, v01011; RV64-NEXT: ret1012entry:1013 %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(1014 <vscale x 1 x i1> poison,1015 <vscale x 1 x i64> %0,1016 i64 %1,1017 <vscale x 1 x i1> %2,1018 iXLen %3)1019 1020 ret <vscale x 1 x i1> %a1021}1022 1023define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {1024; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:1025; CHECK: # %bb.0: # %entry1026; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma1027; CHECK-NEXT: vmv1r.v v9, v01028; CHECK-NEXT: vmv1r.v v0, v81029; CHECK-NEXT: vmsbf.m v8, v9, v0.t1030; CHECK-NEXT: vmv1r.v v0, v81031; CHECK-NEXT: ret1032entry:1033 %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(1034 <vscale x 64 x i1> poison,1035 <vscale x 64 x i1> %0,1036 <vscale x 64 x i1> %1,1037 iXLen %2)1038 1039 ret <vscale x 64 x i1> %a1040}1041