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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh\5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i64> @intrinsic_vle_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vle_mask_nxv1i64_nxv1i64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu11; CHECK-NEXT: vle64.v v8, (a0), v0.t12; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(15 <vscale x 1 x i64> %0,16 ptr %1,17 <vscale x 1 x i1> %2,18 iXLen %3, iXLen 0)19 20 ret <vscale x 1 x i64> %a21}22 23define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {24; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64:25; RV32: # %bb.0: # %entry26; RV32-NEXT: vsetvli zero, a1, e64, m1, tu, mu27; RV32-NEXT: vle64ff.v v8, (a0), v0.t28; RV32-NEXT: csrr a0, vl29; RV32-NEXT: sw a0, 0(a2)30; RV32-NEXT: ret31;32; RV64-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64:33; RV64: # %bb.0: # %entry34; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu35; RV64-NEXT: vle64ff.v v8, (a0), v0.t36; RV64-NEXT: csrr a0, vl37; RV64-NEXT: sd a0, 0(a2)38; RV64-NEXT: ret39entry:40 %a = call { <vscale x 1 x i64>, iXLen } @llvm.riscv.vleff.mask.nxv1i64(41 <vscale x 1 x i64> %0,42 ptr %1,43 <vscale x 1 x i1> %2,44 iXLen %3, iXLen 0)45 %b = extractvalue { <vscale x 1 x i64>, iXLen } %a, 046 %c = extractvalue { <vscale x 1 x i64>, iXLen } %a, 147 store iXLen %c, ptr %448 49 ret <vscale x 1 x i64> %b50}51 52define <vscale x 1 x i64> @intrinsic_vlse_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {53; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i64_nxv1i64:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vsetvli zero, a2, e64, m1, tu, mu56; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t57; CHECK-NEXT: ret58entry:59 %a = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64(60 <vscale x 1 x i64> %0,61 ptr %1,62 iXLen %2,63 <vscale x 1 x i1> %3,64 iXLen %4, iXLen 0)65 66 ret <vscale x 1 x i64> %a67}68 69define <vscale x 1 x i8> @intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1iXLen(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x iXLen> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {70entry:71 %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1iXLen(72 <vscale x 1 x i8> %0,73 ptr %1,74 <vscale x 1 x iXLen> %2,75 <vscale x 1 x i1> %3,76 iXLen %4, iXLen 0)77 78 ret <vscale x 1 x i8> %a79}80 81define <vscale x 1 x i8> @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {82; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu85; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t86; CHECK-NEXT: ret87entry:88 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(89 <vscale x 1 x i8> %0,90 <vscale x 1 x i8> %1,91 <vscale x 1 x i8> %2,92 <vscale x 1 x i1> %3,93 iXLen %4, iXLen 0)94 95 ret <vscale x 1 x i8> %a96}97 98define <vscale x 1 x i16> @intrinsic_vwadd_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {99; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i16_nxv1i8_nxv1i8:100; CHECK: # %bb.0: # %entry101; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu102; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t103; CHECK-NEXT: ret104entry:105 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.mask.nxv1i16.nxv1i8.nxv1i8(106 <vscale x 1 x i16> %0,107 <vscale x 1 x i8> %1,108 <vscale x 1 x i8> %2,109 <vscale x 1 x i1> %3,110 iXLen %4, iXLen 0)111 112 ret <vscale x 1 x i16> %a113}114 115define <vscale x 1 x i8> @intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {116; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu119; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t120; CHECK-NEXT: ret121entry:122 %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(123 <vscale x 1 x i8> %0,124 <vscale x 1 x i8> %1,125 i8 %2,126 <vscale x 1 x i1> %3,127 iXLen %4, iXLen 0)128 129 ret <vscale x 1 x i8> %a130}131 132define <vscale x 1 x i8> @intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {133; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8:134; CHECK: # %bb.0: # %entry135; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu136; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t137; CHECK-NEXT: ret138entry:139 %a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(140 <vscale x 1 x i8> %0,141 <vscale x 1 x i8> %1,142 i8 -9,143 <vscale x 1 x i1> %2,144 iXLen %3, iXLen 0)145 146 ret <vscale x 1 x i8> %a147}148 149define <vscale x 1 x i64> @intrinsic_vzext_mask_vf2_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {150; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv1i64:151; CHECK: # %bb.0: # %entry152; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu153; CHECK-NEXT: vzext.vf2 v8, v9, v0.t154; CHECK-NEXT: ret155entry:156 %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32(157 <vscale x 1 x i64> %1,158 <vscale x 1 x i32> %2,159 <vscale x 1 x i1> %0,160 iXLen %3, iXLen 0)161 162 ret <vscale x 1 x i64> %a163}164 165define <vscale x 1 x i64> @intrinsic_vzext_mask_vf4_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {166; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv1i64:167; CHECK: # %bb.0: # %entry168; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu169; CHECK-NEXT: vzext.vf4 v8, v9, v0.t170; CHECK-NEXT: ret171entry:172 %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i16(173 <vscale x 1 x i64> %1,174 <vscale x 1 x i16> %2,175 <vscale x 1 x i1> %0,176 iXLen %3, iXLen 0)177 178 ret <vscale x 1 x i64> %a179}180define <vscale x 1 x i64> @intrinsic_vzext_mask_vf8_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {181; CHECK-LABEL: intrinsic_vzext_mask_vf8_nxv1i64:182; CHECK: # %bb.0: # %entry183; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu184; CHECK-NEXT: vzext.vf8 v8, v9, v0.t185; CHECK-NEXT: ret186entry:187 %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8(188 <vscale x 1 x i64> %1,189 <vscale x 1 x i8> %2,190 <vscale x 1 x i1> %0,191 iXLen %3, iXLen 0)192 193 ret <vscale x 1 x i64> %a194}195 196define <vscale x 1 x i8> @intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {197; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8:198; CHECK: # %bb.0: # %entry199; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu200; CHECK-NEXT: vand.vv v8, v9, v10, v0.t201; CHECK-NEXT: ret202entry:203 %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.nxv1i8(204 <vscale x 1 x i8> %0,205 <vscale x 1 x i8> %1,206 <vscale x 1 x i8> %2,207 <vscale x 1 x i1> %3,208 iXLen %4, iXLen 0)209 210 ret <vscale x 1 x i8> %a211}212 213define <vscale x 1 x i8> @intrinsic_vsll_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {214; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i8_nxv1i8_nxv1i8:215; CHECK: # %bb.0: # %entry216; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu217; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t218; CHECK-NEXT: ret219entry:220 %a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8(221 <vscale x 1 x i8> %0,222 <vscale x 1 x i8> %1,223 <vscale x 1 x i8> %2,224 <vscale x 1 x i1> %3,225 iXLen %4, iXLen 0)226 227 ret <vscale x 1 x i8> %a228}229 230define <vscale x 1 x i8> @intrinsic_vnsra_mask_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {231; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i8_nxv1i16_nxv1i8:232; CHECK: # %bb.0: # %entry233; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu234; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t235; CHECK-NEXT: ret236entry:237 %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.nxv1i8(238 <vscale x 1 x i8> %0,239 <vscale x 1 x i16> %1,240 <vscale x 1 x i8> %2,241 <vscale x 1 x i1> %3,242 iXLen %4, iXLen 0)243 244 ret <vscale x 1 x i8> %a245}246 247define <vscale x 1 x i8> @intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {248; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu251; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t252; CHECK-NEXT: ret253entry:254 %a = call <vscale x 1 x i8> @llvm.riscv.vmin.mask.nxv1i8.nxv1i8(255 <vscale x 1 x i8> %0,256 <vscale x 1 x i8> %1,257 <vscale x 1 x i8> %2,258 <vscale x 1 x i1> %3,259 iXLen %4, iXLen 0)260 261 ret <vscale x 1 x i8> %a262}263 264define <vscale x 1 x i8> @intrinsic_vdiv_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {265; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i8_nxv1i8_nxv1i8:266; CHECK: # %bb.0: # %entry267; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu268; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t269; CHECK-NEXT: ret270entry:271 %a = call <vscale x 1 x i8> @llvm.riscv.vdiv.mask.nxv1i8.nxv1i8(272 <vscale x 1 x i8> %0,273 <vscale x 1 x i8> %1,274 <vscale x 1 x i8> %2,275 <vscale x 1 x i1> %3,276 iXLen %4, iXLen 0)277 278 ret <vscale x 1 x i8> %a279}280 281define <vscale x 1 x i16> @intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {282; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8:283; CHECK: # %bb.0: # %entry284; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu285; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t286; CHECK-NEXT: ret287entry:288 %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.nxv1i8(289 <vscale x 1 x i16> %0,290 <vscale x 1 x i8> %1,291 <vscale x 1 x i8> %2,292 <vscale x 1 x i1> %3,293 iXLen %4, iXLen 0)294 295 ret <vscale x 1 x i16> %a296}297 298define <vscale x 1 x i8> @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {299; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8:300; CHECK: # %bb.0: # %entry301; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu302; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t303; CHECK-NEXT: ret304entry:305 %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(306 <vscale x 1 x i8> %0,307 <vscale x 1 x i8> %1,308 <vscale x 1 x i8> %2,309 <vscale x 1 x i1> %3,310 iXLen %4, iXLen 0)311 312 ret <vscale x 1 x i8> %a313}314 315define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {316; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8:317; CHECK: # %bb.0: # %entry318; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu319; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t320; CHECK-NEXT: ret321entry:322 %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8(323 <vscale x 1 x i16> %0,324 <vscale x 1 x i8> %1,325 <vscale x 1 x i8> %2,326 <vscale x 1 x i1> %3,327 iXLen %4, iXLen 0)328 329 ret <vscale x 1 x i16> %a330}331 332define <vscale x 1 x i8> @intrinsic_vsadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {333; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:334; CHECK: # %bb.0: # %entry335; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu336; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t337; CHECK-NEXT: ret338entry:339 %a = call <vscale x 1 x i8> @llvm.riscv.vsadd.mask.nxv1i8.nxv1i8(340 <vscale x 1 x i8> %0,341 <vscale x 1 x i8> %1,342 <vscale x 1 x i8> %2,343 <vscale x 1 x i1> %3,344 iXLen %4, iXLen 0)345 346 ret <vscale x 1 x i8> %a347}348 349define <vscale x 1 x i8> @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {350; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:351; CHECK: # %bb.0: # %entry352; CHECK-NEXT: csrwi vxrm, 1353; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu354; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t355; CHECK-NEXT: ret356entry:357 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8(358 <vscale x 1 x i8> %0,359 <vscale x 1 x i8> %1,360 <vscale x 1 x i8> %2,361 <vscale x 1 x i1> %3,362 iXLen 1, iXLen %4, iXLen 0)363 364 ret <vscale x 1 x i8> %a365}366 367define <vscale x 1 x i8> @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {368; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8:369; CHECK: # %bb.0: # %entry370; CHECK-NEXT: csrwi vxrm, 0371; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu372; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t373; CHECK-NEXT: ret374entry:375 %a = call <vscale x 1 x i8> @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8(376 <vscale x 1 x i8> %0,377 <vscale x 1 x i8> %1,378 <vscale x 1 x i8> %2,379 <vscale x 1 x i1> %3,380 iXLen 0, iXLen %4, iXLen 0)381 382 ret <vscale x 1 x i8> %a383}384 385define <vscale x 1 x i8> @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {386; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8:387; CHECK: # %bb.0: # %entry388; CHECK-NEXT: csrwi vxrm, 0389; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu390; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t391; CHECK-NEXT: ret392entry:393 %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8(394 <vscale x 1 x i8> %0,395 <vscale x 1 x i8> %1,396 <vscale x 1 x i8> %2,397 <vscale x 1 x i1> %3,398 iXLen 0, iXLen %4, iXLen 0)399 400 ret <vscale x 1 x i8> %a401}402 403define <vscale x 1 x i8> @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {404; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: csrwi vxrm, 0407; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu408; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t409; CHECK-NEXT: ret410entry:411 %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8(412 <vscale x 1 x i8> %0,413 <vscale x 1 x i16> %1,414 <vscale x 1 x i8> %2,415 <vscale x 1 x i1> %3,416 iXLen 0, iXLen %4, iXLen 0)417 418 ret <vscale x 1 x i8> %a419}420 421define <vscale x 1 x half> @intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {422; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:423; CHECK: # %bb.0: # %entry424; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu425; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t426; CHECK-NEXT: ret427entry:428 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16(429 <vscale x 1 x half> %0,430 <vscale x 1 x half> %1,431 <vscale x 1 x half> %2,432 <vscale x 1 x i1> %3,433 iXLen 7, iXLen %4, iXLen 0)434 435 ret <vscale x 1 x half> %a436}437 438define <vscale x 1 x float> @intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {439; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16:440; CHECK: # %bb.0: # %entry441; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu442; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t443; CHECK-NEXT: ret444entry:445 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16(446 <vscale x 1 x float> %0,447 <vscale x 1 x half> %1,448 <vscale x 1 x half> %2,449 <vscale x 1 x i1> %3,450 iXLen 7, iXLen %4, iXLen 0)451 452 ret <vscale x 1 x float> %a453}454 455define <vscale x 1 x half> @intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {456; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16:457; CHECK: # %bb.0: # %entry458; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu459; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t460; CHECK-NEXT: ret461entry:462 %a = call <vscale x 1 x half> @llvm.riscv.vfmul.mask.nxv1f16.nxv1f16(463 <vscale x 1 x half> %0,464 <vscale x 1 x half> %1,465 <vscale x 1 x half> %2,466 <vscale x 1 x i1> %3,467 iXLen 7, iXLen %4, iXLen 0)468 469 ret <vscale x 1 x half> %a470}471 472define <vscale x 1 x half> @intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {473; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16_nxv1f16:474; CHECK: # %bb.0: # %entry475; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu476; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t477; CHECK-NEXT: ret478entry:479 %a = call <vscale x 1 x half> @llvm.riscv.vfdiv.mask.nxv1f16.nxv1f16(480 <vscale x 1 x half> %0,481 <vscale x 1 x half> %1,482 <vscale x 1 x half> %2,483 <vscale x 1 x i1> %3,484 iXLen 7, iXLen %4, iXLen 0)485 486 ret <vscale x 1 x half> %a487}488 489define <vscale x 1 x half> @intrinsic_vfrdiv_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {490; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f16_nxv1f16_f16:491; CHECK: # %bb.0: # %entry492; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu493; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t494; CHECK-NEXT: ret495entry:496 %a = call <vscale x 1 x half> @llvm.riscv.vfrdiv.mask.nxv1f16.f16(497 <vscale x 1 x half> %0,498 <vscale x 1 x half> %1,499 half %2,500 <vscale x 1 x i1> %3,501 iXLen 7, iXLen %4, iXLen 0)502 503 ret <vscale x 1 x half> %a504}505 506define <vscale x 1 x float> @intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {507; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16:508; CHECK: # %bb.0: # %entry509; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu510; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t511; CHECK-NEXT: ret512entry:513 %a = call <vscale x 1 x float> @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.nxv1f16(514 <vscale x 1 x float> %0,515 <vscale x 1 x half> %1,516 <vscale x 1 x half> %2,517 <vscale x 1 x i1> %3,518 iXLen 7, iXLen %4, iXLen 0)519 520 ret <vscale x 1 x float> %a521}522 523define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {524; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:525; CHECK: # %bb.0: # %entry526; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu527; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t528; CHECK-NEXT: ret529entry:530 %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(531 <vscale x 1 x half> %0,532 <vscale x 1 x half> %1,533 <vscale x 1 x half> %2,534 <vscale x 1 x i1> %3,535 iXLen 7, iXLen %4, iXLen 0)536 537 ret <vscale x 1 x half> %a538}539 540define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {541; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:542; CHECK: # %bb.0: # %entry543; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu544; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t545; CHECK-NEXT: ret546entry:547 %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(548 <vscale x 1 x float> %0,549 <vscale x 1 x half> %1,550 <vscale x 1 x half> %2,551 <vscale x 1 x i1> %3,552 iXLen 7, iXLen %4, iXLen 0)553 ret <vscale x 1 x float> %a554}555 556define <vscale x 1 x half> @intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {557; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16:558; CHECK: # %bb.0: # %entry559; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu560; CHECK-NEXT: vfsqrt.v v8, v9, v0.t561; CHECK-NEXT: ret562entry:563 %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(564 <vscale x 1 x half> %0,565 <vscale x 1 x half> %1,566 <vscale x 1 x i1> %2,567 iXLen 7, iXLen %3, iXLen 0)568 569 ret <vscale x 1 x half> %a570}571 572define <vscale x 1 x half> @intrinsic_vfrsqrt7_mask_v_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {573; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv1f16_nxv1f16:574; CHECK: # %bb.0: # %entry575; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu576; CHECK-NEXT: vfrsqrt7.v v8, v9, v0.t577; CHECK-NEXT: ret578entry:579 %a = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.mask.nxv1f16(580 <vscale x 1 x half> %1,581 <vscale x 1 x half> %2,582 <vscale x 1 x i1> %0,583 iXLen %3, iXLen 0)584 585 ret <vscale x 1 x half> %a586}587 588define <vscale x 1 x half> @intrinsic_vfrec7_mask_v_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {589; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f16_nxv1f16:590; CHECK: # %bb.0: # %entry591; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu592; CHECK-NEXT: vfrec7.v v8, v9, v0.t593; CHECK-NEXT: ret594entry:595 %a = call <vscale x 1 x half> @llvm.riscv.vfrec7.mask.nxv1f16(596 <vscale x 1 x half> %1,597 <vscale x 1 x half> %2,598 <vscale x 1 x i1> %0,599 iXLen 7, iXLen %3, iXLen 0)600 601 ret <vscale x 1 x half> %a602}603 604define <vscale x 1 x half> @intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {605; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16:606; CHECK: # %bb.0: # %entry607; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu608; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t609; CHECK-NEXT: ret610entry:611 %a = call <vscale x 1 x half> @llvm.riscv.vfmin.mask.nxv1f16.nxv1f16(612 <vscale x 1 x half> %0,613 <vscale x 1 x half> %1,614 <vscale x 1 x half> %2,615 <vscale x 1 x i1> %3,616 iXLen %4, iXLen 0)617 618 ret <vscale x 1 x half> %a619}620 621define <vscale x 1 x half> @intrinsic_vfsgnj_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {622; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f16_nxv1f16_nxv1f16:623; CHECK: # %bb.0: # %entry624; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu625; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t626; CHECK-NEXT: ret627entry:628 %a = call <vscale x 1 x half> @llvm.riscv.vfsgnj.mask.nxv1f16.nxv1f16(629 <vscale x 1 x half> %0,630 <vscale x 1 x half> %1,631 <vscale x 1 x half> %2,632 <vscale x 1 x i1> %3,633 iXLen %4, iXLen 0)634 635 ret <vscale x 1 x half> %a636}637 638define <vscale x 1 x i16> @intrinsic_vfclass_mask_v_nxv1i16_nxv1f16(639; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1f16:640; CHECK: # %bb.0: # %entry641; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu642; CHECK-NEXT: vfclass.v v8, v9, v0.t643; CHECK-NEXT: ret644 <vscale x 1 x i16> %0,645 <vscale x 1 x half> %1,646 <vscale x 1 x i1> %2,647 iXLen %3) nounwind {648entry:649 %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16(650 <vscale x 1 x i16> %0,651 <vscale x 1 x half> %1,652 <vscale x 1 x i1> %2,653 iXLen %3, iXLen 0)654 655 ret <vscale x 1 x i16> %a656}657 658define <vscale x 1 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {659; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16:660; CHECK: # %bb.0: # %entry661; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu662; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t663; CHECK-NEXT: ret664entry:665 %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16(666 <vscale x 1 x i16> %0,667 <vscale x 1 x half> %1,668 <vscale x 1 x i1> %2,669 iXLen 7, iXLen %3, iXLen 0)670 671 ret <vscale x 1 x i16> %a672}673 674define <vscale x 1 x half> @intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {675; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16:676; CHECK: # %bb.0: # %entry677; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu678; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t679; CHECK-NEXT: ret680entry:681 %a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16(682 <vscale x 1 x half> %0,683 <vscale x 1 x i16> %1,684 <vscale x 1 x i1> %2,685 iXLen 7, iXLen %3, iXLen 0)686 687 ret <vscale x 1 x half> %a688}689 690define <vscale x 1 x i32> @intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {691; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16:692; CHECK: # %bb.0: # %entry693; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu694; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t695; CHECK-NEXT: ret696entry:697 %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16(698 <vscale x 1 x i32> %0,699 <vscale x 1 x half> %1,700 <vscale x 1 x i1> %2,701 iXLen 7, iXLen %3, iXLen 0)702 703 ret <vscale x 1 x i32> %a704}705 706define <vscale x 1 x half> @intrinsic_vfwcvt_mask_f.x.v_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {707; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f16_nxv1i8:708; CHECK: # %bb.0: # %entry709; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu710; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t711; CHECK-NEXT: ret712entry:713 %a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f16.nxv1i8(714 <vscale x 1 x half> %0,715 <vscale x 1 x i8> %1,716 <vscale x 1 x i1> %2,717 iXLen %3, iXLen 0)718 719 ret <vscale x 1 x half> %a720}721 722define <vscale x 1 x float> @intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {723; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16:724; CHECK: # %bb.0: # %entry725; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu726; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t727; CHECK-NEXT: ret728entry:729 %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16(730 <vscale x 1 x float> %0,731 <vscale x 1 x half> %1,732 <vscale x 1 x i1> %2,733 iXLen %3, iXLen 0)734 735 ret <vscale x 1 x float> %a736}737 738define <vscale x 1 x i8> @intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {739; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16:740; CHECK: # %bb.0: # %entry741; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu742; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t743; CHECK-NEXT: ret744entry:745 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16(746 <vscale x 1 x i8> %0,747 <vscale x 1 x half> %1,748 <vscale x 1 x i1> %2,749 iXLen 7, iXLen %3, iXLen 0)750 751 ret <vscale x 1 x i8> %a752}753 754define <vscale x 1 x half> @intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {755; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32:756; CHECK: # %bb.0: # %entry757; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu758; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t759; CHECK-NEXT: ret760entry:761 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32(762 <vscale x 1 x half> %0,763 <vscale x 1 x i32> %1,764 <vscale x 1 x i1> %2,765 iXLen 7, iXLen %3, iXLen 0)766 767 ret <vscale x 1 x half> %a768}769 770define <vscale x 1 x half> @intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x half> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {771; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32:772; CHECK: # %bb.0: # %entry773; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu774; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t775; CHECK-NEXT: ret776entry:777 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32(778 <vscale x 1 x half> %0,779 <vscale x 1 x float> %1,780 <vscale x 1 x i1> %2,781 iXLen 7, iXLen %3, iXLen 0)782 783 ret <vscale x 1 x half> %a784}785 786define <vscale x 1 x i8> @intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {787; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8:788; CHECK: # %bb.0: # %entry789; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu790; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t791; CHECK-NEXT: ret792entry:793 %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(794 <vscale x 1 x i8> %0,795 <vscale x 1 x i8> %1,796 iXLen %2,797 <vscale x 1 x i1> %3,798 iXLen %4, iXLen 0)799 800 ret <vscale x 1 x i8> %a801}802 803define <vscale x 1 x i8> @intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {804; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8:805; CHECK: # %bb.0: # %entry806; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu807; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t808; CHECK-NEXT: ret809entry:810 %a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8(811 <vscale x 1 x i8> %0,812 <vscale x 1 x i8> %1,813 i8 %2,814 <vscale x 1 x i1> %3,815 iXLen %4, iXLen 0)816 817 ret <vscale x 1 x i8> %a818}819 820define <vscale x 1 x half> @intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {821; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16:822; CHECK: # %bb.0: # %entry823; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu824; CHECK-NEXT: vfslide1up.vf v8, v9, fa0, v0.t825; CHECK-NEXT: ret826entry:827 %a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(828 <vscale x 1 x half> %0,829 <vscale x 1 x half> %1,830 half %2,831 <vscale x 1 x i1> %3,832 iXLen %4, iXLen 0)833 834 ret <vscale x 1 x half> %a835}836 837define <vscale x 1 x i8> @intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {838; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8:839; CHECK: # %bb.0: # %entry840; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu841; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t842; CHECK-NEXT: ret843entry:844 %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.iXLen(845 <vscale x 1 x i8> %0,846 <vscale x 1 x i8> %1,847 <vscale x 1 x i8> %2,848 <vscale x 1 x i1> %3,849 iXLen %4, iXLen 0)850 851 ret <vscale x 1 x i8> %a852}853 854define <vscale x 1 x i8> @intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {855; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8:856; CHECK: # %bb.0: # %entry857; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu858; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t859; CHECK-NEXT: ret860entry:861 %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(862 <vscale x 1 x i8> %0,863 <vscale x 1 x i8> %1,864 <vscale x 1 x i16> %2,865 <vscale x 1 x i1> %3,866 iXLen %4, iXLen 0)867 868 ret <vscale x 1 x i8> %a869}870 871define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {872; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8:873; CHECK: # %bb.0: # %entry874; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu875; CHECK-NEXT: vid.v v8, v0.t876; CHECK-NEXT: ret877entry:878 %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(879 <vscale x 1 x i8> %0,880 <vscale x 1 x i1> %1,881 iXLen %2, iXLen 0)882 883 ret <vscale x 1 x i8> %a884}885 886define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {887; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:888; CHECK: # %bb.0: # %entry889; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu890; CHECK-NEXT: viota.m v8, v0, v0.t891; CHECK-NEXT: ret892entry:893 %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(894 <vscale x 1 x i8> %0,895 <vscale x 1 x i1> %1,896 <vscale x 1 x i1> %1,897 iXLen %2, iXLen 0)898 899 ret <vscale x 1 x i8> %a900}901