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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \3; RUN: < %s | FileCheck %s4 5define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tumu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {6; CHECK-LABEL: intrinsic_vslide1down_mask_tumu_vx_nxv1i64_nxv1i64_i64:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma9; CHECK-NEXT: slli a3, a3, 110; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma11; CHECK-NEXT: vslide1down.vx v9, v9, a012; CHECK-NEXT: vslide1down.vx v9, v9, a113; CHECK-NEXT: vsetvli zero, a2, e64, m1, tu, ma14; CHECK-NEXT: vmerge.vvm v8, v8, v9, v015; CHECK-NEXT: ret16entry:17 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(18 <vscale x 1 x i64> %0,19 <vscale x 1 x i64> %1,20 i64 %2,21 <vscale x 1 x i1> %3,22 i32 %4, i32 0)23 24 ret <vscale x 1 x i64> %a25}26 27define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tamu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {28; CHECK-LABEL: intrinsic_vslide1down_mask_tamu_vx_nxv1i64_nxv1i64_i64:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma31; CHECK-NEXT: slli a3, a3, 132; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma33; CHECK-NEXT: vslide1down.vx v9, v9, a034; CHECK-NEXT: vslide1down.vx v9, v9, a135; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma36; CHECK-NEXT: vmerge.vvm v8, v8, v9, v037; CHECK-NEXT: ret38entry:39 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(40 <vscale x 1 x i64> %0,41 <vscale x 1 x i64> %1,42 i64 %2,43 <vscale x 1 x i1> %3,44 i32 %4, i32 1)45 46 ret <vscale x 1 x i64> %a47}48 49; Fallback vslide1 to mask undisturbed until InsertVSETVLI supports mask agnostic.50define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tuma_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {51; CHECK-LABEL: intrinsic_vslide1down_mask_tuma_vx_nxv1i64_nxv1i64_i64:52; CHECK: # %bb.0: # %entry53; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma54; CHECK-NEXT: slli a3, a3, 155; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma56; CHECK-NEXT: vslide1down.vx v9, v9, a057; CHECK-NEXT: vslide1down.vx v9, v9, a158; CHECK-NEXT: vsetvli zero, a2, e64, m1, tu, ma59; CHECK-NEXT: vmerge.vvm v8, v8, v9, v060; CHECK-NEXT: ret61entry:62 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(63 <vscale x 1 x i64> %0,64 <vscale x 1 x i64> %1,65 i64 %2,66 <vscale x 1 x i1> %3,67 i32 %4, i32 2)68 69 ret <vscale x 1 x i64> %a70}71 72; Fallback vslide1 to mask undisturbed until InsertVSETVLI supports mask agnostic.73define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tama_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {74; CHECK-LABEL: intrinsic_vslide1down_mask_tama_vx_nxv1i64_nxv1i64_i64:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, ma77; CHECK-NEXT: slli a2, a2, 178; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma79; CHECK-NEXT: vslide1down.vx v8, v8, a080; CHECK-NEXT: vslide1down.vx v8, v8, a181; CHECK-NEXT: ret82entry:83 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(84 <vscale x 1 x i64> poison,85 <vscale x 1 x i64> %0,86 i64 %1,87 <vscale x 1 x i1> %2,88 i32 %3, i32 3)89 90 ret <vscale x 1 x i64> %a91}92 93define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tama_undef_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {94; CHECK-LABEL: intrinsic_vslide1down_mask_tama_undef_mask_vx_nxv1i64_nxv1i64_i64:95; CHECK: # %bb.0: # %entry96; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, ma97; CHECK-NEXT: slli a2, a2, 198; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma99; CHECK-NEXT: vslide1down.vx v8, v8, a0100; CHECK-NEXT: vslide1down.vx v8, v8, a1101; CHECK-NEXT: ret102entry:103 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(104 <vscale x 1 x i64> poison,105 <vscale x 1 x i64> %0,106 i64 %1,107 <vscale x 1 x i1> poison,108 i32 %2, i32 3)109 110 ret <vscale x 1 x i64> %a111}112