127 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV324; RUN: llc -mtriple=riscv64 -mattr=+m,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV646 7%struct = type { i64, i64, ptr, i32, i32, i32, [4 x i32] }8 9define void @complex_gep(ptr %p, <vscale x 2 x i64> %vec.ind, <vscale x 2 x i1> %m) {10; RV32-LABEL: complex_gep:11; RV32: # %bb.0:12; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma13; RV32-NEXT: vnsrl.wi v10, v8, 014; RV32-NEXT: li a1, 4815; RV32-NEXT: addi a0, a0, 2816; RV32-NEXT: vmul.vx v8, v10, a117; RV32-NEXT: vmv.v.i v9, 018; RV32-NEXT: vsoxei32.v v9, (a0), v8, v0.t19; RV32-NEXT: ret20;21; RV64-LABEL: complex_gep:22; RV64: # %bb.0:23; RV64-NEXT: li a1, 5624; RV64-NEXT: addi a0, a0, 3225; RV64-NEXT: vsetvli a2, zero, e64, m2, ta, ma26; RV64-NEXT: vmul.vx v8, v8, a127; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma28; RV64-NEXT: vmv.v.i v10, 029; RV64-NEXT: vsoxei64.v v10, (a0), v8, v0.t30; RV64-NEXT: ret31 %gep = getelementptr inbounds %struct, ptr %p, <vscale x 2 x i64> %vec.ind, i32 532 call void @llvm.masked.scatter.nxv2i32.nxv2p0(<vscale x 2 x i32> zeroinitializer, <vscale x 2 x ptr> %gep, i32 8, <vscale x 2 x i1> %m)33 ret void34}35 36define void @strided_store_zero_start(i64 %n, ptr %p) {37; RV32-LABEL: strided_store_zero_start:38; RV32: # %bb.0:39; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma40; RV32-NEXT: vid.v v841; RV32-NEXT: li a0, 4842; RV32-NEXT: addi a1, a2, 3243; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma44; RV32-NEXT: vnsrl.wi v8, v8, 045; RV32-NEXT: vmul.vx v8, v8, a046; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma47; RV32-NEXT: vmv.v.i v9, 048; RV32-NEXT: vsoxei32.v v9, (a1), v849; RV32-NEXT: ret50;51; RV64-LABEL: strided_store_zero_start:52; RV64: # %bb.0:53; RV64-NEXT: addi a0, a1, 3654; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma55; RV64-NEXT: vmv.v.i v8, 056; RV64-NEXT: li a1, 5657; RV64-NEXT: vsse64.v v8, (a0), a158; RV64-NEXT: ret59 %step = tail call <vscale x 1 x i64> @llvm.stepvector.nxv1i64()60 %gep = getelementptr inbounds %struct, ptr %p, <vscale x 1 x i64> %step, i32 661 tail call void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x ptr> %gep, i32 8, <vscale x 1 x i1> splat (i1 true))62 ret void63}64 65define void @strided_store_offset_start(i64 %n, ptr %p) {66; RV32-LABEL: strided_store_offset_start:67; RV32: # %bb.0:68; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma69; RV32-NEXT: vid.v v870; RV32-NEXT: vadd.vx v8, v8, a071; RV32-NEXT: li a0, 4872; RV32-NEXT: addi a1, a2, 3273; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma74; RV32-NEXT: vnsrl.wi v8, v8, 075; RV32-NEXT: vmul.vx v8, v8, a076; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma77; RV32-NEXT: vmv.v.i v9, 078; RV32-NEXT: vsoxei32.v v9, (a1), v879; RV32-NEXT: ret80;81; RV64-LABEL: strided_store_offset_start:82; RV64: # %bb.0:83; RV64-NEXT: slli a2, a0, 384; RV64-NEXT: slli a0, a0, 685; RV64-NEXT: vsetvli a3, zero, e64, m1, ta, ma86; RV64-NEXT: vmv.v.i v8, 087; RV64-NEXT: sub a0, a0, a288; RV64-NEXT: add a0, a1, a089; RV64-NEXT: addi a0, a0, 3690; RV64-NEXT: li a1, 5691; RV64-NEXT: vsse64.v v8, (a0), a192; RV64-NEXT: ret93 %step = tail call <vscale x 1 x i64> @llvm.stepvector.nxv1i64()94 %.splatinsert = insertelement <vscale x 1 x i64> poison, i64 %n, i64 095 %.splat = shufflevector <vscale x 1 x i64> %.splatinsert, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer96 %add = add <vscale x 1 x i64> %step, %.splat97 %gep = getelementptr inbounds %struct, ptr %p, <vscale x 1 x i64> %add, i32 698 tail call void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x ptr> %gep, i32 8, <vscale x 1 x i1> splat (i1 true))99 ret void100}101 102define void @stride_one_store(i64 %n, ptr %p) {103; RV32-LABEL: stride_one_store:104; RV32: # %bb.0:105; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma106; RV32-NEXT: vid.v v8107; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma108; RV32-NEXT: vnsrl.wi v8, v8, 0109; RV32-NEXT: vsll.vi v8, v8, 3110; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma111; RV32-NEXT: vmv.v.i v9, 0112; RV32-NEXT: vsoxei32.v v9, (a2), v8113; RV32-NEXT: ret114;115; RV64-LABEL: stride_one_store:116; RV64: # %bb.0:117; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma118; RV64-NEXT: vmv.v.i v8, 0119; RV64-NEXT: vs1r.v v8, (a1)120; RV64-NEXT: ret121 %step = tail call <vscale x 1 x i64> @llvm.stepvector.nxv1i64()122 %gep = getelementptr inbounds i64, ptr %p, <vscale x 1 x i64> %step123 tail call void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x ptr> %gep, i32 8, <vscale x 1 x i1> splat (i1 true))124 ret void125}126 127