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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3@__const.test.var_45 = private unnamed_addr constant [2 x i8] c"\D1S", align 14@__const.test.var_101 = private unnamed_addr constant [2 x i8] c"\830", align 15 6define dso_local void @test(ptr nocapture noundef %var_99) {7; CHECK-LABEL: test:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: lui a1, %hi(.L__const.test.var_45)10; CHECK-NEXT: addi a1, a1, %lo(.L__const.test.var_45)11; CHECK-NEXT: vsetivli zero, 2, e8, m4, ta, ma12; CHECK-NEXT: vle8.v v8, (a1)13; CHECK-NEXT: lui a1, %hi(.L__const.test.var_101)14; CHECK-NEXT: addi a1, a1, %lo(.L__const.test.var_101)15; CHECK-NEXT: vle8.v v12, (a1)16; CHECK-NEXT: li a1, 117; CHECK-NEXT: csrwi vxrm, 018; CHECK-NEXT: vmul.vx v16, v8, a119; CHECK-NEXT: vmv.x.s a1, v1620; CHECK-NEXT: vmsleu.vx v0, v8, a121; CHECK-NEXT: vssra.vv v8, v12, v822; CHECK-NEXT: vmerge.vvm v8, v8, v8, v023; CHECK-NEXT: vse8.v v8, (a0)24; CHECK-NEXT: ret25entry:26 %0 = tail call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.i64(<vscale x 32 x i8> poison, ptr nonnull @__const.test.var_45, i64 2)27 %1 = tail call <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 1, i64 2)28 %2 = tail call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.i64(<vscale x 32 x i8> poison, ptr nonnull @__const.test.var_101, i64 2)29 %3 = tail call i64 @llvm.riscv.vsetvli.i64(i64 32, i64 0, i64 2)30 %4 = tail call i8 @llvm.riscv.vmv.x.s.nxv32i8(<vscale x 32 x i8> %1)31 %5 = tail call <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %2, <vscale x 32 x i8> %0, i64 0, i64 2)32 %6 = tail call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8.i64(<vscale x 32 x i8> %0, i8 %4, i64 2)33 %7 = tail call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %5, <vscale x 32 x i8> %5, <vscale x 32 x i1> %6, i64 2)34 tail call void @llvm.riscv.vse.nxv32i8.i64(<vscale x 32 x i8> %7, ptr %var_99, i64 2)35 ret void36}37 38