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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-UNKNOWN3; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-2564; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-5125; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-UNKNOWN6; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-2567; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-5128; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-UNKNOWN9; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-25610; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-51211; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-UNKNOWN12; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-25613; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-51214 15;16; VECTOR_REVERSE - masks17;18 19define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {20; RV32-BITS-UNKNOWN-LABEL: reverse_nxv2i1:21; RV32-BITS-UNKNOWN: # %bb.0:22; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, ma23; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 024; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb25; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v026; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 227; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -128; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma29; RV32-BITS-UNKNOWN-NEXT: vid.v v930; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a031; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma32; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v933; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 034; RV32-BITS-UNKNOWN-NEXT: ret35;36; RV32-BITS-256-LABEL: reverse_nxv2i1:37; RV32-BITS-256: # %bb.0:38; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma39; RV32-BITS-256-NEXT: vmv.v.i v8, 040; RV32-BITS-256-NEXT: csrr a0, vlenb41; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v042; RV32-BITS-256-NEXT: srli a0, a0, 243; RV32-BITS-256-NEXT: addi a0, a0, -144; RV32-BITS-256-NEXT: vid.v v945; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a046; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v947; RV32-BITS-256-NEXT: vmsne.vi v0, v10, 048; RV32-BITS-256-NEXT: ret49;50; RV32-BITS-512-LABEL: reverse_nxv2i1:51; RV32-BITS-512: # %bb.0:52; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma53; RV32-BITS-512-NEXT: vmv.v.i v8, 054; RV32-BITS-512-NEXT: csrr a0, vlenb55; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v056; RV32-BITS-512-NEXT: srli a0, a0, 257; RV32-BITS-512-NEXT: addi a0, a0, -158; RV32-BITS-512-NEXT: vid.v v959; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a060; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v961; RV32-BITS-512-NEXT: vmsne.vi v0, v10, 062; RV32-BITS-512-NEXT: ret63;64; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i1:65; RV64-BITS-UNKNOWN: # %bb.0:66; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, ma67; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 068; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb69; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v070; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 271; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -172; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma73; RV64-BITS-UNKNOWN-NEXT: vid.v v974; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a075; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma76; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v977; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 078; RV64-BITS-UNKNOWN-NEXT: ret79;80; RV64-BITS-256-LABEL: reverse_nxv2i1:81; RV64-BITS-256: # %bb.0:82; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma83; RV64-BITS-256-NEXT: vmv.v.i v8, 084; RV64-BITS-256-NEXT: csrr a0, vlenb85; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v086; RV64-BITS-256-NEXT: srli a0, a0, 287; RV64-BITS-256-NEXT: addi a0, a0, -188; RV64-BITS-256-NEXT: vid.v v989; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a090; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v991; RV64-BITS-256-NEXT: vmsne.vi v0, v10, 092; RV64-BITS-256-NEXT: ret93;94; RV64-BITS-512-LABEL: reverse_nxv2i1:95; RV64-BITS-512: # %bb.0:96; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma97; RV64-BITS-512-NEXT: vmv.v.i v8, 098; RV64-BITS-512-NEXT: csrr a0, vlenb99; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0100; RV64-BITS-512-NEXT: srli a0, a0, 2101; RV64-BITS-512-NEXT: addi a0, a0, -1102; RV64-BITS-512-NEXT: vid.v v9103; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0104; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9105; RV64-BITS-512-NEXT: vmsne.vi v0, v10, 0106; RV64-BITS-512-NEXT: ret107 %res = call <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1> %a)108 ret <vscale x 2 x i1> %res109}110 111define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {112; RV32-BITS-UNKNOWN-LABEL: reverse_nxv4i1:113; RV32-BITS-UNKNOWN: # %bb.0:114; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma115; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0116; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb117; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0118; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1119; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1120; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma121; RV32-BITS-UNKNOWN-NEXT: vid.v v9122; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0123; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma124; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9125; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 0126; RV32-BITS-UNKNOWN-NEXT: ret127;128; RV32-BITS-256-LABEL: reverse_nxv4i1:129; RV32-BITS-256: # %bb.0:130; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma131; RV32-BITS-256-NEXT: vmv.v.i v8, 0132; RV32-BITS-256-NEXT: csrr a0, vlenb133; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0134; RV32-BITS-256-NEXT: srli a0, a0, 1135; RV32-BITS-256-NEXT: addi a0, a0, -1136; RV32-BITS-256-NEXT: vid.v v9137; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0138; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9139; RV32-BITS-256-NEXT: vmsne.vi v0, v10, 0140; RV32-BITS-256-NEXT: ret141;142; RV32-BITS-512-LABEL: reverse_nxv4i1:143; RV32-BITS-512: # %bb.0:144; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma145; RV32-BITS-512-NEXT: vmv.v.i v8, 0146; RV32-BITS-512-NEXT: csrr a0, vlenb147; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0148; RV32-BITS-512-NEXT: srli a0, a0, 1149; RV32-BITS-512-NEXT: addi a0, a0, -1150; RV32-BITS-512-NEXT: vid.v v9151; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0152; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9153; RV32-BITS-512-NEXT: vmsne.vi v0, v10, 0154; RV32-BITS-512-NEXT: ret155;156; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i1:157; RV64-BITS-UNKNOWN: # %bb.0:158; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma159; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0160; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb161; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0162; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1163; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1164; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma165; RV64-BITS-UNKNOWN-NEXT: vid.v v9166; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0167; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma168; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9169; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 0170; RV64-BITS-UNKNOWN-NEXT: ret171;172; RV64-BITS-256-LABEL: reverse_nxv4i1:173; RV64-BITS-256: # %bb.0:174; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma175; RV64-BITS-256-NEXT: vmv.v.i v8, 0176; RV64-BITS-256-NEXT: csrr a0, vlenb177; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0178; RV64-BITS-256-NEXT: srli a0, a0, 1179; RV64-BITS-256-NEXT: addi a0, a0, -1180; RV64-BITS-256-NEXT: vid.v v9181; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0182; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9183; RV64-BITS-256-NEXT: vmsne.vi v0, v10, 0184; RV64-BITS-256-NEXT: ret185;186; RV64-BITS-512-LABEL: reverse_nxv4i1:187; RV64-BITS-512: # %bb.0:188; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma189; RV64-BITS-512-NEXT: vmv.v.i v8, 0190; RV64-BITS-512-NEXT: csrr a0, vlenb191; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0192; RV64-BITS-512-NEXT: srli a0, a0, 1193; RV64-BITS-512-NEXT: addi a0, a0, -1194; RV64-BITS-512-NEXT: vid.v v9195; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0196; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9197; RV64-BITS-512-NEXT: vmsne.vi v0, v10, 0198; RV64-BITS-512-NEXT: ret199 %res = call <vscale x 4 x i1> @llvm.vector.reverse.nxv4i1(<vscale x 4 x i1> %a)200 ret <vscale x 4 x i1> %res201}202 203define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) {204; RV32-BITS-UNKNOWN-LABEL: reverse_nxv8i1:205; RV32-BITS-UNKNOWN: # %bb.0:206; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma207; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0208; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb209; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v10, v8, 1, v0210; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1211; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m2, ta, ma212; RV32-BITS-UNKNOWN-NEXT: vid.v v8213; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0214; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma215; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v10, v8216; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v11, 0217; RV32-BITS-UNKNOWN-NEXT: ret218;219; RV32-BITS-256-LABEL: reverse_nxv8i1:220; RV32-BITS-256: # %bb.0:221; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma222; RV32-BITS-256-NEXT: vmv.v.i v8, 0223; RV32-BITS-256-NEXT: csrr a0, vlenb224; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0225; RV32-BITS-256-NEXT: addi a0, a0, -1226; RV32-BITS-256-NEXT: vid.v v9227; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0228; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9229; RV32-BITS-256-NEXT: vmsne.vi v0, v10, 0230; RV32-BITS-256-NEXT: ret231;232; RV32-BITS-512-LABEL: reverse_nxv8i1:233; RV32-BITS-512: # %bb.0:234; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma235; RV32-BITS-512-NEXT: vmv.v.i v8, 0236; RV32-BITS-512-NEXT: csrr a0, vlenb237; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0238; RV32-BITS-512-NEXT: addi a0, a0, -1239; RV32-BITS-512-NEXT: vid.v v9240; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0241; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9242; RV32-BITS-512-NEXT: vmsne.vi v0, v10, 0243; RV32-BITS-512-NEXT: ret244;245; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i1:246; RV64-BITS-UNKNOWN: # %bb.0:247; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma248; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0249; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb250; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v10, v8, 1, v0251; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1252; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m2, ta, ma253; RV64-BITS-UNKNOWN-NEXT: vid.v v8254; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0255; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma256; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v10, v8257; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v11, 0258; RV64-BITS-UNKNOWN-NEXT: ret259;260; RV64-BITS-256-LABEL: reverse_nxv8i1:261; RV64-BITS-256: # %bb.0:262; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma263; RV64-BITS-256-NEXT: vmv.v.i v8, 0264; RV64-BITS-256-NEXT: csrr a0, vlenb265; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0266; RV64-BITS-256-NEXT: addi a0, a0, -1267; RV64-BITS-256-NEXT: vid.v v9268; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0269; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9270; RV64-BITS-256-NEXT: vmsne.vi v0, v10, 0271; RV64-BITS-256-NEXT: ret272;273; RV64-BITS-512-LABEL: reverse_nxv8i1:274; RV64-BITS-512: # %bb.0:275; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma276; RV64-BITS-512-NEXT: vmv.v.i v8, 0277; RV64-BITS-512-NEXT: csrr a0, vlenb278; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0279; RV64-BITS-512-NEXT: addi a0, a0, -1280; RV64-BITS-512-NEXT: vid.v v9281; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0282; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9283; RV64-BITS-512-NEXT: vmsne.vi v0, v10, 0284; RV64-BITS-512-NEXT: ret285 %res = call <vscale x 8 x i1> @llvm.vector.reverse.nxv8i1(<vscale x 8 x i1> %a)286 ret <vscale x 8 x i1> %res287}288 289define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {290; RV32-BITS-UNKNOWN-LABEL: reverse_nxv16i1:291; RV32-BITS-UNKNOWN: # %bb.0:292; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb293; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma294; RV32-BITS-UNKNOWN-NEXT: vid.v v8295; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m2, ta, ma296; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v10, 0297; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1298; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma299; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0300; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma301; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v10, v10, 1, v0302; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma303; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v8304; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v8305; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma306; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v12, 0307; RV32-BITS-UNKNOWN-NEXT: ret308;309; RV32-BITS-256-LABEL: reverse_nxv16i1:310; RV32-BITS-256: # %bb.0:311; RV32-BITS-256-NEXT: csrr a0, vlenb312; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma313; RV32-BITS-256-NEXT: vid.v v10314; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, ma315; RV32-BITS-256-NEXT: vmv.v.i v8, 0316; RV32-BITS-256-NEXT: addi a0, a0, -1317; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma318; RV32-BITS-256-NEXT: vrsub.vx v12, v10, a0319; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma320; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0321; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma322; RV32-BITS-256-NEXT: vrgather.vv v11, v8, v12323; RV32-BITS-256-NEXT: vrgather.vv v10, v9, v12324; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma325; RV32-BITS-256-NEXT: vmsne.vi v0, v10, 0326; RV32-BITS-256-NEXT: ret327;328; RV32-BITS-512-LABEL: reverse_nxv16i1:329; RV32-BITS-512: # %bb.0:330; RV32-BITS-512-NEXT: csrr a0, vlenb331; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma332; RV32-BITS-512-NEXT: vid.v v10333; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, ma334; RV32-BITS-512-NEXT: vmv.v.i v8, 0335; RV32-BITS-512-NEXT: addi a0, a0, -1336; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma337; RV32-BITS-512-NEXT: vrsub.vx v12, v10, a0338; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma339; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0340; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma341; RV32-BITS-512-NEXT: vrgather.vv v11, v8, v12342; RV32-BITS-512-NEXT: vrgather.vv v10, v9, v12343; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma344; RV32-BITS-512-NEXT: vmsne.vi v0, v10, 0345; RV32-BITS-512-NEXT: ret346;347; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i1:348; RV64-BITS-UNKNOWN: # %bb.0:349; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb350; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma351; RV64-BITS-UNKNOWN-NEXT: vid.v v8352; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m2, ta, ma353; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v10, 0354; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1355; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma356; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0357; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma358; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v10, v10, 1, v0359; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma360; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v8361; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v8362; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma363; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v12, 0364; RV64-BITS-UNKNOWN-NEXT: ret365;366; RV64-BITS-256-LABEL: reverse_nxv16i1:367; RV64-BITS-256: # %bb.0:368; RV64-BITS-256-NEXT: csrr a0, vlenb369; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma370; RV64-BITS-256-NEXT: vid.v v10371; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, ma372; RV64-BITS-256-NEXT: vmv.v.i v8, 0373; RV64-BITS-256-NEXT: addi a0, a0, -1374; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma375; RV64-BITS-256-NEXT: vrsub.vx v12, v10, a0376; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma377; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0378; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma379; RV64-BITS-256-NEXT: vrgather.vv v11, v8, v12380; RV64-BITS-256-NEXT: vrgather.vv v10, v9, v12381; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma382; RV64-BITS-256-NEXT: vmsne.vi v0, v10, 0383; RV64-BITS-256-NEXT: ret384;385; RV64-BITS-512-LABEL: reverse_nxv16i1:386; RV64-BITS-512: # %bb.0:387; RV64-BITS-512-NEXT: csrr a0, vlenb388; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma389; RV64-BITS-512-NEXT: vid.v v10390; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, ma391; RV64-BITS-512-NEXT: vmv.v.i v8, 0392; RV64-BITS-512-NEXT: addi a0, a0, -1393; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma394; RV64-BITS-512-NEXT: vrsub.vx v12, v10, a0395; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma396; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0397; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma398; RV64-BITS-512-NEXT: vrgather.vv v11, v8, v12399; RV64-BITS-512-NEXT: vrgather.vv v10, v9, v12400; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma401; RV64-BITS-512-NEXT: vmsne.vi v0, v10, 0402; RV64-BITS-512-NEXT: ret403 %res = call <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1> %a)404 ret <vscale x 16 x i1> %res405}406 407define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {408; RV32-BITS-UNKNOWN-LABEL: reverse_nxv32i1:409; RV32-BITS-UNKNOWN: # %bb.0:410; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb411; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma412; RV32-BITS-UNKNOWN-NEXT: vid.v v12413; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m4, ta, ma414; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0415; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1416; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma417; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v12, a0418; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma419; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0420; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma421; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v8, v16422; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v9, v16423; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v16424; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v16425; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma426; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v12, 0427; RV32-BITS-UNKNOWN-NEXT: ret428;429; RV32-BITS-256-LABEL: reverse_nxv32i1:430; RV32-BITS-256: # %bb.0:431; RV32-BITS-256-NEXT: csrr a0, vlenb432; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma433; RV32-BITS-256-NEXT: vid.v v12434; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, ma435; RV32-BITS-256-NEXT: vmv.v.i v8, 0436; RV32-BITS-256-NEXT: addi a0, a0, -1437; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma438; RV32-BITS-256-NEXT: vrsub.vx v16, v12, a0439; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma440; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0441; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma442; RV32-BITS-256-NEXT: vrgather.vv v15, v8, v16443; RV32-BITS-256-NEXT: vrgather.vv v14, v9, v16444; RV32-BITS-256-NEXT: vrgather.vv v13, v10, v16445; RV32-BITS-256-NEXT: vrgather.vv v12, v11, v16446; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma447; RV32-BITS-256-NEXT: vmsne.vi v0, v12, 0448; RV32-BITS-256-NEXT: ret449;450; RV32-BITS-512-LABEL: reverse_nxv32i1:451; RV32-BITS-512: # %bb.0:452; RV32-BITS-512-NEXT: csrr a0, vlenb453; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma454; RV32-BITS-512-NEXT: vid.v v12455; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma456; RV32-BITS-512-NEXT: vmv.v.i v8, 0457; RV32-BITS-512-NEXT: addi a0, a0, -1458; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma459; RV32-BITS-512-NEXT: vrsub.vx v16, v12, a0460; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma461; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0462; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma463; RV32-BITS-512-NEXT: vrgather.vv v15, v8, v16464; RV32-BITS-512-NEXT: vrgather.vv v14, v9, v16465; RV32-BITS-512-NEXT: vrgather.vv v13, v10, v16466; RV32-BITS-512-NEXT: vrgather.vv v12, v11, v16467; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma468; RV32-BITS-512-NEXT: vmsne.vi v0, v12, 0469; RV32-BITS-512-NEXT: ret470;471; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i1:472; RV64-BITS-UNKNOWN: # %bb.0:473; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb474; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma475; RV64-BITS-UNKNOWN-NEXT: vid.v v12476; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m4, ta, ma477; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0478; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1479; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma480; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v12, a0481; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma482; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0483; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma484; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v8, v16485; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v9, v16486; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v16487; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v16488; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma489; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v12, 0490; RV64-BITS-UNKNOWN-NEXT: ret491;492; RV64-BITS-256-LABEL: reverse_nxv32i1:493; RV64-BITS-256: # %bb.0:494; RV64-BITS-256-NEXT: csrr a0, vlenb495; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma496; RV64-BITS-256-NEXT: vid.v v12497; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, ma498; RV64-BITS-256-NEXT: vmv.v.i v8, 0499; RV64-BITS-256-NEXT: addi a0, a0, -1500; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma501; RV64-BITS-256-NEXT: vrsub.vx v16, v12, a0502; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma503; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0504; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma505; RV64-BITS-256-NEXT: vrgather.vv v15, v8, v16506; RV64-BITS-256-NEXT: vrgather.vv v14, v9, v16507; RV64-BITS-256-NEXT: vrgather.vv v13, v10, v16508; RV64-BITS-256-NEXT: vrgather.vv v12, v11, v16509; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma510; RV64-BITS-256-NEXT: vmsne.vi v0, v12, 0511; RV64-BITS-256-NEXT: ret512;513; RV64-BITS-512-LABEL: reverse_nxv32i1:514; RV64-BITS-512: # %bb.0:515; RV64-BITS-512-NEXT: csrr a0, vlenb516; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma517; RV64-BITS-512-NEXT: vid.v v12518; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma519; RV64-BITS-512-NEXT: vmv.v.i v8, 0520; RV64-BITS-512-NEXT: addi a0, a0, -1521; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma522; RV64-BITS-512-NEXT: vrsub.vx v16, v12, a0523; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma524; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0525; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma526; RV64-BITS-512-NEXT: vrgather.vv v15, v8, v16527; RV64-BITS-512-NEXT: vrgather.vv v14, v9, v16528; RV64-BITS-512-NEXT: vrgather.vv v13, v10, v16529; RV64-BITS-512-NEXT: vrgather.vv v12, v11, v16530; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma531; RV64-BITS-512-NEXT: vmsne.vi v0, v12, 0532; RV64-BITS-512-NEXT: ret533 %res = call <vscale x 32 x i1> @llvm.vector.reverse.nxv32i1(<vscale x 32 x i1> %a)534 ret <vscale x 32 x i1> %res535}536 537define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {538; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i1:539; RV32-BITS-UNKNOWN: # %bb.0:540; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb541; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma542; RV32-BITS-UNKNOWN-NEXT: vid.v v16543; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m8, ta, ma544; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0545; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1546; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma547; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v24, v16, a0548; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma549; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v16, v8, 1, v0550; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma551; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v16, v24552; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v17, v24553; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v18, v24554; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v19, v24555; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v20, v24556; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v21, v24557; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v22, v24558; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v23, v24559; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma560; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0561; RV32-BITS-UNKNOWN-NEXT: ret562;563; RV32-BITS-256-LABEL: reverse_nxv64i1:564; RV32-BITS-256: # %bb.0:565; RV32-BITS-256-NEXT: csrr a0, vlenb566; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma567; RV32-BITS-256-NEXT: vid.v v16568; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m8, ta, ma569; RV32-BITS-256-NEXT: vmv.v.i v8, 0570; RV32-BITS-256-NEXT: addi a0, a0, -1571; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma572; RV32-BITS-256-NEXT: vrsub.vx v24, v16, a0573; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma574; RV32-BITS-256-NEXT: vmerge.vim v16, v8, 1, v0575; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma576; RV32-BITS-256-NEXT: vrgather.vv v15, v16, v24577; RV32-BITS-256-NEXT: vrgather.vv v14, v17, v24578; RV32-BITS-256-NEXT: vrgather.vv v13, v18, v24579; RV32-BITS-256-NEXT: vrgather.vv v12, v19, v24580; RV32-BITS-256-NEXT: vrgather.vv v11, v20, v24581; RV32-BITS-256-NEXT: vrgather.vv v10, v21, v24582; RV32-BITS-256-NEXT: vrgather.vv v9, v22, v24583; RV32-BITS-256-NEXT: vrgather.vv v8, v23, v24584; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma585; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0586; RV32-BITS-256-NEXT: ret587;588; RV32-BITS-512-LABEL: reverse_nxv64i1:589; RV32-BITS-512: # %bb.0:590; RV32-BITS-512-NEXT: csrr a0, vlenb591; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma592; RV32-BITS-512-NEXT: vid.v v16593; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m8, ta, ma594; RV32-BITS-512-NEXT: vmv.v.i v8, 0595; RV32-BITS-512-NEXT: addi a0, a0, -1596; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma597; RV32-BITS-512-NEXT: vrsub.vx v24, v16, a0598; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma599; RV32-BITS-512-NEXT: vmerge.vim v16, v8, 1, v0600; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma601; RV32-BITS-512-NEXT: vrgather.vv v15, v16, v24602; RV32-BITS-512-NEXT: vrgather.vv v14, v17, v24603; RV32-BITS-512-NEXT: vrgather.vv v13, v18, v24604; RV32-BITS-512-NEXT: vrgather.vv v12, v19, v24605; RV32-BITS-512-NEXT: vrgather.vv v11, v20, v24606; RV32-BITS-512-NEXT: vrgather.vv v10, v21, v24607; RV32-BITS-512-NEXT: vrgather.vv v9, v22, v24608; RV32-BITS-512-NEXT: vrgather.vv v8, v23, v24609; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma610; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0611; RV32-BITS-512-NEXT: ret612;613; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i1:614; RV64-BITS-UNKNOWN: # %bb.0:615; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb616; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma617; RV64-BITS-UNKNOWN-NEXT: vid.v v16618; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m8, ta, ma619; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0620; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1621; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma622; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v24, v16, a0623; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma624; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v16, v8, 1, v0625; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma626; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v16, v24627; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v17, v24628; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v18, v24629; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v19, v24630; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v20, v24631; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v21, v24632; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v22, v24633; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v23, v24634; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma635; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0636; RV64-BITS-UNKNOWN-NEXT: ret637;638; RV64-BITS-256-LABEL: reverse_nxv64i1:639; RV64-BITS-256: # %bb.0:640; RV64-BITS-256-NEXT: csrr a0, vlenb641; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma642; RV64-BITS-256-NEXT: vid.v v16643; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m8, ta, ma644; RV64-BITS-256-NEXT: vmv.v.i v8, 0645; RV64-BITS-256-NEXT: addi a0, a0, -1646; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma647; RV64-BITS-256-NEXT: vrsub.vx v24, v16, a0648; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma649; RV64-BITS-256-NEXT: vmerge.vim v16, v8, 1, v0650; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma651; RV64-BITS-256-NEXT: vrgather.vv v15, v16, v24652; RV64-BITS-256-NEXT: vrgather.vv v14, v17, v24653; RV64-BITS-256-NEXT: vrgather.vv v13, v18, v24654; RV64-BITS-256-NEXT: vrgather.vv v12, v19, v24655; RV64-BITS-256-NEXT: vrgather.vv v11, v20, v24656; RV64-BITS-256-NEXT: vrgather.vv v10, v21, v24657; RV64-BITS-256-NEXT: vrgather.vv v9, v22, v24658; RV64-BITS-256-NEXT: vrgather.vv v8, v23, v24659; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma660; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0661; RV64-BITS-256-NEXT: ret662;663; RV64-BITS-512-LABEL: reverse_nxv64i1:664; RV64-BITS-512: # %bb.0:665; RV64-BITS-512-NEXT: csrr a0, vlenb666; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma667; RV64-BITS-512-NEXT: vid.v v16668; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m8, ta, ma669; RV64-BITS-512-NEXT: vmv.v.i v8, 0670; RV64-BITS-512-NEXT: addi a0, a0, -1671; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma672; RV64-BITS-512-NEXT: vrsub.vx v24, v16, a0673; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma674; RV64-BITS-512-NEXT: vmerge.vim v16, v8, 1, v0675; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma676; RV64-BITS-512-NEXT: vrgather.vv v15, v16, v24677; RV64-BITS-512-NEXT: vrgather.vv v14, v17, v24678; RV64-BITS-512-NEXT: vrgather.vv v13, v18, v24679; RV64-BITS-512-NEXT: vrgather.vv v12, v19, v24680; RV64-BITS-512-NEXT: vrgather.vv v11, v20, v24681; RV64-BITS-512-NEXT: vrgather.vv v10, v21, v24682; RV64-BITS-512-NEXT: vrgather.vv v9, v22, v24683; RV64-BITS-512-NEXT: vrgather.vv v8, v23, v24684; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma685; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0686; RV64-BITS-512-NEXT: ret687 %res = call <vscale x 64 x i1> @llvm.vector.reverse.nxv64i1(<vscale x 64 x i1> %a)688 ret <vscale x 64 x i1> %res689}690 691;692; VECTOR_REVERSE - integer693;694 695define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {696; RV32-BITS-UNKNOWN-LABEL: reverse_nxv1i8:697; RV32-BITS-UNKNOWN: # %bb.0:698; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb699; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 3700; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1701; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma702; RV32-BITS-UNKNOWN-NEXT: vid.v v9703; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0704; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma705; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10706; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9707; RV32-BITS-UNKNOWN-NEXT: ret708;709; RV32-BITS-256-LABEL: reverse_nxv1i8:710; RV32-BITS-256: # %bb.0:711; RV32-BITS-256-NEXT: csrr a0, vlenb712; RV32-BITS-256-NEXT: srli a0, a0, 3713; RV32-BITS-256-NEXT: addi a0, a0, -1714; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, ma715; RV32-BITS-256-NEXT: vid.v v9716; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0717; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10718; RV32-BITS-256-NEXT: vmv1r.v v8, v9719; RV32-BITS-256-NEXT: ret720;721; RV32-BITS-512-LABEL: reverse_nxv1i8:722; RV32-BITS-512: # %bb.0:723; RV32-BITS-512-NEXT: csrr a0, vlenb724; RV32-BITS-512-NEXT: srli a0, a0, 3725; RV32-BITS-512-NEXT: addi a0, a0, -1726; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, ma727; RV32-BITS-512-NEXT: vid.v v9728; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0729; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10730; RV32-BITS-512-NEXT: vmv1r.v v8, v9731; RV32-BITS-512-NEXT: ret732;733; RV64-BITS-UNKNOWN-LABEL: reverse_nxv1i8:734; RV64-BITS-UNKNOWN: # %bb.0:735; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb736; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 3737; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1738; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma739; RV64-BITS-UNKNOWN-NEXT: vid.v v9740; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0741; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma742; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10743; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9744; RV64-BITS-UNKNOWN-NEXT: ret745;746; RV64-BITS-256-LABEL: reverse_nxv1i8:747; RV64-BITS-256: # %bb.0:748; RV64-BITS-256-NEXT: csrr a0, vlenb749; RV64-BITS-256-NEXT: srli a0, a0, 3750; RV64-BITS-256-NEXT: addi a0, a0, -1751; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, ma752; RV64-BITS-256-NEXT: vid.v v9753; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0754; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10755; RV64-BITS-256-NEXT: vmv1r.v v8, v9756; RV64-BITS-256-NEXT: ret757;758; RV64-BITS-512-LABEL: reverse_nxv1i8:759; RV64-BITS-512: # %bb.0:760; RV64-BITS-512-NEXT: csrr a0, vlenb761; RV64-BITS-512-NEXT: srli a0, a0, 3762; RV64-BITS-512-NEXT: addi a0, a0, -1763; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, ma764; RV64-BITS-512-NEXT: vid.v v9765; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0766; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10767; RV64-BITS-512-NEXT: vmv1r.v v8, v9768; RV64-BITS-512-NEXT: ret769 %res = call <vscale x 1 x i8> @llvm.vector.reverse.nxv1i8(<vscale x 1 x i8> %a)770 ret <vscale x 1 x i8> %res771}772 773define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {774; RV32-BITS-UNKNOWN-LABEL: reverse_nxv2i8:775; RV32-BITS-UNKNOWN: # %bb.0:776; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb777; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2778; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1779; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma780; RV32-BITS-UNKNOWN-NEXT: vid.v v9781; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0782; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma783; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10784; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9785; RV32-BITS-UNKNOWN-NEXT: ret786;787; RV32-BITS-256-LABEL: reverse_nxv2i8:788; RV32-BITS-256: # %bb.0:789; RV32-BITS-256-NEXT: csrr a0, vlenb790; RV32-BITS-256-NEXT: srli a0, a0, 2791; RV32-BITS-256-NEXT: addi a0, a0, -1792; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, ma793; RV32-BITS-256-NEXT: vid.v v9794; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0795; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10796; RV32-BITS-256-NEXT: vmv1r.v v8, v9797; RV32-BITS-256-NEXT: ret798;799; RV32-BITS-512-LABEL: reverse_nxv2i8:800; RV32-BITS-512: # %bb.0:801; RV32-BITS-512-NEXT: csrr a0, vlenb802; RV32-BITS-512-NEXT: srli a0, a0, 2803; RV32-BITS-512-NEXT: addi a0, a0, -1804; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, ma805; RV32-BITS-512-NEXT: vid.v v9806; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0807; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10808; RV32-BITS-512-NEXT: vmv1r.v v8, v9809; RV32-BITS-512-NEXT: ret810;811; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i8:812; RV64-BITS-UNKNOWN: # %bb.0:813; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb814; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2815; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1816; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma817; RV64-BITS-UNKNOWN-NEXT: vid.v v9818; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0819; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma820; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10821; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9822; RV64-BITS-UNKNOWN-NEXT: ret823;824; RV64-BITS-256-LABEL: reverse_nxv2i8:825; RV64-BITS-256: # %bb.0:826; RV64-BITS-256-NEXT: csrr a0, vlenb827; RV64-BITS-256-NEXT: srli a0, a0, 2828; RV64-BITS-256-NEXT: addi a0, a0, -1829; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, ma830; RV64-BITS-256-NEXT: vid.v v9831; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0832; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10833; RV64-BITS-256-NEXT: vmv1r.v v8, v9834; RV64-BITS-256-NEXT: ret835;836; RV64-BITS-512-LABEL: reverse_nxv2i8:837; RV64-BITS-512: # %bb.0:838; RV64-BITS-512-NEXT: csrr a0, vlenb839; RV64-BITS-512-NEXT: srli a0, a0, 2840; RV64-BITS-512-NEXT: addi a0, a0, -1841; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, ma842; RV64-BITS-512-NEXT: vid.v v9843; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0844; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10845; RV64-BITS-512-NEXT: vmv1r.v v8, v9846; RV64-BITS-512-NEXT: ret847 %res = call <vscale x 2 x i8> @llvm.vector.reverse.nxv2i8(<vscale x 2 x i8> %a)848 ret <vscale x 2 x i8> %res849}850 851define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {852; RV32-BITS-UNKNOWN-LABEL: reverse_nxv4i8:853; RV32-BITS-UNKNOWN: # %bb.0:854; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb855; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1856; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1857; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, ma858; RV32-BITS-UNKNOWN-NEXT: vid.v v9859; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0860; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma861; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10862; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9863; RV32-BITS-UNKNOWN-NEXT: ret864;865; RV32-BITS-256-LABEL: reverse_nxv4i8:866; RV32-BITS-256: # %bb.0:867; RV32-BITS-256-NEXT: csrr a0, vlenb868; RV32-BITS-256-NEXT: srli a0, a0, 1869; RV32-BITS-256-NEXT: addi a0, a0, -1870; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, ma871; RV32-BITS-256-NEXT: vid.v v9872; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0873; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10874; RV32-BITS-256-NEXT: vmv1r.v v8, v9875; RV32-BITS-256-NEXT: ret876;877; RV32-BITS-512-LABEL: reverse_nxv4i8:878; RV32-BITS-512: # %bb.0:879; RV32-BITS-512-NEXT: csrr a0, vlenb880; RV32-BITS-512-NEXT: srli a0, a0, 1881; RV32-BITS-512-NEXT: addi a0, a0, -1882; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, ma883; RV32-BITS-512-NEXT: vid.v v9884; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0885; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10886; RV32-BITS-512-NEXT: vmv1r.v v8, v9887; RV32-BITS-512-NEXT: ret888;889; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i8:890; RV64-BITS-UNKNOWN: # %bb.0:891; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb892; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1893; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1894; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, ma895; RV64-BITS-UNKNOWN-NEXT: vid.v v9896; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0897; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma898; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10899; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9900; RV64-BITS-UNKNOWN-NEXT: ret901;902; RV64-BITS-256-LABEL: reverse_nxv4i8:903; RV64-BITS-256: # %bb.0:904; RV64-BITS-256-NEXT: csrr a0, vlenb905; RV64-BITS-256-NEXT: srli a0, a0, 1906; RV64-BITS-256-NEXT: addi a0, a0, -1907; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, ma908; RV64-BITS-256-NEXT: vid.v v9909; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0910; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10911; RV64-BITS-256-NEXT: vmv1r.v v8, v9912; RV64-BITS-256-NEXT: ret913;914; RV64-BITS-512-LABEL: reverse_nxv4i8:915; RV64-BITS-512: # %bb.0:916; RV64-BITS-512-NEXT: csrr a0, vlenb917; RV64-BITS-512-NEXT: srli a0, a0, 1918; RV64-BITS-512-NEXT: addi a0, a0, -1919; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, ma920; RV64-BITS-512-NEXT: vid.v v9921; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0922; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10923; RV64-BITS-512-NEXT: vmv1r.v v8, v9924; RV64-BITS-512-NEXT: ret925 %res = call <vscale x 4 x i8> @llvm.vector.reverse.nxv4i8(<vscale x 4 x i8> %a)926 ret <vscale x 4 x i8> %res927}928 929define <vscale x 8 x i8> @reverse_nxv8i8(<vscale x 8 x i8> %a) {930; RV32-BITS-UNKNOWN-LABEL: reverse_nxv8i8:931; RV32-BITS-UNKNOWN: # %bb.0:932; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb933; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1934; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma935; RV32-BITS-UNKNOWN-NEXT: vid.v v10936; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0937; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma938; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10939; RV32-BITS-UNKNOWN-NEXT: vmv.v.v v8, v9940; RV32-BITS-UNKNOWN-NEXT: ret941;942; RV32-BITS-256-LABEL: reverse_nxv8i8:943; RV32-BITS-256: # %bb.0:944; RV32-BITS-256-NEXT: csrr a0, vlenb945; RV32-BITS-256-NEXT: addi a0, a0, -1946; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma947; RV32-BITS-256-NEXT: vid.v v9948; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0949; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10950; RV32-BITS-256-NEXT: vmv.v.v v8, v9951; RV32-BITS-256-NEXT: ret952;953; RV32-BITS-512-LABEL: reverse_nxv8i8:954; RV32-BITS-512: # %bb.0:955; RV32-BITS-512-NEXT: csrr a0, vlenb956; RV32-BITS-512-NEXT: addi a0, a0, -1957; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma958; RV32-BITS-512-NEXT: vid.v v9959; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0960; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10961; RV32-BITS-512-NEXT: vmv.v.v v8, v9962; RV32-BITS-512-NEXT: ret963;964; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i8:965; RV64-BITS-UNKNOWN: # %bb.0:966; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb967; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1968; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma969; RV64-BITS-UNKNOWN-NEXT: vid.v v10970; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0971; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma972; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10973; RV64-BITS-UNKNOWN-NEXT: vmv.v.v v8, v9974; RV64-BITS-UNKNOWN-NEXT: ret975;976; RV64-BITS-256-LABEL: reverse_nxv8i8:977; RV64-BITS-256: # %bb.0:978; RV64-BITS-256-NEXT: csrr a0, vlenb979; RV64-BITS-256-NEXT: addi a0, a0, -1980; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma981; RV64-BITS-256-NEXT: vid.v v9982; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0983; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10984; RV64-BITS-256-NEXT: vmv.v.v v8, v9985; RV64-BITS-256-NEXT: ret986;987; RV64-BITS-512-LABEL: reverse_nxv8i8:988; RV64-BITS-512: # %bb.0:989; RV64-BITS-512-NEXT: csrr a0, vlenb990; RV64-BITS-512-NEXT: addi a0, a0, -1991; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma992; RV64-BITS-512-NEXT: vid.v v9993; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0994; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10995; RV64-BITS-512-NEXT: vmv.v.v v8, v9996; RV64-BITS-512-NEXT: ret997 %res = call <vscale x 8 x i8> @llvm.vector.reverse.nxv8i8(<vscale x 8 x i8> %a)998 ret <vscale x 8 x i8> %res999}1000 1001define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {1002; RV32-BITS-UNKNOWN-LABEL: reverse_nxv16i8:1003; RV32-BITS-UNKNOWN: # %bb.0:1004; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb1005; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -11006; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma1007; RV32-BITS-UNKNOWN-NEXT: vid.v v101008; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v10, a01009; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma1010; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v8, v121011; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v9, v121012; RV32-BITS-UNKNOWN-NEXT: vmv2r.v v8, v101013; RV32-BITS-UNKNOWN-NEXT: ret1014;1015; RV32-BITS-256-LABEL: reverse_nxv16i8:1016; RV32-BITS-256: # %bb.0:1017; RV32-BITS-256-NEXT: csrr a0, vlenb1018; RV32-BITS-256-NEXT: addi a0, a0, -11019; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma1020; RV32-BITS-256-NEXT: vid.v v101021; RV32-BITS-256-NEXT: vrsub.vx v12, v10, a01022; RV32-BITS-256-NEXT: vrgather.vv v11, v8, v121023; RV32-BITS-256-NEXT: vrgather.vv v10, v9, v121024; RV32-BITS-256-NEXT: vmv2r.v v8, v101025; RV32-BITS-256-NEXT: ret1026;1027; RV32-BITS-512-LABEL: reverse_nxv16i8:1028; RV32-BITS-512: # %bb.0:1029; RV32-BITS-512-NEXT: csrr a0, vlenb1030; RV32-BITS-512-NEXT: addi a0, a0, -11031; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma1032; RV32-BITS-512-NEXT: vid.v v101033; RV32-BITS-512-NEXT: vrsub.vx v12, v10, a01034; RV32-BITS-512-NEXT: vrgather.vv v11, v8, v121035; RV32-BITS-512-NEXT: vrgather.vv v10, v9, v121036; RV32-BITS-512-NEXT: vmv2r.v v8, v101037; RV32-BITS-512-NEXT: ret1038;1039; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i8:1040; RV64-BITS-UNKNOWN: # %bb.0:1041; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb1042; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -11043; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma1044; RV64-BITS-UNKNOWN-NEXT: vid.v v101045; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v10, a01046; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma1047; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v8, v121048; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v9, v121049; RV64-BITS-UNKNOWN-NEXT: vmv2r.v v8, v101050; RV64-BITS-UNKNOWN-NEXT: ret1051;1052; RV64-BITS-256-LABEL: reverse_nxv16i8:1053; RV64-BITS-256: # %bb.0:1054; RV64-BITS-256-NEXT: csrr a0, vlenb1055; RV64-BITS-256-NEXT: addi a0, a0, -11056; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma1057; RV64-BITS-256-NEXT: vid.v v101058; RV64-BITS-256-NEXT: vrsub.vx v12, v10, a01059; RV64-BITS-256-NEXT: vrgather.vv v11, v8, v121060; RV64-BITS-256-NEXT: vrgather.vv v10, v9, v121061; RV64-BITS-256-NEXT: vmv2r.v v8, v101062; RV64-BITS-256-NEXT: ret1063;1064; RV64-BITS-512-LABEL: reverse_nxv16i8:1065; RV64-BITS-512: # %bb.0:1066; RV64-BITS-512-NEXT: csrr a0, vlenb1067; RV64-BITS-512-NEXT: addi a0, a0, -11068; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma1069; RV64-BITS-512-NEXT: vid.v v101070; RV64-BITS-512-NEXT: vrsub.vx v12, v10, a01071; RV64-BITS-512-NEXT: vrgather.vv v11, v8, v121072; RV64-BITS-512-NEXT: vrgather.vv v10, v9, v121073; RV64-BITS-512-NEXT: vmv2r.v v8, v101074; RV64-BITS-512-NEXT: ret1075 %res = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %a)1076 ret <vscale x 16 x i8> %res1077}1078 1079define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {1080; RV32-BITS-UNKNOWN-LABEL: reverse_nxv32i8:1081; RV32-BITS-UNKNOWN: # %bb.0:1082; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb1083; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -11084; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma1085; RV32-BITS-UNKNOWN-NEXT: vid.v v121086; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v12, a01087; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma1088; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v8, v161089; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v9, v161090; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v161091; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v161092; RV32-BITS-UNKNOWN-NEXT: vmv4r.v v8, v121093; RV32-BITS-UNKNOWN-NEXT: ret1094;1095; RV32-BITS-256-LABEL: reverse_nxv32i8:1096; RV32-BITS-256: # %bb.0:1097; RV32-BITS-256-NEXT: csrr a0, vlenb1098; RV32-BITS-256-NEXT: addi a0, a0, -11099; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma1100; RV32-BITS-256-NEXT: vid.v v121101; RV32-BITS-256-NEXT: vrsub.vx v16, v12, a01102; RV32-BITS-256-NEXT: vrgather.vv v15, v8, v161103; RV32-BITS-256-NEXT: vrgather.vv v14, v9, v161104; RV32-BITS-256-NEXT: vrgather.vv v13, v10, v161105; RV32-BITS-256-NEXT: vrgather.vv v12, v11, v161106; RV32-BITS-256-NEXT: vmv4r.v v8, v121107; RV32-BITS-256-NEXT: ret1108;1109; RV32-BITS-512-LABEL: reverse_nxv32i8:1110; RV32-BITS-512: # %bb.0:1111; RV32-BITS-512-NEXT: csrr a0, vlenb1112; RV32-BITS-512-NEXT: addi a0, a0, -11113; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma1114; RV32-BITS-512-NEXT: vid.v v121115; RV32-BITS-512-NEXT: vrsub.vx v16, v12, a01116; RV32-BITS-512-NEXT: vrgather.vv v15, v8, v161117; RV32-BITS-512-NEXT: vrgather.vv v14, v9, v161118; RV32-BITS-512-NEXT: vrgather.vv v13, v10, v161119; RV32-BITS-512-NEXT: vrgather.vv v12, v11, v161120; RV32-BITS-512-NEXT: vmv4r.v v8, v121121; RV32-BITS-512-NEXT: ret1122;1123; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i8:1124; RV64-BITS-UNKNOWN: # %bb.0:1125; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb1126; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -11127; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma1128; RV64-BITS-UNKNOWN-NEXT: vid.v v121129; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v12, a01130; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma1131; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v8, v161132; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v9, v161133; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v161134; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v161135; RV64-BITS-UNKNOWN-NEXT: vmv4r.v v8, v121136; RV64-BITS-UNKNOWN-NEXT: ret1137;1138; RV64-BITS-256-LABEL: reverse_nxv32i8:1139; RV64-BITS-256: # %bb.0:1140; RV64-BITS-256-NEXT: csrr a0, vlenb1141; RV64-BITS-256-NEXT: addi a0, a0, -11142; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma1143; RV64-BITS-256-NEXT: vid.v v121144; RV64-BITS-256-NEXT: vrsub.vx v16, v12, a01145; RV64-BITS-256-NEXT: vrgather.vv v15, v8, v161146; RV64-BITS-256-NEXT: vrgather.vv v14, v9, v161147; RV64-BITS-256-NEXT: vrgather.vv v13, v10, v161148; RV64-BITS-256-NEXT: vrgather.vv v12, v11, v161149; RV64-BITS-256-NEXT: vmv4r.v v8, v121150; RV64-BITS-256-NEXT: ret1151;1152; RV64-BITS-512-LABEL: reverse_nxv32i8:1153; RV64-BITS-512: # %bb.0:1154; RV64-BITS-512-NEXT: csrr a0, vlenb1155; RV64-BITS-512-NEXT: addi a0, a0, -11156; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma1157; RV64-BITS-512-NEXT: vid.v v121158; RV64-BITS-512-NEXT: vrsub.vx v16, v12, a01159; RV64-BITS-512-NEXT: vrgather.vv v15, v8, v161160; RV64-BITS-512-NEXT: vrgather.vv v14, v9, v161161; RV64-BITS-512-NEXT: vrgather.vv v13, v10, v161162; RV64-BITS-512-NEXT: vrgather.vv v12, v11, v161163; RV64-BITS-512-NEXT: vmv4r.v v8, v121164; RV64-BITS-512-NEXT: ret1165 %res = call <vscale x 32 x i8> @llvm.vector.reverse.nxv32i8(<vscale x 32 x i8> %a)1166 ret <vscale x 32 x i8> %res1167}1168 1169define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {1170; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i8:1171; RV32-BITS-UNKNOWN: # %bb.0:1172; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m2, ta, ma1173; RV32-BITS-UNKNOWN-NEXT: vmv8r.v v16, v81174; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb1175; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -11176; RV32-BITS-UNKNOWN-NEXT: vid.v v81177; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v24, v8, a01178; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma1179; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v16, v241180; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v17, v241181; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v18, v241182; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v19, v241183; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v20, v241184; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v21, v241185; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v22, v241186; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v23, v241187; RV32-BITS-UNKNOWN-NEXT: ret1188;1189; RV32-BITS-256-LABEL: reverse_nxv64i8:1190; RV32-BITS-256: # %bb.0:1191; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma1192; RV32-BITS-256-NEXT: vmv8r.v v16, v81193; RV32-BITS-256-NEXT: csrr a0, vlenb1194; RV32-BITS-256-NEXT: addi a0, a0, -11195; RV32-BITS-256-NEXT: vid.v v81196; RV32-BITS-256-NEXT: vrsub.vx v24, v8, a01197; RV32-BITS-256-NEXT: vrgather.vv v15, v16, v241198; RV32-BITS-256-NEXT: vrgather.vv v14, v17, v241199; RV32-BITS-256-NEXT: vrgather.vv v13, v18, v241200; RV32-BITS-256-NEXT: vrgather.vv v12, v19, v241201; RV32-BITS-256-NEXT: vrgather.vv v11, v20, v241202; RV32-BITS-256-NEXT: vrgather.vv v10, v21, v241203; RV32-BITS-256-NEXT: vrgather.vv v9, v22, v241204; RV32-BITS-256-NEXT: vrgather.vv v8, v23, v241205; RV32-BITS-256-NEXT: ret1206;1207; RV32-BITS-512-LABEL: reverse_nxv64i8:1208; RV32-BITS-512: # %bb.0:1209; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma1210; RV32-BITS-512-NEXT: vmv8r.v v16, v81211; RV32-BITS-512-NEXT: csrr a0, vlenb1212; RV32-BITS-512-NEXT: addi a0, a0, -11213; RV32-BITS-512-NEXT: vid.v v81214; RV32-BITS-512-NEXT: vrsub.vx v24, v8, a01215; RV32-BITS-512-NEXT: vrgather.vv v15, v16, v241216; RV32-BITS-512-NEXT: vrgather.vv v14, v17, v241217; RV32-BITS-512-NEXT: vrgather.vv v13, v18, v241218; RV32-BITS-512-NEXT: vrgather.vv v12, v19, v241219; RV32-BITS-512-NEXT: vrgather.vv v11, v20, v241220; RV32-BITS-512-NEXT: vrgather.vv v10, v21, v241221; RV32-BITS-512-NEXT: vrgather.vv v9, v22, v241222; RV32-BITS-512-NEXT: vrgather.vv v8, v23, v241223; RV32-BITS-512-NEXT: ret1224;1225; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i8:1226; RV64-BITS-UNKNOWN: # %bb.0:1227; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m2, ta, ma1228; RV64-BITS-UNKNOWN-NEXT: vmv8r.v v16, v81229; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb1230; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -11231; RV64-BITS-UNKNOWN-NEXT: vid.v v81232; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v24, v8, a01233; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma1234; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v16, v241235; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v17, v241236; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v18, v241237; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v19, v241238; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v20, v241239; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v21, v241240; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v22, v241241; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v23, v241242; RV64-BITS-UNKNOWN-NEXT: ret1243;1244; RV64-BITS-256-LABEL: reverse_nxv64i8:1245; RV64-BITS-256: # %bb.0:1246; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma1247; RV64-BITS-256-NEXT: vmv8r.v v16, v81248; RV64-BITS-256-NEXT: csrr a0, vlenb1249; RV64-BITS-256-NEXT: addi a0, a0, -11250; RV64-BITS-256-NEXT: vid.v v81251; RV64-BITS-256-NEXT: vrsub.vx v24, v8, a01252; RV64-BITS-256-NEXT: vrgather.vv v15, v16, v241253; RV64-BITS-256-NEXT: vrgather.vv v14, v17, v241254; RV64-BITS-256-NEXT: vrgather.vv v13, v18, v241255; RV64-BITS-256-NEXT: vrgather.vv v12, v19, v241256; RV64-BITS-256-NEXT: vrgather.vv v11, v20, v241257; RV64-BITS-256-NEXT: vrgather.vv v10, v21, v241258; RV64-BITS-256-NEXT: vrgather.vv v9, v22, v241259; RV64-BITS-256-NEXT: vrgather.vv v8, v23, v241260; RV64-BITS-256-NEXT: ret1261;1262; RV64-BITS-512-LABEL: reverse_nxv64i8:1263; RV64-BITS-512: # %bb.0:1264; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma1265; RV64-BITS-512-NEXT: vmv8r.v v16, v81266; RV64-BITS-512-NEXT: csrr a0, vlenb1267; RV64-BITS-512-NEXT: addi a0, a0, -11268; RV64-BITS-512-NEXT: vid.v v81269; RV64-BITS-512-NEXT: vrsub.vx v24, v8, a01270; RV64-BITS-512-NEXT: vrgather.vv v15, v16, v241271; RV64-BITS-512-NEXT: vrgather.vv v14, v17, v241272; RV64-BITS-512-NEXT: vrgather.vv v13, v18, v241273; RV64-BITS-512-NEXT: vrgather.vv v12, v19, v241274; RV64-BITS-512-NEXT: vrgather.vv v11, v20, v241275; RV64-BITS-512-NEXT: vrgather.vv v10, v21, v241276; RV64-BITS-512-NEXT: vrgather.vv v9, v22, v241277; RV64-BITS-512-NEXT: vrgather.vv v8, v23, v241278; RV64-BITS-512-NEXT: ret1279 %res = call <vscale x 64 x i8> @llvm.vector.reverse.nxv64i8(<vscale x 64 x i8> %a)1280 ret <vscale x 64 x i8> %res1281}1282 1283define <vscale x 1 x i16> @reverse_nxv1i16(<vscale x 1 x i16> %a) {1284; CHECK-LABEL: reverse_nxv1i16:1285; CHECK: # %bb.0:1286; CHECK-NEXT: csrr a0, vlenb1287; CHECK-NEXT: srli a0, a0, 31288; CHECK-NEXT: addi a0, a0, -11289; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma1290; CHECK-NEXT: vid.v v91291; CHECK-NEXT: vrsub.vx v10, v9, a01292; CHECK-NEXT: vrgather.vv v9, v8, v101293; CHECK-NEXT: vmv1r.v v8, v91294; CHECK-NEXT: ret1295 %res = call <vscale x 1 x i16> @llvm.vector.reverse.nxv1i16(<vscale x 1 x i16> %a)1296 ret <vscale x 1 x i16> %res1297}1298 1299define <vscale x 2 x i16> @reverse_nxv2i16(<vscale x 2 x i16> %a) {1300; CHECK-LABEL: reverse_nxv2i16:1301; CHECK: # %bb.0:1302; CHECK-NEXT: csrr a0, vlenb1303; CHECK-NEXT: srli a0, a0, 21304; CHECK-NEXT: addi a0, a0, -11305; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma1306; CHECK-NEXT: vid.v v91307; CHECK-NEXT: vrsub.vx v10, v9, a01308; CHECK-NEXT: vrgather.vv v9, v8, v101309; CHECK-NEXT: vmv1r.v v8, v91310; CHECK-NEXT: ret1311 %res = call <vscale x 2 x i16> @llvm.vector.reverse.nxv2i16(<vscale x 2 x i16> %a)1312 ret <vscale x 2 x i16> %res1313}1314 1315define <vscale x 4 x i16> @reverse_nxv4i16(<vscale x 4 x i16> %a) {1316; CHECK-LABEL: reverse_nxv4i16:1317; CHECK: # %bb.0:1318; CHECK-NEXT: csrr a0, vlenb1319; CHECK-NEXT: srli a0, a0, 11320; CHECK-NEXT: addi a0, a0, -11321; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1322; CHECK-NEXT: vid.v v91323; CHECK-NEXT: vrsub.vx v10, v9, a01324; CHECK-NEXT: vrgather.vv v9, v8, v101325; CHECK-NEXT: vmv.v.v v8, v91326; CHECK-NEXT: ret1327 %res = call <vscale x 4 x i16> @llvm.vector.reverse.nxv4i16(<vscale x 4 x i16> %a)1328 ret <vscale x 4 x i16> %res1329}1330 1331define <vscale x 8 x i16> @reverse_nxv8i16(<vscale x 8 x i16> %a) {1332; CHECK-LABEL: reverse_nxv8i16:1333; CHECK: # %bb.0:1334; CHECK-NEXT: csrr a0, vlenb1335; CHECK-NEXT: srli a0, a0, 11336; CHECK-NEXT: addi a0, a0, -11337; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1338; CHECK-NEXT: vid.v v101339; CHECK-NEXT: vrsub.vx v12, v10, a01340; CHECK-NEXT: vrgather.vv v11, v8, v121341; CHECK-NEXT: vrgather.vv v10, v9, v121342; CHECK-NEXT: vmv2r.v v8, v101343; CHECK-NEXT: ret1344 %res = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %a)1345 ret <vscale x 8 x i16> %res1346}1347 1348define <vscale x 16 x i16> @reverse_nxv16i16(<vscale x 16 x i16> %a) {1349; CHECK-LABEL: reverse_nxv16i16:1350; CHECK: # %bb.0:1351; CHECK-NEXT: csrr a0, vlenb1352; CHECK-NEXT: srli a0, a0, 11353; CHECK-NEXT: addi a0, a0, -11354; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1355; CHECK-NEXT: vid.v v121356; CHECK-NEXT: vrsub.vx v16, v12, a01357; CHECK-NEXT: vrgather.vv v15, v8, v161358; CHECK-NEXT: vrgather.vv v14, v9, v161359; CHECK-NEXT: vrgather.vv v13, v10, v161360; CHECK-NEXT: vrgather.vv v12, v11, v161361; CHECK-NEXT: vmv4r.v v8, v121362; CHECK-NEXT: ret1363 %res = call <vscale x 16 x i16> @llvm.vector.reverse.nxv16i16(<vscale x 16 x i16> %a)1364 ret <vscale x 16 x i16> %res1365}1366 1367define <vscale x 32 x i16> @reverse_nxv32i16(<vscale x 32 x i16> %a) {1368; CHECK-LABEL: reverse_nxv32i16:1369; CHECK: # %bb.0:1370; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma1371; CHECK-NEXT: vmv8r.v v16, v81372; CHECK-NEXT: csrr a0, vlenb1373; CHECK-NEXT: srli a0, a0, 11374; CHECK-NEXT: addi a0, a0, -11375; CHECK-NEXT: vid.v v81376; CHECK-NEXT: vrsub.vx v24, v8, a01377; CHECK-NEXT: vrgather.vv v15, v16, v241378; CHECK-NEXT: vrgather.vv v14, v17, v241379; CHECK-NEXT: vrgather.vv v13, v18, v241380; CHECK-NEXT: vrgather.vv v12, v19, v241381; CHECK-NEXT: vrgather.vv v11, v20, v241382; CHECK-NEXT: vrgather.vv v10, v21, v241383; CHECK-NEXT: vrgather.vv v9, v22, v241384; CHECK-NEXT: vrgather.vv v8, v23, v241385; CHECK-NEXT: ret1386 %res = call <vscale x 32 x i16> @llvm.vector.reverse.nxv32i16(<vscale x 32 x i16> %a)1387 ret <vscale x 32 x i16> %res1388}1389 1390define <vscale x 1 x i32> @reverse_nxv1i32(<vscale x 1 x i32> %a) {1391; CHECK-LABEL: reverse_nxv1i32:1392; CHECK: # %bb.0:1393; CHECK-NEXT: csrr a0, vlenb1394; CHECK-NEXT: srli a0, a0, 31395; CHECK-NEXT: addi a0, a0, -11396; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1397; CHECK-NEXT: vid.v v91398; CHECK-NEXT: vrsub.vx v10, v9, a01399; CHECK-NEXT: vrgather.vv v9, v8, v101400; CHECK-NEXT: vmv1r.v v8, v91401; CHECK-NEXT: ret1402 %res = call <vscale x 1 x i32> @llvm.vector.reverse.nxv1i32(<vscale x 1 x i32> %a)1403 ret <vscale x 1 x i32> %res1404}1405 1406define <vscale x 2 x i32> @reverse_nxv2i32(<vscale x 2 x i32> %a) {1407; CHECK-LABEL: reverse_nxv2i32:1408; CHECK: # %bb.0:1409; CHECK-NEXT: csrr a0, vlenb1410; CHECK-NEXT: srli a0, a0, 21411; CHECK-NEXT: addi a0, a0, -11412; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1413; CHECK-NEXT: vid.v v91414; CHECK-NEXT: vrsub.vx v10, v9, a01415; CHECK-NEXT: vrgather.vv v9, v8, v101416; CHECK-NEXT: vmv.v.v v8, v91417; CHECK-NEXT: ret1418 %res = call <vscale x 2 x i32> @llvm.vector.reverse.nxv2i32(<vscale x 2 x i32> %a)1419 ret <vscale x 2 x i32> %res1420}1421 1422define <vscale x 4 x i32> @reverse_nxv4i32(<vscale x 4 x i32> %a) {1423; CHECK-LABEL: reverse_nxv4i32:1424; CHECK: # %bb.0:1425; CHECK-NEXT: csrr a0, vlenb1426; CHECK-NEXT: srli a0, a0, 21427; CHECK-NEXT: addi a0, a0, -11428; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1429; CHECK-NEXT: vid.v v101430; CHECK-NEXT: vrsub.vx v12, v10, a01431; CHECK-NEXT: vrgather.vv v11, v8, v121432; CHECK-NEXT: vrgather.vv v10, v9, v121433; CHECK-NEXT: vmv2r.v v8, v101434; CHECK-NEXT: ret1435 %res = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)1436 ret <vscale x 4 x i32> %res1437}1438 1439define <vscale x 8 x i32> @reverse_nxv8i32(<vscale x 8 x i32> %a) {1440; CHECK-LABEL: reverse_nxv8i32:1441; CHECK: # %bb.0:1442; CHECK-NEXT: csrr a0, vlenb1443; CHECK-NEXT: srli a0, a0, 21444; CHECK-NEXT: addi a0, a0, -11445; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1446; CHECK-NEXT: vid.v v121447; CHECK-NEXT: vrsub.vx v16, v12, a01448; CHECK-NEXT: vrgather.vv v15, v8, v161449; CHECK-NEXT: vrgather.vv v14, v9, v161450; CHECK-NEXT: vrgather.vv v13, v10, v161451; CHECK-NEXT: vrgather.vv v12, v11, v161452; CHECK-NEXT: vmv4r.v v8, v121453; CHECK-NEXT: ret1454 %res = call <vscale x 8 x i32> @llvm.vector.reverse.nxv8i32(<vscale x 8 x i32> %a)1455 ret <vscale x 8 x i32> %res1456}1457 1458define <vscale x 16 x i32> @reverse_nxv16i32(<vscale x 16 x i32> %a) {1459; CHECK-LABEL: reverse_nxv16i32:1460; CHECK: # %bb.0:1461; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1462; CHECK-NEXT: vmv8r.v v16, v81463; CHECK-NEXT: csrr a0, vlenb1464; CHECK-NEXT: srli a0, a0, 21465; CHECK-NEXT: addi a0, a0, -11466; CHECK-NEXT: vid.v v81467; CHECK-NEXT: vrsub.vx v24, v8, a01468; CHECK-NEXT: vrgather.vv v15, v16, v241469; CHECK-NEXT: vrgather.vv v14, v17, v241470; CHECK-NEXT: vrgather.vv v13, v18, v241471; CHECK-NEXT: vrgather.vv v12, v19, v241472; CHECK-NEXT: vrgather.vv v11, v20, v241473; CHECK-NEXT: vrgather.vv v10, v21, v241474; CHECK-NEXT: vrgather.vv v9, v22, v241475; CHECK-NEXT: vrgather.vv v8, v23, v241476; CHECK-NEXT: ret1477 %res = call <vscale x 16 x i32> @llvm.vector.reverse.nxv16i32(<vscale x 16 x i32> %a)1478 ret <vscale x 16 x i32> %res1479}1480 1481define <vscale x 1 x i64> @reverse_nxv1i64(<vscale x 1 x i64> %a) {1482; CHECK-LABEL: reverse_nxv1i64:1483; CHECK: # %bb.0:1484; CHECK-NEXT: csrr a0, vlenb1485; CHECK-NEXT: srli a0, a0, 31486; CHECK-NEXT: addi a0, a0, -11487; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1488; CHECK-NEXT: vid.v v91489; CHECK-NEXT: vrsub.vx v10, v9, a01490; CHECK-NEXT: vrgather.vv v9, v8, v101491; CHECK-NEXT: vmv.v.v v8, v91492; CHECK-NEXT: ret1493 %res = call <vscale x 1 x i64> @llvm.vector.reverse.nxv1i64(<vscale x 1 x i64> %a)1494 ret <vscale x 1 x i64> %res1495}1496 1497define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) {1498; CHECK-LABEL: reverse_nxv2i64:1499; CHECK: # %bb.0:1500; CHECK-NEXT: csrr a0, vlenb1501; CHECK-NEXT: srli a0, a0, 31502; CHECK-NEXT: addi a0, a0, -11503; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1504; CHECK-NEXT: vid.v v101505; CHECK-NEXT: vrsub.vx v12, v10, a01506; CHECK-NEXT: vrgather.vv v11, v8, v121507; CHECK-NEXT: vrgather.vv v10, v9, v121508; CHECK-NEXT: vmv2r.v v8, v101509; CHECK-NEXT: ret1510 %res = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %a)1511 ret <vscale x 2 x i64> %res1512}1513 1514define <vscale x 4 x i64> @reverse_nxv4i64(<vscale x 4 x i64> %a) {1515; CHECK-LABEL: reverse_nxv4i64:1516; CHECK: # %bb.0:1517; CHECK-NEXT: csrr a0, vlenb1518; CHECK-NEXT: srli a0, a0, 31519; CHECK-NEXT: addi a0, a0, -11520; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1521; CHECK-NEXT: vid.v v121522; CHECK-NEXT: vrsub.vx v16, v12, a01523; CHECK-NEXT: vrgather.vv v15, v8, v161524; CHECK-NEXT: vrgather.vv v14, v9, v161525; CHECK-NEXT: vrgather.vv v13, v10, v161526; CHECK-NEXT: vrgather.vv v12, v11, v161527; CHECK-NEXT: vmv4r.v v8, v121528; CHECK-NEXT: ret1529 %res = call <vscale x 4 x i64> @llvm.vector.reverse.nxv4i64(<vscale x 4 x i64> %a)1530 ret <vscale x 4 x i64> %res1531}1532 1533define <vscale x 8 x i64> @reverse_nxv8i64(<vscale x 8 x i64> %a) {1534; CHECK-LABEL: reverse_nxv8i64:1535; CHECK: # %bb.0:1536; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma1537; CHECK-NEXT: vmv8r.v v16, v81538; CHECK-NEXT: csrr a0, vlenb1539; CHECK-NEXT: srli a0, a0, 31540; CHECK-NEXT: addi a0, a0, -11541; CHECK-NEXT: vid.v v81542; CHECK-NEXT: vrsub.vx v24, v8, a01543; CHECK-NEXT: vrgather.vv v15, v16, v241544; CHECK-NEXT: vrgather.vv v14, v17, v241545; CHECK-NEXT: vrgather.vv v13, v18, v241546; CHECK-NEXT: vrgather.vv v12, v19, v241547; CHECK-NEXT: vrgather.vv v11, v20, v241548; CHECK-NEXT: vrgather.vv v10, v21, v241549; CHECK-NEXT: vrgather.vv v9, v22, v241550; CHECK-NEXT: vrgather.vv v8, v23, v241551; CHECK-NEXT: ret1552 %res = call <vscale x 8 x i64> @llvm.vector.reverse.nxv8i64(<vscale x 8 x i64> %a)1553 ret <vscale x 8 x i64> %res1554}1555 1556;1557; VECTOR_REVERSE - floating point1558;1559 1560define <vscale x 1 x bfloat> @reverse_nxv1bf16(<vscale x 1 x bfloat> %a) {1561; CHECK-LABEL: reverse_nxv1bf16:1562; CHECK: # %bb.0:1563; CHECK-NEXT: csrr a0, vlenb1564; CHECK-NEXT: srli a0, a0, 31565; CHECK-NEXT: addi a0, a0, -11566; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma1567; CHECK-NEXT: vid.v v91568; CHECK-NEXT: vrsub.vx v10, v9, a01569; CHECK-NEXT: vrgather.vv v9, v8, v101570; CHECK-NEXT: vmv1r.v v8, v91571; CHECK-NEXT: ret1572 %res = call <vscale x 1 x bfloat> @llvm.vector.reverse.nxv1bf16(<vscale x 1 x bfloat> %a)1573 ret <vscale x 1 x bfloat> %res1574}1575 1576define <vscale x 2 x bfloat> @reverse_nxv2bf16(<vscale x 2 x bfloat> %a) {1577; CHECK-LABEL: reverse_nxv2bf16:1578; CHECK: # %bb.0:1579; CHECK-NEXT: csrr a0, vlenb1580; CHECK-NEXT: srli a0, a0, 21581; CHECK-NEXT: addi a0, a0, -11582; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma1583; CHECK-NEXT: vid.v v91584; CHECK-NEXT: vrsub.vx v10, v9, a01585; CHECK-NEXT: vrgather.vv v9, v8, v101586; CHECK-NEXT: vmv1r.v v8, v91587; CHECK-NEXT: ret1588 %res = call <vscale x 2 x bfloat> @llvm.vector.reverse.nxv2bf16(<vscale x 2 x bfloat> %a)1589 ret <vscale x 2 x bfloat> %res1590}1591 1592define <vscale x 4 x bfloat> @reverse_nxv4bf16(<vscale x 4 x bfloat> %a) {1593; CHECK-LABEL: reverse_nxv4bf16:1594; CHECK: # %bb.0:1595; CHECK-NEXT: csrr a0, vlenb1596; CHECK-NEXT: srli a0, a0, 11597; CHECK-NEXT: addi a0, a0, -11598; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1599; CHECK-NEXT: vid.v v91600; CHECK-NEXT: vrsub.vx v10, v9, a01601; CHECK-NEXT: vrgather.vv v9, v8, v101602; CHECK-NEXT: vmv.v.v v8, v91603; CHECK-NEXT: ret1604 %res = call <vscale x 4 x bfloat> @llvm.vector.reverse.nxv4bf16(<vscale x 4 x bfloat> %a)1605 ret <vscale x 4 x bfloat> %res1606}1607 1608define <vscale x 8 x bfloat> @reverse_nxv8bf16(<vscale x 8 x bfloat> %a) {1609; CHECK-LABEL: reverse_nxv8bf16:1610; CHECK: # %bb.0:1611; CHECK-NEXT: csrr a0, vlenb1612; CHECK-NEXT: srli a0, a0, 11613; CHECK-NEXT: addi a0, a0, -11614; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1615; CHECK-NEXT: vid.v v101616; CHECK-NEXT: vrsub.vx v12, v10, a01617; CHECK-NEXT: vrgather.vv v11, v8, v121618; CHECK-NEXT: vrgather.vv v10, v9, v121619; CHECK-NEXT: vmv2r.v v8, v101620; CHECK-NEXT: ret1621 %res = call <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat> %a)1622 ret <vscale x 8 x bfloat> %res1623}1624 1625define <vscale x 16 x bfloat> @reverse_nxv16bf16(<vscale x 16 x bfloat> %a) {1626; CHECK-LABEL: reverse_nxv16bf16:1627; CHECK: # %bb.0:1628; CHECK-NEXT: csrr a0, vlenb1629; CHECK-NEXT: srli a0, a0, 11630; CHECK-NEXT: addi a0, a0, -11631; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1632; CHECK-NEXT: vid.v v121633; CHECK-NEXT: vrsub.vx v16, v12, a01634; CHECK-NEXT: vrgather.vv v15, v8, v161635; CHECK-NEXT: vrgather.vv v14, v9, v161636; CHECK-NEXT: vrgather.vv v13, v10, v161637; CHECK-NEXT: vrgather.vv v12, v11, v161638; CHECK-NEXT: vmv4r.v v8, v121639; CHECK-NEXT: ret1640 %res = call <vscale x 16 x bfloat> @llvm.vector.reverse.nxv16bf16(<vscale x 16 x bfloat> %a)1641 ret <vscale x 16 x bfloat> %res1642}1643 1644define <vscale x 32 x bfloat> @reverse_nxv32bf16(<vscale x 32 x bfloat> %a) {1645; CHECK-LABEL: reverse_nxv32bf16:1646; CHECK: # %bb.0:1647; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma1648; CHECK-NEXT: vmv8r.v v16, v81649; CHECK-NEXT: csrr a0, vlenb1650; CHECK-NEXT: srli a0, a0, 11651; CHECK-NEXT: addi a0, a0, -11652; CHECK-NEXT: vid.v v81653; CHECK-NEXT: vrsub.vx v24, v8, a01654; CHECK-NEXT: vrgather.vv v15, v16, v241655; CHECK-NEXT: vrgather.vv v14, v17, v241656; CHECK-NEXT: vrgather.vv v13, v18, v241657; CHECK-NEXT: vrgather.vv v12, v19, v241658; CHECK-NEXT: vrgather.vv v11, v20, v241659; CHECK-NEXT: vrgather.vv v10, v21, v241660; CHECK-NEXT: vrgather.vv v9, v22, v241661; CHECK-NEXT: vrgather.vv v8, v23, v241662; CHECK-NEXT: ret1663 %res = call <vscale x 32 x bfloat> @llvm.vector.reverse.nxv32bf16(<vscale x 32 x bfloat> %a)1664 ret <vscale x 32 x bfloat> %res1665}1666 1667define <vscale x 1 x half> @reverse_nxv1f16(<vscale x 1 x half> %a) {1668; CHECK-LABEL: reverse_nxv1f16:1669; CHECK: # %bb.0:1670; CHECK-NEXT: csrr a0, vlenb1671; CHECK-NEXT: srli a0, a0, 31672; CHECK-NEXT: addi a0, a0, -11673; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma1674; CHECK-NEXT: vid.v v91675; CHECK-NEXT: vrsub.vx v10, v9, a01676; CHECK-NEXT: vrgather.vv v9, v8, v101677; CHECK-NEXT: vmv1r.v v8, v91678; CHECK-NEXT: ret1679 %res = call <vscale x 1 x half> @llvm.vector.reverse.nxv1f16(<vscale x 1 x half> %a)1680 ret <vscale x 1 x half> %res1681}1682 1683define <vscale x 2 x half> @reverse_nxv2f16(<vscale x 2 x half> %a) {1684; CHECK-LABEL: reverse_nxv2f16:1685; CHECK: # %bb.0:1686; CHECK-NEXT: csrr a0, vlenb1687; CHECK-NEXT: srli a0, a0, 21688; CHECK-NEXT: addi a0, a0, -11689; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma1690; CHECK-NEXT: vid.v v91691; CHECK-NEXT: vrsub.vx v10, v9, a01692; CHECK-NEXT: vrgather.vv v9, v8, v101693; CHECK-NEXT: vmv1r.v v8, v91694; CHECK-NEXT: ret1695 %res = call <vscale x 2 x half> @llvm.vector.reverse.nxv2f16(<vscale x 2 x half> %a)1696 ret <vscale x 2 x half> %res1697}1698 1699define <vscale x 4 x half> @reverse_nxv4f16(<vscale x 4 x half> %a) {1700; CHECK-LABEL: reverse_nxv4f16:1701; CHECK: # %bb.0:1702; CHECK-NEXT: csrr a0, vlenb1703; CHECK-NEXT: srli a0, a0, 11704; CHECK-NEXT: addi a0, a0, -11705; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1706; CHECK-NEXT: vid.v v91707; CHECK-NEXT: vrsub.vx v10, v9, a01708; CHECK-NEXT: vrgather.vv v9, v8, v101709; CHECK-NEXT: vmv.v.v v8, v91710; CHECK-NEXT: ret1711 %res = call <vscale x 4 x half> @llvm.vector.reverse.nxv4f16(<vscale x 4 x half> %a)1712 ret <vscale x 4 x half> %res1713}1714 1715define <vscale x 8 x half> @reverse_nxv8f16(<vscale x 8 x half> %a) {1716; CHECK-LABEL: reverse_nxv8f16:1717; CHECK: # %bb.0:1718; CHECK-NEXT: csrr a0, vlenb1719; CHECK-NEXT: srli a0, a0, 11720; CHECK-NEXT: addi a0, a0, -11721; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1722; CHECK-NEXT: vid.v v101723; CHECK-NEXT: vrsub.vx v12, v10, a01724; CHECK-NEXT: vrgather.vv v11, v8, v121725; CHECK-NEXT: vrgather.vv v10, v9, v121726; CHECK-NEXT: vmv2r.v v8, v101727; CHECK-NEXT: ret1728 %res = call <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half> %a)1729 ret <vscale x 8 x half> %res1730}1731 1732define <vscale x 16 x half> @reverse_nxv16f16(<vscale x 16 x half> %a) {1733; CHECK-LABEL: reverse_nxv16f16:1734; CHECK: # %bb.0:1735; CHECK-NEXT: csrr a0, vlenb1736; CHECK-NEXT: srli a0, a0, 11737; CHECK-NEXT: addi a0, a0, -11738; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1739; CHECK-NEXT: vid.v v121740; CHECK-NEXT: vrsub.vx v16, v12, a01741; CHECK-NEXT: vrgather.vv v15, v8, v161742; CHECK-NEXT: vrgather.vv v14, v9, v161743; CHECK-NEXT: vrgather.vv v13, v10, v161744; CHECK-NEXT: vrgather.vv v12, v11, v161745; CHECK-NEXT: vmv4r.v v8, v121746; CHECK-NEXT: ret1747 %res = call <vscale x 16 x half> @llvm.vector.reverse.nxv16f16(<vscale x 16 x half> %a)1748 ret <vscale x 16 x half> %res1749}1750 1751define <vscale x 32 x half> @reverse_nxv32f16(<vscale x 32 x half> %a) {1752; CHECK-LABEL: reverse_nxv32f16:1753; CHECK: # %bb.0:1754; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma1755; CHECK-NEXT: vmv8r.v v16, v81756; CHECK-NEXT: csrr a0, vlenb1757; CHECK-NEXT: srli a0, a0, 11758; CHECK-NEXT: addi a0, a0, -11759; CHECK-NEXT: vid.v v81760; CHECK-NEXT: vrsub.vx v24, v8, a01761; CHECK-NEXT: vrgather.vv v15, v16, v241762; CHECK-NEXT: vrgather.vv v14, v17, v241763; CHECK-NEXT: vrgather.vv v13, v18, v241764; CHECK-NEXT: vrgather.vv v12, v19, v241765; CHECK-NEXT: vrgather.vv v11, v20, v241766; CHECK-NEXT: vrgather.vv v10, v21, v241767; CHECK-NEXT: vrgather.vv v9, v22, v241768; CHECK-NEXT: vrgather.vv v8, v23, v241769; CHECK-NEXT: ret1770 %res = call <vscale x 32 x half> @llvm.vector.reverse.nxv32f16(<vscale x 32 x half> %a)1771 ret <vscale x 32 x half> %res1772}1773 1774define <vscale x 1 x float> @reverse_nxv1f32(<vscale x 1 x float> %a) {1775; CHECK-LABEL: reverse_nxv1f32:1776; CHECK: # %bb.0:1777; CHECK-NEXT: csrr a0, vlenb1778; CHECK-NEXT: srli a0, a0, 31779; CHECK-NEXT: addi a0, a0, -11780; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1781; CHECK-NEXT: vid.v v91782; CHECK-NEXT: vrsub.vx v10, v9, a01783; CHECK-NEXT: vrgather.vv v9, v8, v101784; CHECK-NEXT: vmv1r.v v8, v91785; CHECK-NEXT: ret1786 %res = call <vscale x 1 x float> @llvm.vector.reverse.nxv1f32(<vscale x 1 x float> %a)1787 ret <vscale x 1 x float> %res1788}1789 1790define <vscale x 2 x float> @reverse_nxv2f32(<vscale x 2 x float> %a) {1791; CHECK-LABEL: reverse_nxv2f32:1792; CHECK: # %bb.0:1793; CHECK-NEXT: csrr a0, vlenb1794; CHECK-NEXT: srli a0, a0, 21795; CHECK-NEXT: addi a0, a0, -11796; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1797; CHECK-NEXT: vid.v v91798; CHECK-NEXT: vrsub.vx v10, v9, a01799; CHECK-NEXT: vrgather.vv v9, v8, v101800; CHECK-NEXT: vmv.v.v v8, v91801; CHECK-NEXT: ret1802 %res = call <vscale x 2 x float> @llvm.vector.reverse.nxv2f32(<vscale x 2 x float> %a)1803 ret <vscale x 2 x float> %res1804}1805 1806define <vscale x 4 x float> @reverse_nxv4f32(<vscale x 4 x float> %a) {1807; CHECK-LABEL: reverse_nxv4f32:1808; CHECK: # %bb.0:1809; CHECK-NEXT: csrr a0, vlenb1810; CHECK-NEXT: srli a0, a0, 21811; CHECK-NEXT: addi a0, a0, -11812; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1813; CHECK-NEXT: vid.v v101814; CHECK-NEXT: vrsub.vx v12, v10, a01815; CHECK-NEXT: vrgather.vv v11, v8, v121816; CHECK-NEXT: vrgather.vv v10, v9, v121817; CHECK-NEXT: vmv2r.v v8, v101818; CHECK-NEXT: ret1819 %res = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %a)1820 ret <vscale x 4 x float> %res1821}1822 1823define <vscale x 8 x float> @reverse_nxv8f32(<vscale x 8 x float> %a) {1824; CHECK-LABEL: reverse_nxv8f32:1825; CHECK: # %bb.0:1826; CHECK-NEXT: csrr a0, vlenb1827; CHECK-NEXT: srli a0, a0, 21828; CHECK-NEXT: addi a0, a0, -11829; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1830; CHECK-NEXT: vid.v v121831; CHECK-NEXT: vrsub.vx v16, v12, a01832; CHECK-NEXT: vrgather.vv v15, v8, v161833; CHECK-NEXT: vrgather.vv v14, v9, v161834; CHECK-NEXT: vrgather.vv v13, v10, v161835; CHECK-NEXT: vrgather.vv v12, v11, v161836; CHECK-NEXT: vmv4r.v v8, v121837; CHECK-NEXT: ret1838 %res = call <vscale x 8 x float> @llvm.vector.reverse.nxv8f32(<vscale x 8 x float> %a)1839 ret <vscale x 8 x float> %res1840}1841 1842define <vscale x 16 x float> @reverse_nxv16f32(<vscale x 16 x float> %a) {1843; CHECK-LABEL: reverse_nxv16f32:1844; CHECK: # %bb.0:1845; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1846; CHECK-NEXT: vmv8r.v v16, v81847; CHECK-NEXT: csrr a0, vlenb1848; CHECK-NEXT: srli a0, a0, 21849; CHECK-NEXT: addi a0, a0, -11850; CHECK-NEXT: vid.v v81851; CHECK-NEXT: vrsub.vx v24, v8, a01852; CHECK-NEXT: vrgather.vv v15, v16, v241853; CHECK-NEXT: vrgather.vv v14, v17, v241854; CHECK-NEXT: vrgather.vv v13, v18, v241855; CHECK-NEXT: vrgather.vv v12, v19, v241856; CHECK-NEXT: vrgather.vv v11, v20, v241857; CHECK-NEXT: vrgather.vv v10, v21, v241858; CHECK-NEXT: vrgather.vv v9, v22, v241859; CHECK-NEXT: vrgather.vv v8, v23, v241860; CHECK-NEXT: ret1861 %res = call <vscale x 16 x float> @llvm.vector.reverse.nxv16f32(<vscale x 16 x float> %a)1862 ret <vscale x 16 x float> %res1863}1864 1865define <vscale x 1 x double> @reverse_nxv1f64(<vscale x 1 x double> %a) {1866; CHECK-LABEL: reverse_nxv1f64:1867; CHECK: # %bb.0:1868; CHECK-NEXT: csrr a0, vlenb1869; CHECK-NEXT: srli a0, a0, 31870; CHECK-NEXT: addi a0, a0, -11871; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1872; CHECK-NEXT: vid.v v91873; CHECK-NEXT: vrsub.vx v10, v9, a01874; CHECK-NEXT: vrgather.vv v9, v8, v101875; CHECK-NEXT: vmv.v.v v8, v91876; CHECK-NEXT: ret1877 %res = call <vscale x 1 x double> @llvm.vector.reverse.nxv1f64(<vscale x 1 x double> %a)1878 ret <vscale x 1 x double> %res1879}1880 1881define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) {1882; CHECK-LABEL: reverse_nxv2f64:1883; CHECK: # %bb.0:1884; CHECK-NEXT: csrr a0, vlenb1885; CHECK-NEXT: srli a0, a0, 31886; CHECK-NEXT: addi a0, a0, -11887; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1888; CHECK-NEXT: vid.v v101889; CHECK-NEXT: vrsub.vx v12, v10, a01890; CHECK-NEXT: vrgather.vv v11, v8, v121891; CHECK-NEXT: vrgather.vv v10, v9, v121892; CHECK-NEXT: vmv2r.v v8, v101893; CHECK-NEXT: ret1894 %res = call <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double> %a)1895 ret <vscale x 2 x double> %res1896}1897 1898define <vscale x 4 x double> @reverse_nxv4f64(<vscale x 4 x double> %a) {1899; CHECK-LABEL: reverse_nxv4f64:1900; CHECK: # %bb.0:1901; CHECK-NEXT: csrr a0, vlenb1902; CHECK-NEXT: srli a0, a0, 31903; CHECK-NEXT: addi a0, a0, -11904; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1905; CHECK-NEXT: vid.v v121906; CHECK-NEXT: vrsub.vx v16, v12, a01907; CHECK-NEXT: vrgather.vv v15, v8, v161908; CHECK-NEXT: vrgather.vv v14, v9, v161909; CHECK-NEXT: vrgather.vv v13, v10, v161910; CHECK-NEXT: vrgather.vv v12, v11, v161911; CHECK-NEXT: vmv4r.v v8, v121912; CHECK-NEXT: ret1913 %res = call <vscale x 4 x double> @llvm.vector.reverse.nxv4f64(<vscale x 4 x double> %a)1914 ret <vscale x 4 x double> %res1915}1916 1917define <vscale x 8 x double> @reverse_nxv8f64(<vscale x 8 x double> %a) {1918; CHECK-LABEL: reverse_nxv8f64:1919; CHECK: # %bb.0:1920; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma1921; CHECK-NEXT: vmv8r.v v16, v81922; CHECK-NEXT: csrr a0, vlenb1923; CHECK-NEXT: srli a0, a0, 31924; CHECK-NEXT: addi a0, a0, -11925; CHECK-NEXT: vid.v v81926; CHECK-NEXT: vrsub.vx v24, v8, a01927; CHECK-NEXT: vrgather.vv v15, v16, v241928; CHECK-NEXT: vrgather.vv v14, v17, v241929; CHECK-NEXT: vrgather.vv v13, v18, v241930; CHECK-NEXT: vrgather.vv v12, v19, v241931; CHECK-NEXT: vrgather.vv v11, v20, v241932; CHECK-NEXT: vrgather.vv v10, v21, v241933; CHECK-NEXT: vrgather.vv v9, v22, v241934; CHECK-NEXT: vrgather.vv v8, v23, v241935; CHECK-NEXT: ret1936 %res = call <vscale x 8 x double> @llvm.vector.reverse.nxv8f64(<vscale x 8 x double> %a)1937 ret <vscale x 8 x double> %res1938}1939 1940; Test widen reverse vector1941 1942define <vscale x 3 x i64> @reverse_nxv3i64(<vscale x 3 x i64> %a) {1943; CHECK-LABEL: reverse_nxv3i64:1944; CHECK: # %bb.0:1945; CHECK-NEXT: csrr a0, vlenb1946; CHECK-NEXT: srli a0, a0, 31947; CHECK-NEXT: addi a0, a0, -11948; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1949; CHECK-NEXT: vid.v v121950; CHECK-NEXT: vrsub.vx v14, v12, a01951; CHECK-NEXT: vrgather.vv v13, v10, v141952; CHECK-NEXT: vrgather.vv v10, v9, v141953; CHECK-NEXT: vmv.v.v v12, v131954; CHECK-NEXT: vrgather.vv v15, v8, v141955; CHECK-NEXT: vmv.v.v v13, v101956; CHECK-NEXT: vrgather.vv v8, v11, v141957; CHECK-NEXT: vmv.v.v v14, v151958; CHECK-NEXT: vmv4r.v v8, v121959; CHECK-NEXT: ret1960 %res = call <vscale x 3 x i64> @llvm.vector.reverse.nxv3i64(<vscale x 3 x i64> %a)1961 ret <vscale x 3 x i64> %res1962}1963 1964define <vscale x 6 x i64> @reverse_nxv6i64(<vscale x 6 x i64> %a) {1965; CHECK-LABEL: reverse_nxv6i64:1966; CHECK: # %bb.0:1967; CHECK-NEXT: csrr a0, vlenb1968; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1969; CHECK-NEXT: vid.v v161970; CHECK-NEXT: srli a0, a0, 31971; CHECK-NEXT: addi a0, a0, -11972; CHECK-NEXT: vrsub.vx v24, v16, a01973; CHECK-NEXT: vrgather.vv v21, v10, v241974; CHECK-NEXT: vrgather.vv v19, v12, v241975; CHECK-NEXT: vrgather.vv v18, v13, v241976; CHECK-NEXT: vrgather.vv v20, v11, v241977; CHECK-NEXT: vmv2r.v v16, v181978; CHECK-NEXT: vmv2r.v v18, v201979; CHECK-NEXT: vrgather.vv v23, v8, v241980; CHECK-NEXT: vrgather.vv v22, v9, v241981; CHECK-NEXT: vrgather.vv v9, v14, v241982; CHECK-NEXT: vrgather.vv v8, v15, v241983; CHECK-NEXT: vmv2r.v v20, v221984; CHECK-NEXT: vmv8r.v v8, v161985; CHECK-NEXT: ret1986 %res = call <vscale x 6 x i64> @llvm.vector.reverse.nxv6i64(<vscale x 6 x i64> %a)1987 ret <vscale x 6 x i64> %res1988}1989 1990define <vscale x 12 x i64> @reverse_nxv12i64(<vscale x 12 x i64> %a) {1991; RV32-LABEL: reverse_nxv12i64:1992; RV32: # %bb.0:1993; RV32-NEXT: addi sp, sp, -801994; RV32-NEXT: .cfi_def_cfa_offset 801995; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill1996; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill1997; RV32-NEXT: .cfi_offset ra, -41998; RV32-NEXT: .cfi_offset s0, -81999; RV32-NEXT: addi s0, sp, 802000; RV32-NEXT: .cfi_def_cfa s0, 02001; RV32-NEXT: csrr a0, vlenb2002; RV32-NEXT: slli a0, a0, 42003; RV32-NEXT: sub sp, sp, a02004; RV32-NEXT: andi sp, sp, -642005; RV32-NEXT: csrr a0, vlenb2006; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma2007; RV32-NEXT: vid.v v202008; RV32-NEXT: srli a1, a0, 32009; RV32-NEXT: addi a1, a1, -12010; RV32-NEXT: vrsub.vx v7, v20, a12011; RV32-NEXT: vrgather.vv v31, v12, v72012; RV32-NEXT: vrgather.vv v23, v8, v72013; RV32-NEXT: vrgather.vv v30, v13, v72014; RV32-NEXT: vrgather.vv v22, v9, v72015; RV32-NEXT: vrgather.vv v29, v14, v72016; RV32-NEXT: vrgather.vv v21, v10, v72017; RV32-NEXT: vrgather.vv v28, v15, v72018; RV32-NEXT: vrgather.vv v20, v11, v72019; RV32-NEXT: addi a1, sp, 642020; RV32-NEXT: slli a0, a0, 32021; RV32-NEXT: add a0, a1, a02022; RV32-NEXT: vrgather.vv v27, v16, v72023; RV32-NEXT: vs4r.v v20, (a0)2024; RV32-NEXT: vrgather.vv v26, v17, v72025; RV32-NEXT: vrgather.vv v25, v18, v72026; RV32-NEXT: vrgather.vv v24, v19, v72027; RV32-NEXT: vs8r.v v24, (a1)2028; RV32-NEXT: vl8re64.v v16, (a0)2029; RV32-NEXT: vl8re64.v v8, (a1)2030; RV32-NEXT: addi sp, s0, -802031; RV32-NEXT: .cfi_def_cfa sp, 802032; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload2033; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload2034; RV32-NEXT: .cfi_restore ra2035; RV32-NEXT: .cfi_restore s02036; RV32-NEXT: addi sp, sp, 802037; RV32-NEXT: .cfi_def_cfa_offset 02038; RV32-NEXT: ret2039;2040; RV64-LABEL: reverse_nxv12i64:2041; RV64: # %bb.0:2042; RV64-NEXT: addi sp, sp, -802043; RV64-NEXT: .cfi_def_cfa_offset 802044; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill2045; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill2046; RV64-NEXT: .cfi_offset ra, -82047; RV64-NEXT: .cfi_offset s0, -162048; RV64-NEXT: addi s0, sp, 802049; RV64-NEXT: .cfi_def_cfa s0, 02050; RV64-NEXT: csrr a0, vlenb2051; RV64-NEXT: slli a0, a0, 42052; RV64-NEXT: sub sp, sp, a02053; RV64-NEXT: andi sp, sp, -642054; RV64-NEXT: csrr a0, vlenb2055; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma2056; RV64-NEXT: vid.v v202057; RV64-NEXT: srli a1, a0, 32058; RV64-NEXT: addi a1, a1, -12059; RV64-NEXT: vrsub.vx v7, v20, a12060; RV64-NEXT: vrgather.vv v31, v12, v72061; RV64-NEXT: vrgather.vv v23, v8, v72062; RV64-NEXT: vrgather.vv v30, v13, v72063; RV64-NEXT: vrgather.vv v22, v9, v72064; RV64-NEXT: vrgather.vv v29, v14, v72065; RV64-NEXT: vrgather.vv v21, v10, v72066; RV64-NEXT: vrgather.vv v28, v15, v72067; RV64-NEXT: vrgather.vv v20, v11, v72068; RV64-NEXT: addi a1, sp, 642069; RV64-NEXT: slli a0, a0, 32070; RV64-NEXT: add a0, a1, a02071; RV64-NEXT: vrgather.vv v27, v16, v72072; RV64-NEXT: vs4r.v v20, (a0)2073; RV64-NEXT: vrgather.vv v26, v17, v72074; RV64-NEXT: vrgather.vv v25, v18, v72075; RV64-NEXT: vrgather.vv v24, v19, v72076; RV64-NEXT: vs8r.v v24, (a1)2077; RV64-NEXT: vl8re64.v v16, (a0)2078; RV64-NEXT: vl8re64.v v8, (a1)2079; RV64-NEXT: addi sp, s0, -802080; RV64-NEXT: .cfi_def_cfa sp, 802081; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload2082; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload2083; RV64-NEXT: .cfi_restore ra2084; RV64-NEXT: .cfi_restore s02085; RV64-NEXT: addi sp, sp, 802086; RV64-NEXT: .cfi_def_cfa_offset 02087; RV64-NEXT: ret2088 %res = call <vscale x 12 x i64> @llvm.vector.reverse.nxv12i64(<vscale x 12 x i64> %a)2089 ret <vscale x 12 x i64> %res2090}2091 2092