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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3 4define <vscale x 4 x i32> @test_vloxei(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {5; CHECK-LABEL: test_vloxei:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma8; CHECK-NEXT: vzext.vf8 v12, v89; CHECK-NEXT: vsll.vi v12, v12, 410; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma11; CHECK-NEXT: vloxei64.v v8, (a0), v1212; CHECK-NEXT: ret13entry:14 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>15 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)16 %res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(17 <vscale x 4 x i32> poison,18 ptr %ptr,19 <vscale x 4 x i64> %shl,20 i64 %vl)21 ret <vscale x 4 x i32> %res22}23 24define <vscale x 4 x i32> @test_vloxei2(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {25; CHECK-LABEL: test_vloxei2:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma28; CHECK-NEXT: vzext.vf8 v12, v829; CHECK-NEXT: vsll.vi v12, v12, 1430; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma31; CHECK-NEXT: vloxei64.v v8, (a0), v1232; CHECK-NEXT: ret33entry:34 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>35 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 14)36 %res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(37 <vscale x 4 x i32> poison,38 ptr %ptr,39 <vscale x 4 x i64> %shl,40 i64 %vl)41 ret <vscale x 4 x i32> %res42}43 44define <vscale x 4 x i32> @test_vloxei3(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {45; CHECK-LABEL: test_vloxei3:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma48; CHECK-NEXT: vzext.vf8 v12, v849; CHECK-NEXT: vsll.vi v12, v12, 2650; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma51; CHECK-NEXT: vloxei64.v v8, (a0), v1252; CHECK-NEXT: ret53entry:54 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>55 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 26)56 %res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(57 <vscale x 4 x i32> poison,58 ptr %ptr,59 <vscale x 4 x i64> %shl,60 i64 %vl)61 ret <vscale x 4 x i32> %res62}63 64; Test use vp.zext to extend.65define <vscale x 4 x i32> @test_vloxei4(ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i32 zeroext %vl) {66; CHECK-LABEL: test_vloxei4:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma69; CHECK-NEXT: vzext.vf8 v12, v8, v0.t70; CHECK-NEXT: vsll.vi v12, v12, 471; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma72; CHECK-NEXT: vloxei64.v v8, (a0), v1273; CHECK-NEXT: ret74entry:75 %offset.ext = call <vscale x 4 x i64> @llvm.vp.zext.nxvi64.nxv1i8(<vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i32 %vl)76 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)77 %vl.i64 = zext i32 %vl to i6478 %res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(79 <vscale x 4 x i32> poison,80 ptr %ptr,81 <vscale x 4 x i64> %shl,82 i64 %vl.i64)83 ret <vscale x 4 x i32> %res84}85 86; Test orignal extnened type is enough narrow.87define <vscale x 4 x i32> @test_vloxei5(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {88; CHECK-LABEL: test_vloxei5:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma91; CHECK-NEXT: vzext.vf2 v9, v892; CHECK-NEXT: vsll.vi v10, v9, 1293; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma94; CHECK-NEXT: vloxei16.v v8, (a0), v1095; CHECK-NEXT: ret96entry:97 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i16>98 %shl = shl <vscale x 4 x i16> %offset.ext, splat (i16 12)99 %res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(100 <vscale x 4 x i32> poison,101 ptr %ptr,102 <vscale x 4 x i16> %shl,103 i64 %vl)104 ret <vscale x 4 x i32> %res105}106 107define <vscale x 4 x i32> @test_vloxei6(ptr %ptr, <vscale x 4 x i7> %offset, i64 %vl) {108; CHECK-LABEL: test_vloxei6:109; CHECK: # %bb.0: # %entry110; CHECK-NEXT: li a2, 127111; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma112; CHECK-NEXT: vand.vx v12, v8, a2113; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma114; CHECK-NEXT: vzext.vf8 v8, v12115; CHECK-NEXT: vsll.vi v12, v8, 4116; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma117; CHECK-NEXT: vloxei64.v v8, (a0), v12118; CHECK-NEXT: ret119entry:120 %offset.ext = zext <vscale x 4 x i7> %offset to <vscale x 4 x i64>121 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)122 %res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(123 <vscale x 4 x i32> poison,124 ptr %ptr,125 <vscale x 4 x i64> %shl,126 i64 %vl)127 ret <vscale x 4 x i32> %res128}129 130define <vscale x 4 x i32> @test_vloxei7(ptr %ptr, <vscale x 4 x i1> %offset, i64 %vl) {131; CHECK-LABEL: test_vloxei7:132; CHECK: # %bb.0: # %entry133; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma134; CHECK-NEXT: vmv.v.i v8, 0135; CHECK-NEXT: vmerge.vim v8, v8, 1, v0136; CHECK-NEXT: vsll.vi v12, v8, 2137; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma138; CHECK-NEXT: vloxei64.v v8, (a0), v12139; CHECK-NEXT: ret140entry:141 %offset.ext = zext <vscale x 4 x i1> %offset to <vscale x 4 x i64>142 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 2)143 %res = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(144 <vscale x 4 x i32> poison,145 ptr %ptr,146 <vscale x 4 x i64> %shl,147 i64 %vl)148 ret <vscale x 4 x i32> %res149}150 151define <vscale x 4 x i32> @test_vloxei_mask(ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {152; CHECK-LABEL: test_vloxei_mask:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma155; CHECK-NEXT: vzext.vf8 v12, v8156; CHECK-NEXT: vsll.vi v12, v12, 4157; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma158; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t159; CHECK-NEXT: ret160entry:161 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>162 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)163 %res = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i64(164 <vscale x 4 x i32> poison,165 ptr %ptr,166 <vscale x 4 x i64> %shl,167 <vscale x 4 x i1> %m,168 i64 %vl, i64 1)169 ret <vscale x 4 x i32> %res170}171 172define <vscale x 4 x i32> @test_vluxei(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {173; CHECK-LABEL: test_vluxei:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma176; CHECK-NEXT: vzext.vf8 v12, v8177; CHECK-NEXT: vsll.vi v12, v12, 4178; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma179; CHECK-NEXT: vluxei64.v v8, (a0), v12180; CHECK-NEXT: ret181entry:182 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>183 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)184 %res = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64(185 <vscale x 4 x i32> poison,186 ptr %ptr,187 <vscale x 4 x i64> %shl,188 i64 %vl)189 ret <vscale x 4 x i32> %res190}191 192define <vscale x 4 x i32> @test_vluxei_mask(ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {193; CHECK-LABEL: test_vluxei_mask:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma196; CHECK-NEXT: vzext.vf8 v12, v8197; CHECK-NEXT: vsll.vi v12, v12, 4198; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma199; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t200; CHECK-NEXT: ret201entry:202 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>203 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)204 %res = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64(205 <vscale x 4 x i32> poison,206 ptr %ptr,207 <vscale x 4 x i64> %shl,208 <vscale x 4 x i1> %m,209 i64 %vl, i64 1)210 ret <vscale x 4 x i32> %res211}212 213define void @test_vsoxei(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {214; CHECK-LABEL: test_vsoxei:215; CHECK: # %bb.0: # %entry216; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma217; CHECK-NEXT: vzext.vf8 v12, v10218; CHECK-NEXT: vsll.vi v12, v12, 4219; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma220; CHECK-NEXT: vsoxei64.v v8, (a0), v12221; CHECK-NEXT: ret222entry:223 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>224 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)225 call void @llvm.riscv.vsoxei.nxv4i32.nxv4i64(226 <vscale x 4 x i32> %val,227 ptr %ptr,228 <vscale x 4 x i64> %shl,229 i64 %vl)230 ret void231}232 233define void @test_vsoxei_mask(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {234; CHECK-LABEL: test_vsoxei_mask:235; CHECK: # %bb.0: # %entry236; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma237; CHECK-NEXT: vzext.vf8 v12, v10238; CHECK-NEXT: vsll.vi v12, v12, 4239; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma240; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t241; CHECK-NEXT: ret242entry:243 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>244 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)245 call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i64(246 <vscale x 4 x i32> %val,247 ptr %ptr,248 <vscale x 4 x i64> %shl,249 <vscale x 4 x i1> %m,250 i64 %vl)251 ret void252}253 254define void @test_vsuxei(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {255; CHECK-LABEL: test_vsuxei:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma258; CHECK-NEXT: vzext.vf8 v12, v10259; CHECK-NEXT: vsll.vi v12, v12, 4260; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma261; CHECK-NEXT: vsuxei64.v v8, (a0), v12262; CHECK-NEXT: ret263entry:264 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>265 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)266 call void @llvm.riscv.vsuxei.nxv4i32.nxv4i64(267 <vscale x 4 x i32> %val,268 ptr %ptr,269 <vscale x 4 x i64> %shl,270 i64 %vl)271 ret void272}273 274define void @test_vsuxei_mask(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {275; CHECK-LABEL: test_vsuxei_mask:276; CHECK: # %bb.0: # %entry277; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma278; CHECK-NEXT: vzext.vf8 v12, v10279; CHECK-NEXT: vsll.vi v12, v12, 4280; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma281; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t282; CHECK-NEXT: ret283entry:284 %offset.ext = zext <vscale x 4 x i8> %offset to <vscale x 4 x i64>285 %shl = shl <vscale x 4 x i64> %offset.ext, splat (i64 4)286 call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i64(287 <vscale x 4 x i32> %val,288 ptr %ptr,289 <vscale x 4 x i64> %shl,290 <vscale x 4 x i1> %m,291 i64 %vl)292 ret void293}294