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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+v -o - %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -o - %s | FileCheck %s4 5define <4 x i32> @partial_reduce_add_v4i32_v4i32(<4 x i32> %accumulator, <4 x i32> %0) {6; CHECK-LABEL: partial_reduce_add_v4i32_v4i32:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma9; CHECK-NEXT: vadd.vv v8, v8, v910; CHECK-NEXT: ret11entry:12 %partial.reduce = call <4 x i32> @llvm.vector.partial.reduce.add(<4 x i32> %accumulator, <4 x i32> %0)13 ret <4 x i32> %partial.reduce14}15 16define <4 x i32> @partial_reduce_add_v4i32_v8i32(<4 x i32> %accumulator, <8 x i32> %0) {17; CHECK-LABEL: partial_reduce_add_v4i32_v8i32:18; CHECK: # %bb.0: # %entry19; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma20; CHECK-NEXT: vadd.vv v12, v8, v1021; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma22; CHECK-NEXT: vslidedown.vi v8, v10, 423; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma24; CHECK-NEXT: vadd.vv v8, v8, v1225; CHECK-NEXT: ret26entry:27 %partial.reduce = call <4 x i32> @llvm.vector.partial.reduce.add(<4 x i32> %accumulator, <8 x i32> %0)28 ret <4 x i32> %partial.reduce29}30 31define <vscale x 4 x i32> @partial_reduce_add_nvx4i32_nvx4i32(<vscale x 4 x i32> %accumulator, <vscale x 4 x i32> %0) {32; CHECK-LABEL: partial_reduce_add_nvx4i32_nvx4i32:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma35; CHECK-NEXT: vadd.vv v8, v8, v1036; CHECK-NEXT: ret37entry:38 %partial.reduce = call <vscale x 4 x i32> @llvm.vector.partial.reduce.add(<vscale x 4 x i32> %accumulator, <vscale x 4 x i32> %0)39 ret <vscale x 4 x i32> %partial.reduce40}41 42define <vscale x 4 x i32> @partial_reduce_add_nvx4i32_nvx8i32(<vscale x 4 x i32> %accumulator, <vscale x 8 x i32> %0) {43; CHECK-LABEL: partial_reduce_add_nvx4i32_nvx8i32:44; CHECK: # %bb.0: # %entry45; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma46; CHECK-NEXT: vadd.vv v8, v8, v1247; CHECK-NEXT: vadd.vv v8, v14, v848; CHECK-NEXT: ret49entry:50 %partial.reduce = call <vscale x 4 x i32> @llvm.vector.partial.reduce.add(<vscale x 4 x i32> %accumulator, <vscale x 8 x i32> %0)51 ret <vscale x 4 x i32> %partial.reduce52}53 54define <vscale x 4 x i32> @partial_reduce_add_nvx4i32_nvx16i32(<vscale x 4 x i32> %accumulator, <vscale x 16 x i32> %0) {55; CHECK-LABEL: partial_reduce_add_nvx4i32_nvx16i32:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma58; CHECK-NEXT: vadd.vv v10, v18, v2059; CHECK-NEXT: vadd.vv v8, v8, v1660; CHECK-NEXT: vadd.vv v8, v22, v861; CHECK-NEXT: vadd.vv v8, v10, v862; CHECK-NEXT: ret63entry:64 %partial.reduce = call <vscale x 4 x i32> @llvm.vector.partial.reduce.add(<vscale x 4 x i32> %accumulator, <vscale x 16 x i32> %0)65 ret <vscale x 4 x i32> %partial.reduce66}67 68define <vscale x 8 x i32> @partial_reduce_add_nvx8i32_nvx16i32(<vscale x 8 x i32> %accumulator, <vscale x 16 x i32> %0) {69; CHECK-LABEL: partial_reduce_add_nvx8i32_nvx16i32:70; CHECK: # %bb.0: # %entry71; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma72; CHECK-NEXT: vadd.vv v8, v8, v1673; CHECK-NEXT: vadd.vv v8, v20, v874; CHECK-NEXT: ret75entry:76 %partial.reduce = call <vscale x 8 x i32> @llvm.vector.partial.reduce.add(<vscale x 8 x i32> %accumulator, <vscale x 16 x i32> %0)77 ret <vscale x 8 x i32> %partial.reduce78}79 80