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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mattr=+v < %s -verify-machineinstrs | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"5target triple = "riscv64-unknown-linux-gnu"6 7define void @m(<vscale x 4 x i1> %0) {8; CHECK-LABEL: m:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu11; CHECK-NEXT: vmv.v.i v8, 012; CHECK-NEXT: vlse32.v v8, (zero), zero, v0.t13; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma14; CHECK-NEXT: vse32.v v8, (zero)15; CHECK-NEXT: ret16entry:17 %broadcast.splatinsert184 = insertelement <vscale x 4 x ptr> zeroinitializer, ptr null, i64 018 %broadcast.splat185 = shufflevector <vscale x 4 x ptr> %broadcast.splatinsert184, <vscale x 4 x ptr> zeroinitializer, <vscale x 4 x i32> zeroinitializer19 %wide.masked.gather186 = tail call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> %broadcast.splat185, i32 4, <vscale x 4 x i1> %0, <vscale x 4 x i32> zeroinitializer)20 %predphi187 = select <vscale x 4 x i1> %0, <vscale x 4 x i32> %wide.masked.gather186, <vscale x 4 x i32> zeroinitializer21 %1 = extractelement <vscale x 4 x i32> %predphi187, i32 022 store i32 %1, ptr null, align 423 ret void24}25