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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v | FileCheck %s3 4; Test for an "Invalid size request on a scalable vector". Attempts to reduce5; the test faurther were not successful. The failure requires a shuffle with 26; scalable->fixed extracts from the same vector. 0 is the only valid index for a7; scalable->fixed extract so the 2 extract must be the same. Shuffles with the8; same source are aggressively canonicalized to a unary shuffle so it requires9; the extracts to become identical through other optimizations without the10; shuffle being canonicalized before it is lowered.11 12define <2 x i32> @main(ptr %0) {13; CHECK-LABEL: main:14; CHECK: # %bb.0: # %entry15; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma16; CHECK-NEXT: vmv.v.i v8, 017; CHECK-NEXT: vse32.v v8, (zero)18; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma19; CHECK-NEXT: vmv.v.i v8, 020; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma21; CHECK-NEXT: vmv.v.i v10, 022; CHECK-NEXT: li a2, 6423; CHECK-NEXT: sw zero, 80(zero)24; CHECK-NEXT: lui a1, 725; CHECK-NEXT: lui a3, 126; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma27; CHECK-NEXT: vid.v v1128; CHECK-NEXT: li a4, 1629; CHECK-NEXT: lui a5, 230; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma31; CHECK-NEXT: vse32.v v10, (a2)32; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma33; CHECK-NEXT: vmv.v.i v10, 034; CHECK-NEXT: li a2, 2435; CHECK-NEXT: sh zero, -392(a3)36; CHECK-NEXT: sh zero, 534(a3)37; CHECK-NEXT: sh zero, 1460(a3)38; CHECK-NEXT: li a3, 3239; CHECK-NEXT: vse32.v v10, (a2)40; CHECK-NEXT: li a2, 4041; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma42; CHECK-NEXT: vse32.v v8, (a0)43; CHECK-NEXT: sh zero, -1710(a5)44; CHECK-NEXT: sh zero, -784(a5)45; CHECK-NEXT: sh zero, 142(a5)46; CHECK-NEXT: lw a5, 1244(a1)47; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma48; CHECK-NEXT: vse32.v v10, (a3)49; CHECK-NEXT: lw a3, -188(a1)50; CHECK-NEXT: sh zero, 0(a0)51; CHECK-NEXT: lw a0, -304(a1)52; CHECK-NEXT: vadd.vi v9, v11, -153; CHECK-NEXT: vse32.v v10, (a2)54; CHECK-NEXT: lw a2, -188(a1)55; CHECK-NEXT: vmv.v.x v8, a356; CHECK-NEXT: lw a3, 1244(a1)57; CHECK-NEXT: lw a1, -304(a1)58; CHECK-NEXT: vmv.v.x v10, a559; CHECK-NEXT: vmv.v.x v11, a060; CHECK-NEXT: vslide1down.vx v8, v8, zero61; CHECK-NEXT: vslide1down.vx v10, v10, zero62; CHECK-NEXT: vmin.vv v8, v10, v863; CHECK-NEXT: vmv.s.x v10, a364; CHECK-NEXT: vslide1down.vx v11, v11, zero65; CHECK-NEXT: vmin.vx v10, v10, a266; CHECK-NEXT: vmin.vx v10, v10, a167; CHECK-NEXT: vmin.vv v11, v8, v1168; CHECK-NEXT: vmv1r.v v8, v1069; CHECK-NEXT: vand.vv v9, v11, v970; CHECK-NEXT: vslideup.vi v8, v10, 171; CHECK-NEXT: vse32.v v9, (a4)72; CHECK-NEXT: sh zero, 0(zero)73; CHECK-NEXT: ret74entry:75 store <16 x i32> zeroinitializer, ptr null, align 476 store <8 x i32> zeroinitializer, ptr %0, align 477 store <4 x i32> zeroinitializer, ptr getelementptr inbounds nuw (i8, ptr null, i64 64), align 478 store i32 0, ptr getelementptr inbounds nuw (i8, ptr null, i64 80), align 479 %1 = load i32, ptr getelementptr inbounds nuw (i8, ptr null, i64 29916), align 480 %broadcast.splatinsert53 = insertelement <4 x i32> zeroinitializer, i32 %1, i64 081 %2 = load i32, ptr getelementptr inbounds nuw (i8, ptr null, i64 28484), align 482 %broadcast.splatinsert55 = insertelement <4 x i32> zeroinitializer, i32 %2, i64 083 %3 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %broadcast.splatinsert53, <4 x i32> %broadcast.splatinsert55)84 %4 = load i32, ptr getelementptr inbounds nuw (i8, ptr null, i64 28368), align 485 %broadcast.splatinsert57 = insertelement <4 x i32> zeroinitializer, i32 %4, i64 086 %5 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %3, <4 x i32> %broadcast.splatinsert57)87 store i16 0, ptr getelementptr inbounds nuw (i8, ptr null, i64 3704), align 288 store i16 0, ptr getelementptr inbounds nuw (i8, ptr null, i64 4630), align 289 %6 = shufflevector <4 x i32> %5, <4 x i32> zeroinitializer, <2 x i32> <i32 0, i32 4>90 store <2 x i32> %6, ptr getelementptr inbounds nuw (i8, ptr null, i64 16), align 491 store i16 0, ptr getelementptr inbounds nuw (i8, ptr null, i64 5556), align 292 store i16 0, ptr getelementptr inbounds nuw (i8, ptr null, i64 6482), align 293 store <2 x i32> zeroinitializer, ptr getelementptr inbounds nuw (i8, ptr null, i64 24), align 494 store i16 0, ptr getelementptr inbounds nuw (i8, ptr null, i64 7408), align 295 store i16 0, ptr getelementptr inbounds nuw (i8, ptr null, i64 8334), align 296 store <2 x i32> zeroinitializer, ptr getelementptr inbounds nuw (i8, ptr null, i64 32), align 497 store i16 0, ptr %0, align 298 store <2 x i32> zeroinitializer, ptr getelementptr inbounds nuw (i8, ptr null, i64 40), align 499 %7 = load i32, ptr getelementptr inbounds nuw (i8, ptr null, i64 29916), align 4100 %broadcast.splatinsert165 = insertelement <4 x i32> poison, i32 %7, i64 0101 %8 = load i32, ptr getelementptr inbounds nuw (i8, ptr null, i64 28484), align 4102 %broadcast.splatinsert167 = insertelement <4 x i32> poison, i32 %8, i64 0103 %9 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %broadcast.splatinsert165, <4 x i32> %broadcast.splatinsert167)104 %10 = load i32, ptr getelementptr inbounds nuw (i8, ptr null, i64 28368), align 4105 %broadcast.splatinsert169 = insertelement <4 x i32> poison, i32 %10, i64 0106 %11 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %9, <4 x i32> %broadcast.splatinsert169)107 store i16 0, ptr null, align 2108 %12 = load i32, ptr getelementptr inbounds nuw (i8, ptr null, i64 29916), align 4109 %broadcast.splatinsert179 = insertelement <4 x i32> poison, i32 %12, i64 0110 %13 = load i32, ptr getelementptr inbounds nuw (i8, ptr null, i64 28484), align 4111 %broadcast.splatinsert181 = insertelement <4 x i32> poison, i32 %13, i64 0112 %14 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %broadcast.splatinsert179, <4 x i32> %broadcast.splatinsert181)113 %15 = load i32, ptr getelementptr inbounds nuw (i8, ptr null, i64 28368), align 4114 %broadcast.splatinsert183 = insertelement <4 x i32> poison, i32 %15, i64 0115 %16 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %14, <4 x i32> %broadcast.splatinsert183)116 %17 = shufflevector <4 x i32> %11, <4 x i32> %16, <2 x i32> <i32 0, i32 4>117 ret <2 x i32> %17118}119