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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3 4define <vscale x 8 x i1> @main(<120 x i1> %0) #0 {5; CHECK-LABEL: main:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: li a0, 1288; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma9; CHECK-NEXT: vfirst.m a0, v010; CHECK-NEXT: seqz a0, a011; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma12; CHECK-NEXT: vmv.v.x v8, a013; CHECK-NEXT: vmsne.vi v0, v8, 014; CHECK-NEXT: ret15entry:16 %1 = extractelement <120 x i1> %0, i64 017 %2 = insertelement <vscale x 8 x i1> zeroinitializer, i1 %1, i64 018 %3 = shufflevector <vscale x 8 x i1> %2, <vscale x 8 x i1> zeroinitializer, <vscale x 8 x i32> zeroinitializer19 ret <vscale x 8 x i1> %320}21