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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3 4target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"5target triple = "riscv64-unknown-linux-gnu"6 7define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element3047, ptr %arrayinit.element3049, ptr %arrayinit.element3051, ptr %arrayinit.element3053, ptr %arrayinit.element3055, ptr %arrayinit.element3057, ptr %arrayinit.element3059, ptr %arrayinit.element3061, ptr %arrayinit.element3063, ptr %arrayinit.element3065, ptr %arrayinit.element3067, i64 %var_94_i.07698, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1) {8; CHECK-LABEL: main:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: addi sp, sp, -1611; CHECK-NEXT: .cfi_def_cfa_offset 1612; CHECK-NEXT: csrr t0, vlenb13; CHECK-NEXT: slli t0, t0, 314; CHECK-NEXT: mv t1, t015; CHECK-NEXT: slli t0, t0, 116; CHECK-NEXT: add t0, t0, t117; CHECK-NEXT: sub sp, sp, t018; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb19; CHECK-NEXT: sd a1, 8(sp) # 8-byte Folded Spill20; CHECK-NEXT: sd a2, 0(sp) # 8-byte Folded Spill21; CHECK-NEXT: csrr a1, vlenb22; CHECK-NEXT: slli a1, a1, 423; CHECK-NEXT: add a1, sp, a124; CHECK-NEXT: addi a1, a1, 1625; CHECK-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill26; CHECK-NEXT: csrr a2, vlenb27; CHECK-NEXT: slli a2, a2, 228; CHECK-NEXT: add a1, a1, a229; CHECK-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill30; CHECK-NEXT: csrr a1, vlenb31; CHECK-NEXT: slli a1, a1, 232; CHECK-NEXT: mv a2, a133; CHECK-NEXT: slli a1, a1, 134; CHECK-NEXT: add a1, a1, a235; CHECK-NEXT: add a1, sp, a136; CHECK-NEXT: addi a1, a1, 1637; CHECK-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill38; CHECK-NEXT: csrr a1, vlenb39; CHECK-NEXT: slli a1, a1, 340; CHECK-NEXT: mv a2, a141; CHECK-NEXT: slli a1, a1, 142; CHECK-NEXT: add a1, a1, a243; CHECK-NEXT: add a1, sp, a144; CHECK-NEXT: ld t0, 56(a1)45; CHECK-NEXT: csrr a1, vlenb46; CHECK-NEXT: slli a1, a1, 347; CHECK-NEXT: mv a2, a148; CHECK-NEXT: slli a1, a1, 149; CHECK-NEXT: add a1, a1, a250; CHECK-NEXT: add a1, sp, a151; CHECK-NEXT: ld t1, 48(a1)52; CHECK-NEXT: vsetvli t2, zero, e8, m1, ta, ma53; CHECK-NEXT: vmv.v.i v9, 054; CHECK-NEXT: csrr a1, vlenb55; CHECK-NEXT: slli a1, a1, 356; CHECK-NEXT: mv a2, a157; CHECK-NEXT: slli a1, a1, 158; CHECK-NEXT: add a1, a1, a259; CHECK-NEXT: add a1, sp, a160; CHECK-NEXT: ld t2, 40(a1)61; CHECK-NEXT: # kill: def $v10 killed $v9 killed $vtype62; CHECK-NEXT: csrr a1, vlenb63; CHECK-NEXT: slli a1, a1, 364; CHECK-NEXT: mv a2, a165; CHECK-NEXT: slli a1, a1, 166; CHECK-NEXT: add a1, a1, a267; CHECK-NEXT: add a1, sp, a168; CHECK-NEXT: ld t3, 32(a1)69; CHECK-NEXT: vmv.v.i v11, 070; CHECK-NEXT: csrr a1, vlenb71; CHECK-NEXT: slli a1, a1, 372; CHECK-NEXT: mv a2, a173; CHECK-NEXT: slli a1, a1, 174; CHECK-NEXT: add a1, a1, a275; CHECK-NEXT: add a1, sp, a176; CHECK-NEXT: ld t4, 16(a1)77; CHECK-NEXT: vmv.v.i v12, 078; CHECK-NEXT: csrr a1, vlenb79; CHECK-NEXT: slli a1, a1, 380; CHECK-NEXT: mv a2, a181; CHECK-NEXT: slli a1, a1, 182; CHECK-NEXT: add a1, a1, a283; CHECK-NEXT: add a1, sp, a184; CHECK-NEXT: ld t5, 24(a1)85; CHECK-NEXT: vmv.v.i v13, 086; CHECK-NEXT: vsetvli t6, zero, e8, m2, ta, ma87; CHECK-NEXT: vmv.v.i v22, 088; CHECK-NEXT: vmv1r.v v14, v989; CHECK-NEXT: sd zero, 0(a0)90; CHECK-NEXT: vmv.v.i v24, 091; CHECK-NEXT: vmv1r.v v15, v992; CHECK-NEXT: vmv1r.v v18, v993; CHECK-NEXT: li t6, 102394; CHECK-NEXT: vmv.v.i v26, 095; CHECK-NEXT: vmv1r.v v19, v996; CHECK-NEXT: slli t6, t6, 5297; CHECK-NEXT: vmv.v.i v28, 098; CHECK-NEXT: addi a1, sp, 1699; CHECK-NEXT: vs2r.v v22, (a1) # vscale x 16-byte Folded Spill100; CHECK-NEXT: csrr a2, vlenb101; CHECK-NEXT: slli a2, a2, 1102; CHECK-NEXT: add a1, a1, a2103; CHECK-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill104; CHECK-NEXT: slli a2, a2, 1105; CHECK-NEXT: add a1, a1, a2106; CHECK-NEXT: ld a2, 0(sp) # 8-byte Folded Reload107; CHECK-NEXT: vs2r.v v28, (a1) # vscale x 16-byte Folded Spill108; CHECK-NEXT: ld a1, 8(sp) # 8-byte Folded Reload109; CHECK-NEXT: vmv1r.v v20, v9110; CHECK-NEXT: sd t6, 0(t5)111; CHECK-NEXT: vmv2r.v v16, v14112; CHECK-NEXT: vmv2r.v v14, v12113; CHECK-NEXT: vmv2r.v v12, v10114; CHECK-NEXT: vmv1r.v v11, v9115; CHECK-NEXT: vmv1r.v v21, v9116; CHECK-NEXT: csrr t5, vlenb117; CHECK-NEXT: slli t5, t5, 3118; CHECK-NEXT: add t5, sp, t5119; CHECK-NEXT: addi t5, t5, 16120; CHECK-NEXT: vs2r.v v18, (t5) # vscale x 16-byte Folded Spill121; CHECK-NEXT: csrr t6, vlenb122; CHECK-NEXT: slli t6, t6, 1123; CHECK-NEXT: add t5, t5, t6124; CHECK-NEXT: vs2r.v v20, (t5) # vscale x 16-byte Folded Spill125; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma126; CHECK-NEXT: vmv.v.i v19, 0127; CHECK-NEXT: vmclr.m v10128; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma129; CHECK-NEXT: vmv.v.i v6, 0130; CHECK-NEXT: .LBB0_1: # %for.body131; CHECK-NEXT: # =>This Inner Loop Header: Depth=1132; CHECK-NEXT: vmv1r.v v0, v10133; CHECK-NEXT: vmv1r.v v20, v19134; CHECK-NEXT: vmv1r.v v3, v19135; CHECK-NEXT: vmv1r.v v5, v19136; CHECK-NEXT: vmv1r.v v2, v19137; CHECK-NEXT: vmv1r.v v31, v19138; CHECK-NEXT: vmv1r.v v30, v19139; CHECK-NEXT: vmv1r.v v4, v19140; CHECK-NEXT: vmv2r.v v22, v10141; CHECK-NEXT: vmv4r.v v24, v12142; CHECK-NEXT: vmv2r.v v28, v16143; CHECK-NEXT: vmv2r.v v8, v6144; CHECK-NEXT: vmv1r.v v18, v19145; CHECK-NEXT: vmv1r.v v21, v10146; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma147; CHECK-NEXT: vle32.v v20, (t4)148; CHECK-NEXT: vle32.v v3, (t1)149; CHECK-NEXT: vle32.v v30, (a7)150; CHECK-NEXT: vle64.v v8, (a4)151; CHECK-NEXT: vle32.v v5, (t2)152; CHECK-NEXT: vle32.v v2, (t3)153; CHECK-NEXT: vle32.v v31, (a6)154; CHECK-NEXT: vmv1r.v v24, v30155; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu156; CHECK-NEXT: vmflt.vv v21, v8, v6, v0.t157; CHECK-NEXT: vmv1r.v v8, v19158; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu159; CHECK-NEXT: vle32.v v18, (a2)160; CHECK-NEXT: vle32.v v8, (a3)161; CHECK-NEXT: vle32.v v4, (a5)162; CHECK-NEXT: vmv1r.v v22, v20163; CHECK-NEXT: csrr t5, vlenb164; CHECK-NEXT: slli t5, t5, 3165; CHECK-NEXT: add t5, sp, t5166; CHECK-NEXT: addi t5, t5, 16167; CHECK-NEXT: vl1r.v v1, (t5) # vscale x 8-byte Folded Reload168; CHECK-NEXT: csrr t6, vlenb169; CHECK-NEXT: add t5, t5, t6170; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload171; CHECK-NEXT: slli t6, t6, 1172; CHECK-NEXT: add t5, t5, t6173; CHECK-NEXT: vl1r.v v4, (t5) # vscale x 8-byte Folded Reload174; CHECK-NEXT: vsseg4e32.v v1, (zero)175; CHECK-NEXT: vsseg8e32.v v22, (a1)176; CHECK-NEXT: vmv1r.v v0, v21177; CHECK-NEXT: vssub.vv v8, v19, v18, v0.t178; CHECK-NEXT: csrr t5, vlenb179; CHECK-NEXT: slli t5, t5, 2180; CHECK-NEXT: mv t6, t5181; CHECK-NEXT: slli t5, t5, 1182; CHECK-NEXT: add t5, t5, t6183; CHECK-NEXT: add t5, sp, t5184; CHECK-NEXT: addi t5, t5, 16185; CHECK-NEXT: vl4r.v v20, (t5) # vscale x 32-byte Folded Reload186; CHECK-NEXT: vsetvli zero, t0, e64, m2, ta, ma187; CHECK-NEXT: vsseg2e64.v v20, (zero)188; CHECK-NEXT: vmv1r.v v0, v10189; CHECK-NEXT: addi t5, sp, 16190; CHECK-NEXT: vl4r.v v20, (t5) # vscale x 32-byte Folded Reload191; CHECK-NEXT: csrr t6, vlenb192; CHECK-NEXT: slli t6, t6, 2193; CHECK-NEXT: add t5, t5, t6194; CHECK-NEXT: vl4r.v v24, (t5) # vscale x 32-byte Folded Reload195; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma196; CHECK-NEXT: vsseg4e64.v v20, (zero), v0.t197; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma198; CHECK-NEXT: vsseg8e32.v v8, (a0)199; CHECK-NEXT: csrr t5, vlenb200; CHECK-NEXT: slli t5, t5, 4201; CHECK-NEXT: add t5, sp, t5202; CHECK-NEXT: addi t5, t5, 16203; CHECK-NEXT: vl4r.v v20, (t5) # vscale x 32-byte Folded Reload204; CHECK-NEXT: csrr t6, vlenb205; CHECK-NEXT: slli t6, t6, 2206; CHECK-NEXT: add t5, t5, t6207; CHECK-NEXT: vl4r.v v24, (t5) # vscale x 32-byte Folded Reload208; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma209; CHECK-NEXT: vsseg4e64.v v20, (zero)210; CHECK-NEXT: j .LBB0_1211entry:212 store double 0.000000e+00, ptr %var_117, align 8213 store double 1.000000e+00, ptr %arrayinit.element3061, align 8214 br label %for.body215 216for.body: ; preds = %for.body, %entry217 %2 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> zeroinitializer, ptr %arrayinit.element3059, i64 0)218 %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> zeroinitializer, ptr %arrayinit.element3067, i64 0)219 %4 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> zeroinitializer, ptr %arrayinit.element3065, i64 0)220 %5 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> zeroinitializer, ptr %arrayinit.element3063, i64 0)221 %6 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> zeroinitializer, ptr %arrayinit.element3055, i64 0)222 %7 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> zeroinitializer, ptr %arrayinit.element3057, i64 0)223 %8 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> zeroinitializer, ptr %arrayinit.element3053, i64 0)224 %9 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> zeroinitializer, ptr %arrayinit.element3051, i64 0)225 %10 = tail call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> zeroinitializer, ptr %arrayinit.element3047, i64 0)226 %11 = tail call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> zeroinitializer, ptr %arrayinit.element3049, i64 0)227 call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) zeroinitializer, ptr null, i64 0, i64 5)228 %12 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv2f32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) zeroinitializer, <vscale x 2 x float> %8, i32 0)229 %13 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv2f32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %12, <vscale x 2 x float> %7, i32 2)230 %14 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv2f32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %13, <vscale x 2 x float> %6, i32 0)231 %15 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv2f32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %14, <vscale x 2 x float> %5, i32 0)232 %16 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv2f32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %15, <vscale x 2 x float> %4, i32 0)233 %17 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv2f32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %16, <vscale x 2 x float> %3, i32 0)234 %18 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv2f32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %17, <vscale x 2 x float> %2, i32 0)235 call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %18, ptr %arrayinit.element3045, i64 0, i64 5)236 %19 = tail call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x i1> zeroinitializer, <vscale x 2 x double> zeroinitializer, <vscale x 2 x double> %9, <vscale x 2 x i1> zeroinitializer, i64 0)237 %20 = tail call <vscale x 2 x i32> @llvm.riscv.vssub.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %11, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %10, <vscale x 2 x i1> %19, i64 0, i64 0)238 call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr null, i64 %var_94_i.07698, i64 6)239 call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) zeroinitializer, ptr null, <vscale x 2 x i1> zeroinitializer, i64 0, i64 6)240 %21 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, <vscale x 2 x i32> %20, i32 0)241 call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %21, ptr %var_117, i64 0, i64 5)242 call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr null, i64 0, i64 6)243 br label %for.body244}245