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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3 4define <vscale x 4 x i8> @foo(ptr %p) {5; CHECK-LABEL: foo:6; CHECK: # %bb.0:7; CHECK-NEXT: vl1re16.v v10, (a0)8; CHECK-NEXT: lui a0, 49; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma10; CHECK-NEXT: vmv.v.x v8, a011; CHECK-NEXT: li a0, 24812; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma13; CHECK-NEXT: vsll.vi v12, v10, 314; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma15; CHECK-NEXT: vzext.vf2 v10, v1216; CHECK-NEXT: vand.vx v10, v10, a017; CHECK-NEXT: lui a0, 118; CHECK-NEXT: addi a0, a0, -36119; CHECK-NEXT: vmacc.vx v8, a0, v1020; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma21; CHECK-NEXT: vnsrl.wi v10, v8, 1522; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma23; CHECK-NEXT: vnsrl.wi v8, v10, 024; CHECK-NEXT: ret25 %i13 = load <vscale x 4 x i16>, ptr %p, align 226 %i14 = zext <vscale x 4 x i16> %i13 to <vscale x 4 x i32>27 %i15 = shl nuw nsw <vscale x 4 x i32> %i14, splat (i32 3)28 %i16 = and <vscale x 4 x i32> %i15, splat (i32 248)29 %i17 = mul nuw nsw <vscale x 4 x i32> %i16, splat (i32 3735)30 %i18 = add nuw nsw <vscale x 4 x i32> %i17, splat (i32 16384)31 %i21 = lshr <vscale x 4 x i32> %i18, splat (i32 15)32 %i22 = trunc <vscale x 4 x i32> %i21 to <vscale x 4 x i8>33 ret <vscale x 4 x i8> %i2234}35