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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=riscv64 -mattr=+v -target-abi=lp64d | FileCheck %s3 4define <4 x float> @foo(ptr %0) nounwind {5; CHECK-LABEL: foo:6; CHECK: # %bb.0:7; CHECK-NEXT: addi sp, sp, -488; CHECK-NEXT: sd ra, 40(sp) # 8-byte Folded Spill9; CHECK-NEXT: sd s0, 32(sp) # 8-byte Folded Spill10; CHECK-NEXT: sd s1, 24(sp) # 8-byte Folded Spill11; CHECK-NEXT: sd s2, 16(sp) # 8-byte Folded Spill12; CHECK-NEXT: csrr a1, vlenb13; CHECK-NEXT: slli a1, a1, 114; CHECK-NEXT: sub sp, sp, a115; CHECK-NEXT: lhu s0, 0(a0)16; CHECK-NEXT: lhu s1, 2(a0)17; CHECK-NEXT: lhu s2, 4(a0)18; CHECK-NEXT: lhu a0, 6(a0)19; CHECK-NEXT: fmv.w.x fa0, a020; CHECK-NEXT: call __extendhfsf221; CHECK-NEXT: fmv.w.x fa5, s222; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma23; CHECK-NEXT: vfmv.s.f v8, fa024; CHECK-NEXT: addi a0, sp, 1625; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill26; CHECK-NEXT: fmv.s fa0, fa527; CHECK-NEXT: call __extendhfsf228; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma29; CHECK-NEXT: vfmv.s.f v8, fa030; CHECK-NEXT: addi a0, sp, 1631; CHECK-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload32; CHECK-NEXT: vslideup.vi v8, v9, 133; CHECK-NEXT: csrr a0, vlenb34; CHECK-NEXT: add a0, sp, a035; CHECK-NEXT: addi a0, a0, 1636; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill37; CHECK-NEXT: fmv.w.x fa0, s138; CHECK-NEXT: call __extendhfsf239; CHECK-NEXT: fmv.w.x fa5, s040; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma41; CHECK-NEXT: vfmv.s.f v8, fa042; CHECK-NEXT: addi a0, sp, 1643; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill44; CHECK-NEXT: fmv.s fa0, fa545; CHECK-NEXT: call __extendhfsf246; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma47; CHECK-NEXT: vfmv.s.f v8, fa048; CHECK-NEXT: addi a0, sp, 1649; CHECK-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload50; CHECK-NEXT: vslideup.vi v8, v9, 151; CHECK-NEXT: csrr a0, vlenb52; CHECK-NEXT: add a0, sp, a053; CHECK-NEXT: addi a0, a0, 1654; CHECK-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload55; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma56; CHECK-NEXT: vslideup.vi v8, v9, 257; CHECK-NEXT: csrr a0, vlenb58; CHECK-NEXT: slli a0, a0, 159; CHECK-NEXT: add sp, sp, a060; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload61; CHECK-NEXT: ld s0, 32(sp) # 8-byte Folded Reload62; CHECK-NEXT: ld s1, 24(sp) # 8-byte Folded Reload63; CHECK-NEXT: ld s2, 16(sp) # 8-byte Folded Reload64; CHECK-NEXT: addi sp, sp, 4865; CHECK-NEXT: ret66 %2 = load <4 x half>, ptr %0, align 267 %3 = fpext <4 x half> %2 to <4 x float>68 ret <4 x float> %369}70