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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck %s3 4; This showcases a miscompile that was fixed in #83107:5; - The memset will be type-legalized to a 512 bit store + 2 x 128 bit stores.6; - the load and store of q aliases the upper 128 bits store of p.7; - The aliasing 128 bit store will be between the chain of the scalar8; load/store:9;10; t54: ch = store<(store (s512) into %ir.p, align 1)> t0, ...11; t51: ch = store<(store (s128) into %ir.p + 64, align 1)> t0, ...12;13; t44: i64,ch = load<(load (s32) from %ir.q), sext from i32> t0, ...14; t50: ch = store<(store (s128) into %ir.p + 80, align 1)> t44:1, ...15; t46: ch = store<(store (s32) into %ir.q), trunc to i32> t50, ...16;17; Previously, the scalar load/store was incorrectly combined away:18;19; t54: ch = store<(store (s512) into %ir.p, align 1)> t0, ...20; t51: ch = store<(store (s128) into %ir.p + 64, align 1)> t0, ...21;22; // MISSING23; t50: ch = store<(store (s128) into %ir.p + 80, align 1)> t44:1, ...24; // MISSING25;26; - We need to compile with an exact VLEN so that we select an ISD::STORE node27; which triggers the combine28; - The miscompile doesn't happen if we use separate GEPs as we need the stores29; to share the same MachinePointerInfo30define void @aliasing(ptr %p) {31; CHECK-LABEL: aliasing:32; CHECK: # %bb.0:33; CHECK-NEXT: lw a1, 84(a0)34; CHECK-NEXT: addi a2, a0, 8035; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma36; CHECK-NEXT: vmv.v.i v8, 037; CHECK-NEXT: vs1r.v v8, (a2)38; CHECK-NEXT: addi a2, a0, 6439; CHECK-NEXT: vs1r.v v8, (a2)40; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, ma41; CHECK-NEXT: vmv.v.i v8, 042; CHECK-NEXT: vs4r.v v8, (a0)43; CHECK-NEXT: sw a1, 84(a0)44; CHECK-NEXT: ret45 %q = getelementptr inbounds i8, ptr %p, i64 8446 %tmp = load i32, ptr %q47 tail call void @llvm.memset.p0.i64(ptr %p, i8 0, i64 96, i1 false)48 store i32 %tmp, ptr %q49 ret void50}51