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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3 4define i1 @foo(<vscale x 16 x i8> %x, i64 %y) {5; CHECK-LABEL: foo:6; CHECK: # %bb.0:7; CHECK-NEXT: csrr a1, vlenb8; CHECK-NEXT: slli a2, a1, 49; CHECK-NEXT: addi a2, a2, -110; CHECK-NEXT: bltu a0, a2, .LBB0_211; CHECK-NEXT: # %bb.1:12; CHECK-NEXT: mv a0, a213; CHECK-NEXT: .LBB0_2:14; CHECK-NEXT: addi sp, sp, -8015; CHECK-NEXT: .cfi_def_cfa_offset 8016; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill17; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill18; CHECK-NEXT: .cfi_offset ra, -819; CHECK-NEXT: .cfi_offset s0, -1620; CHECK-NEXT: addi s0, sp, 8021; CHECK-NEXT: .cfi_def_cfa s0, 022; CHECK-NEXT: csrr a2, vlenb23; CHECK-NEXT: slli a2, a2, 424; CHECK-NEXT: sub sp, sp, a225; CHECK-NEXT: andi sp, sp, -6426; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma27; CHECK-NEXT: vmv1r.v v0, v928; CHECK-NEXT: addi a2, sp, 6429; CHECK-NEXT: slli a1, a1, 330; CHECK-NEXT: vmv.v.i v16, 031; CHECK-NEXT: add a0, a2, a032; CHECK-NEXT: add a1, a2, a133; CHECK-NEXT: vmerge.vim v24, v16, 1, v034; CHECK-NEXT: vs8r.v v24, (a1)35; CHECK-NEXT: vmv1r.v v0, v836; CHECK-NEXT: vmerge.vim v8, v16, 1, v037; CHECK-NEXT: vs8r.v v8, (a2)38; CHECK-NEXT: lbu a0, 0(a0)39; CHECK-NEXT: addi sp, s0, -8040; CHECK-NEXT: .cfi_def_cfa sp, 8041; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload42; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload43; CHECK-NEXT: .cfi_restore ra44; CHECK-NEXT: .cfi_restore s045; CHECK-NEXT: addi sp, sp, 8046; CHECK-NEXT: .cfi_def_cfa_offset 047; CHECK-NEXT: ret48 %a = bitcast <vscale x 16 x i8> %x to <vscale x 128 x i1>49 %b = extractelement <vscale x 128 x i1> %a, i64 %y50 ret i1 %b51}52 53define i8 @bar(<vscale x 128 x i1> %x, i64 %y) {54; CHECK-LABEL: bar:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, ma57; CHECK-NEXT: vmv1r.v v1, v858; CHECK-NEXT: vslidedown.vx v8, v0, a059; CHECK-NEXT: vmv.x.s a0, v860; CHECK-NEXT: ret61 %a = bitcast <vscale x 128 x i1> %x to <vscale x 16 x i8>62 %b = extractelement <vscale x 16 x i8> %a, i64 %y63 ret i8 %b64}65