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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3 4; This showcases a miscompile that was fixed in #90573:5; - The memset will be type-legalized to a 512 bit store + 2 x 128 bit stores.6; - the load and store of q aliases the upper 128 bits store of p.7; - The aliasing 128 bit store will be between the chain of the scalar8; load/store:9;10; t54: ch = store<(store (s512) into %ir.p, align 1)> t0, ...11; t51: ch = store<(store (s128) into %ir.p + 64, align 1)> t0, ...12;13; t44: i64,ch = load<(load (s32) from %ir.q), sext from i32> t0, ...14; t50: ch = store<(store (s128) into %ir.p + 80, align 1)> t44:1, ...15; t46: ch = store<(store (s32) into %ir.q), trunc to i32> t50, ...16;17; Previously, the scalar load/store was incorrectly combined away:18;19; t54: ch = store<(store (s512) into %ir.p, align 1)> t0, ...20; t51: ch = store<(store (s128) into %ir.p + 64, align 1)> t0, ...21;22; // MISSING23; t50: ch = store<(store (s128) into %ir.p + 80, align 1)> t44:1, ...24; // MISSING25; See also pr83017.ll: This is the same code, but relies on vscale_range instead26; of -riscv-v-vector-bits-max=128.27define void @f(ptr %p) vscale_range(2,2) {28; CHECK-LABEL: f:29; CHECK: # %bb.0:30; CHECK-NEXT: lw a1, 84(a0)31; CHECK-NEXT: addi a2, a0, 8032; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma33; CHECK-NEXT: vmv.v.i v8, 034; CHECK-NEXT: vs1r.v v8, (a2)35; CHECK-NEXT: addi a2, a0, 6436; CHECK-NEXT: vs1r.v v8, (a2)37; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, ma38; CHECK-NEXT: vmv.v.i v8, 039; CHECK-NEXT: vs4r.v v8, (a0)40; CHECK-NEXT: sw a1, 84(a0)41; CHECK-NEXT: ret42 %q = getelementptr inbounds i8, ptr %p, i64 8443 %x = load i32, ptr %q44 call void @llvm.memset.p0.i64(ptr %p, i8 0, i64 96, i1 false)45 store i32 %x, ptr %q46 ret void47}48