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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv64 -mattr=+v,+c < %s | FileCheck %s3 4; This previously crashed when spilling a GPR because when we removed a dead5; ADDI we weren't removing it from the LIS instruction map. Needs +c to trigger.6 7define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscale x 4 x i1> %arg.6, i64 %arg.7, i1 %arg.8, i64 %arg.9, i32 %arg.10) vscale_range(2,2) {8; CHECK-LABEL: main:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: addi sp, sp, -11211; CHECK-NEXT: .cfi_def_cfa_offset 11212; CHECK-NEXT: sd ra, 104(sp) # 8-byte Folded Spill13; CHECK-NEXT: sd s0, 96(sp) # 8-byte Folded Spill14; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill15; CHECK-NEXT: sd s2, 80(sp) # 8-byte Folded Spill16; CHECK-NEXT: sd s3, 72(sp) # 8-byte Folded Spill17; CHECK-NEXT: sd s4, 64(sp) # 8-byte Folded Spill18; CHECK-NEXT: sd s5, 56(sp) # 8-byte Folded Spill19; CHECK-NEXT: sd s6, 48(sp) # 8-byte Folded Spill20; CHECK-NEXT: sd s7, 40(sp) # 8-byte Folded Spill21; CHECK-NEXT: sd s8, 32(sp) # 8-byte Folded Spill22; CHECK-NEXT: sd s9, 24(sp) # 8-byte Folded Spill23; CHECK-NEXT: sd s10, 16(sp) # 8-byte Folded Spill24; CHECK-NEXT: sd s11, 8(sp) # 8-byte Folded Spill25; CHECK-NEXT: .cfi_offset ra, -826; CHECK-NEXT: .cfi_offset s0, -1627; CHECK-NEXT: .cfi_offset s1, -2428; CHECK-NEXT: .cfi_offset s2, -3229; CHECK-NEXT: .cfi_offset s3, -4030; CHECK-NEXT: .cfi_offset s4, -4831; CHECK-NEXT: .cfi_offset s5, -5632; CHECK-NEXT: .cfi_offset s6, -6433; CHECK-NEXT: .cfi_offset s7, -7234; CHECK-NEXT: .cfi_offset s8, -8035; CHECK-NEXT: .cfi_offset s9, -8836; CHECK-NEXT: .cfi_offset s10, -9637; CHECK-NEXT: .cfi_offset s11, -10438; CHECK-NEXT: li a6, 039; CHECK-NEXT: li s2, 840; CHECK-NEXT: li t0, 1241; CHECK-NEXT: li s0, 442; CHECK-NEXT: li t1, 2043; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma44; CHECK-NEXT: vmv.v.i v8, 045; CHECK-NEXT: andi t3, a4, 146; CHECK-NEXT: li t2, 447; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader.i48; CHECK-NEXT: # =>This Loop Header: Depth=149; CHECK-NEXT: # Child Loop BB0_2 Depth 250; CHECK-NEXT: # Child Loop BB0_3 Depth 351; CHECK-NEXT: # Child Loop BB0_4 Depth 452; CHECK-NEXT: # Child Loop BB0_5 Depth 553; CHECK-NEXT: mv t4, t154; CHECK-NEXT: mv t5, t255; CHECK-NEXT: mv t6, t056; CHECK-NEXT: mv a7, s257; CHECK-NEXT: mv s4, a658; CHECK-NEXT: .LBB0_2: # %for.cond5.preheader.i59; CHECK-NEXT: # Parent Loop BB0_1 Depth=160; CHECK-NEXT: # => This Loop Header: Depth=261; CHECK-NEXT: # Child Loop BB0_3 Depth 362; CHECK-NEXT: # Child Loop BB0_4 Depth 463; CHECK-NEXT: # Child Loop BB0_5 Depth 564; CHECK-NEXT: mv s5, t465; CHECK-NEXT: mv s6, t566; CHECK-NEXT: mv s7, t667; CHECK-NEXT: mv s3, a768; CHECK-NEXT: mv s9, s469; CHECK-NEXT: .LBB0_3: # %for.cond9.preheader.i70; CHECK-NEXT: # Parent Loop BB0_1 Depth=171; CHECK-NEXT: # Parent Loop BB0_2 Depth=272; CHECK-NEXT: # => This Loop Header: Depth=373; CHECK-NEXT: # Child Loop BB0_4 Depth 474; CHECK-NEXT: # Child Loop BB0_5 Depth 575; CHECK-NEXT: mv s11, s576; CHECK-NEXT: mv a3, s677; CHECK-NEXT: mv ra, s778; CHECK-NEXT: mv s8, s379; CHECK-NEXT: mv s1, s980; CHECK-NEXT: .LBB0_4: # %vector.ph.i81; CHECK-NEXT: # Parent Loop BB0_1 Depth=182; CHECK-NEXT: # Parent Loop BB0_2 Depth=283; CHECK-NEXT: # Parent Loop BB0_3 Depth=384; CHECK-NEXT: # => This Loop Header: Depth=485; CHECK-NEXT: # Child Loop BB0_5 Depth 586; CHECK-NEXT: li a1, 087; CHECK-NEXT: .LBB0_5: # %vector.body.i88; CHECK-NEXT: # Parent Loop BB0_1 Depth=189; CHECK-NEXT: # Parent Loop BB0_2 Depth=290; CHECK-NEXT: # Parent Loop BB0_3 Depth=391; CHECK-NEXT: # Parent Loop BB0_4 Depth=492; CHECK-NEXT: # => This Inner Loop Header: Depth=593; CHECK-NEXT: addi a5, a1, 494; CHECK-NEXT: add a4, s8, a195; CHECK-NEXT: add a1, a1, a396; CHECK-NEXT: vse32.v v8, (a4), v0.t97; CHECK-NEXT: vse32.v v8, (a1), v0.t98; CHECK-NEXT: mv a1, a599; CHECK-NEXT: bne a5, s0, .LBB0_5100; CHECK-NEXT: # %bb.6: # %for.cond.cleanup15.i101; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=4102; CHECK-NEXT: addi s1, s1, 4103; CHECK-NEXT: addi s8, s8, 4104; CHECK-NEXT: addi ra, ra, 4105; CHECK-NEXT: addi a3, a3, 4106; CHECK-NEXT: andi s10, a0, 1107; CHECK-NEXT: addi s11, s11, 4108; CHECK-NEXT: beqz s10, .LBB0_4109; CHECK-NEXT: # %bb.7: # %for.cond.cleanup11.i110; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=3111; CHECK-NEXT: addi s9, s9, 4112; CHECK-NEXT: addi s3, s3, 4113; CHECK-NEXT: addi s7, s7, 4114; CHECK-NEXT: addi s6, s6, 4115; CHECK-NEXT: andi a1, a2, 1116; CHECK-NEXT: addi s5, s5, 4117; CHECK-NEXT: beqz a1, .LBB0_3118; CHECK-NEXT: # %bb.8: # %for.cond.cleanup7.i119; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=2120; CHECK-NEXT: addi s4, s4, 4121; CHECK-NEXT: addi a7, a7, 4122; CHECK-NEXT: addi t6, t6, 4123; CHECK-NEXT: addi t5, t5, 4124; CHECK-NEXT: addi t4, t4, 4125; CHECK-NEXT: beqz t3, .LBB0_2126; CHECK-NEXT: # %bb.9: # %for.cond.cleanup3.i127; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1128; CHECK-NEXT: addi a6, a6, 4129; CHECK-NEXT: addi s2, s2, 4130; CHECK-NEXT: addi t0, t0, 4131; CHECK-NEXT: addi t2, t2, 4132; CHECK-NEXT: addi t1, t1, 4133; CHECK-NEXT: beqz a1, .LBB0_1134; CHECK-NEXT: # %bb.10: # %l.exit135; CHECK-NEXT: li a0, 0136; CHECK-NEXT: jalr a0137; CHECK-NEXT: beqz s10, .LBB0_12138; CHECK-NEXT: .LBB0_11: # %for.body7.us.14139; CHECK-NEXT: # =>This Inner Loop Header: Depth=1140; CHECK-NEXT: j .LBB0_11141; CHECK-NEXT: .LBB0_12: # %for.body7.us.19142; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma143; CHECK-NEXT: ld a0, 112(sp)144; CHECK-NEXT: vmv.s.x v16, a0145; CHECK-NEXT: vmv.v.i v8, 0146; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma147; CHECK-NEXT: vslideup.vi v8, v16, 1148; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma149; CHECK-NEXT: vmsne.vi v16, v8, 0150; CHECK-NEXT: vmv.x.s a0, v16151; CHECK-NEXT: snez a0, a0152; CHECK-NEXT: sb a0, 0(zero)153; CHECK-NEXT: li a0, 0154; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload155; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload156; CHECK-NEXT: ld s1, 88(sp) # 8-byte Folded Reload157; CHECK-NEXT: ld s2, 80(sp) # 8-byte Folded Reload158; CHECK-NEXT: ld s3, 72(sp) # 8-byte Folded Reload159; CHECK-NEXT: ld s4, 64(sp) # 8-byte Folded Reload160; CHECK-NEXT: ld s5, 56(sp) # 8-byte Folded Reload161; CHECK-NEXT: ld s6, 48(sp) # 8-byte Folded Reload162; CHECK-NEXT: ld s7, 40(sp) # 8-byte Folded Reload163; CHECK-NEXT: ld s8, 32(sp) # 8-byte Folded Reload164; CHECK-NEXT: ld s9, 24(sp) # 8-byte Folded Reload165; CHECK-NEXT: ld s10, 16(sp) # 8-byte Folded Reload166; CHECK-NEXT: ld s11, 8(sp) # 8-byte Folded Reload167; CHECK-NEXT: .cfi_restore ra168; CHECK-NEXT: .cfi_restore s0169; CHECK-NEXT: .cfi_restore s1170; CHECK-NEXT: .cfi_restore s2171; CHECK-NEXT: .cfi_restore s3172; CHECK-NEXT: .cfi_restore s4173; CHECK-NEXT: .cfi_restore s5174; CHECK-NEXT: .cfi_restore s6175; CHECK-NEXT: .cfi_restore s7176; CHECK-NEXT: .cfi_restore s8177; CHECK-NEXT: .cfi_restore s9178; CHECK-NEXT: .cfi_restore s10179; CHECK-NEXT: .cfi_restore s11180; CHECK-NEXT: addi sp, sp, 112181; CHECK-NEXT: .cfi_def_cfa_offset 0182; CHECK-NEXT: ret183entry:184 %0 = tail call <vscale x 4 x i64> @llvm.stepvector.nxv4i64()185 br label %for.cond1.preheader.i186 187for.cond1.preheader.i: ; preds = %for.cond.cleanup3.i, %entry188 %arg.21 = phi i64 [ 0, %entry ], [ %indvars.iv.next74.i, %for.cond.cleanup3.i ]189 br label %for.cond5.preheader.i190 191for.cond5.preheader.i: ; preds = %for.cond.cleanup7.i, %for.cond1.preheader.i192 %arg.42 = phi i64 [ 0, %for.cond1.preheader.i ], [ %indvars.iv.next70.i, %for.cond.cleanup7.i ]193 %1 = add i64 %arg.42, %arg.21194 br label %for.cond9.preheader.i195 196for.cond.cleanup3.i: ; preds = %for.cond.cleanup7.i197 %indvars.iv.next74.i = add i64 %arg.21, 1198 br i1 %arg.3, label %l.exit, label %for.cond1.preheader.i199 200for.cond9.preheader.i: ; preds = %for.cond.cleanup11.i, %for.cond5.preheader.i201 %arg.74 = phi i64 [ 0, %for.cond5.preheader.i ], [ %indvars.iv.next66.i, %for.cond.cleanup11.i ]202 %2 = add i64 %1, %arg.74203 br label %vector.ph.i204 205for.cond.cleanup7.i: ; preds = %for.cond.cleanup11.i206 %indvars.iv.next70.i = add i64 %arg.42, 1207 br i1 %arg.5, label %for.cond.cleanup3.i, label %for.cond5.preheader.i208 209vector.ph.i: ; preds = %for.cond.cleanup15.i, %for.cond9.preheader.i210 %arg.96 = phi i64 [ 0, %for.cond9.preheader.i ], [ %indvars.iv.next62.i, %for.cond.cleanup15.i ]211 %3 = add i64 %2, %arg.96212 %broadcast.splatinsert.i = insertelement <vscale x 4 x i64> zeroinitializer, i64 %3, i64 0213 %broadcast.splat.i = shufflevector <vscale x 4 x i64> %broadcast.splatinsert.i, <vscale x 4 x i64> zeroinitializer, <vscale x 4 x i32> zeroinitializer214 br label %vector.body.i215 216vector.body.i: ; preds = %vector.body.i, %vector.ph.i217 %index.i = phi i64 [ 0, %vector.ph.i ], [ %index.next.i, %vector.body.i ]218 %vec.ind.i = phi <vscale x 4 x i64> [ %0, %vector.ph.i ], [ %6, %vector.body.i ]219 %4 = add <vscale x 4 x i64> %vec.ind.i, %broadcast.splat.i220 %5 = getelementptr [6 x i32], ptr null, i64 0, <vscale x 4 x i64> %4221 tail call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x ptr> %5, i32 4, <vscale x 4 x i1> zeroinitializer)222 %6 = add <vscale x 4 x i64> %vec.ind.i, shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 1, i64 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)223 %7 = getelementptr [6 x i32], ptr null, i64 0, <vscale x 4 x i64> %6224 tail call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x ptr> %7, i32 4, <vscale x 4 x i1> zeroinitializer)225 %arg.100 = add <vscale x 4 x i64> %4, shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 2, i64 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)226 %arg.101 = getelementptr [6 x i32], ptr null, i64 0, <vscale x 4 x i64> %arg.100227 tail call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x ptr> %arg.101, i32 4, <vscale x 4 x i1> %arg.6)228 %arg.102 = add <vscale x 4 x i64> %4, shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 3, i64 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)229 %arg.103 = getelementptr [6 x i32], ptr null, i64 0, <vscale x 4 x i64> %arg.102230 tail call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x ptr> %arg.103, i32 4, <vscale x 4 x i1> zeroinitializer)231 %arg.104 = add <vscale x 4 x i64> %4, shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 1, i64 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)232 %arg.105 = getelementptr [6 x i32], ptr null, i64 0, <vscale x 4 x i64> %arg.104233 tail call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x ptr> %arg.105, i32 4, <vscale x 4 x i1> %arg.6)234 %arg.106 = add <vscale x 4 x i64> %4, shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 5, i64 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)235 %arg.107 = getelementptr [6 x i32], ptr null, i64 0, <vscale x 4 x i64> %arg.106236 tail call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x ptr> %arg.107, i32 4, <vscale x 4 x i1> zeroinitializer)237 %index.next.i = add i64 %index.i, 1238 %arg.108 = icmp eq i64 %index.i, 0239 br i1 %arg.108, label %for.cond.cleanup15.i, label %vector.body.i240 241for.cond.cleanup11.i: ; preds = %for.cond.cleanup15.i242 %indvars.iv.next66.i = add i64 %arg.74, 1243 br i1 %arg.3, label %for.cond.cleanup7.i, label %for.cond9.preheader.i244 245for.cond.cleanup15.i: ; preds = %vector.body.i246 %indvars.iv.next62.i = add i64 %arg.96, 1247 br i1 %arg.1, label %for.cond.cleanup11.i, label %vector.ph.i248 249l.exit: ; preds = %for.cond.cleanup3.i250 tail call void null()251 br i1 %arg.1, label %for.body7.us.14, label %for.body7.us.19252 253for.body7.us.14: ; preds = %for.body7.us.14, %l.exit254 br label %for.body7.us.14255 256for.body7.us.19: ; preds = %l.exit257 %arg.109 = insertelement <32 x i32> zeroinitializer, i32 %arg.10, i64 1258 %8 = icmp ne <32 x i32> %arg.109, zeroinitializer259 %9 = bitcast <32 x i1> %8 to i32260 %op.rdx13 = icmp ne i32 %9, 0261 %op.rdx = zext i1 %op.rdx13 to i8262 store i8 %op.rdx, ptr null, align 1263 ret i32 0264}265