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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv64 -mattr='+v,+zvl512b' < %s | FileCheck %s3 4define <2 x float> @redundant_vfmv(<2 x float> %arg0, <64 x float> %arg1, <64 x float> %arg2) {5; CHECK-LABEL: redundant_vfmv:6; CHECK: # %bb.0:7; CHECK-NEXT: li a0, 648; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma9; CHECK-NEXT: vfredusum.vs v9, v12, v810; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma11; CHECK-NEXT: vslidedown.vi v8, v8, 112; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma13; CHECK-NEXT: vfredusum.vs v8, v16, v814; CHECK-NEXT: vsetivli zero, 2, e32, mf2, tu, ma15; CHECK-NEXT: vslideup.vi v9, v8, 116; CHECK-NEXT: vmv1r.v v8, v917; CHECK-NEXT: ret18 %s0 = extractelement <2 x float> %arg0, i64 019 %r0 = tail call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s0, <64 x float> %arg1)20 %a0 = insertelement <2 x float> poison, float %r0, i64 021 %s1 = extractelement <2 x float> %arg0, i64 122 %r1 = tail call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s1, <64 x float> %arg2)23 %a1 = insertelement <2 x float> %a0, float %r1, i64 124 ret <2 x float> %a125}26