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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m \3; RUN: -regalloc=fast -verify-machineinstrs < %s | FileCheck %s4 5; This test previously crashed with an error "ran out of registers during register allocation"6 7define void @test_vsseg2_mask_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask, i32 %vl) {8; CHECK-LABEL: test_vsseg2_mask_nxv16i16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma11; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t12; CHECK-NEXT: ret13entry:14 tail call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask, i32 %vl, i32 4)15 ret void16}17