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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s3 4define void @vid(ptr %p) {5; CHECK-LABEL: vid:6; CHECK: # %bb.0:7; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma8; CHECK-NEXT: vid.v v89; CHECK-NEXT: vs8r.v v8, (a0)10; CHECK-NEXT: vl8re64.v v16, (a0)11; CHECK-NEXT: vl8re64.v v24, (a0)12; CHECK-NEXT: vl8re64.v v0, (a0)13; CHECK-NEXT: vl8re64.v v8, (a0)14; CHECK-NEXT: vs8r.v v8, (a0)15; CHECK-NEXT: vs8r.v v0, (a0)16; CHECK-NEXT: vs8r.v v24, (a0)17; CHECK-NEXT: vs8r.v v16, (a0)18; CHECK-NEXT: vid.v v819; CHECK-NEXT: vs8r.v v8, (a0)20; CHECK-NEXT: ret21 %vid = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(<vscale x 8 x i64> poison, i64 -1)22 store volatile <vscale x 8 x i64> %vid, ptr %p23 24 %a = load volatile <vscale x 8 x i64>, ptr %p25 %b = load volatile <vscale x 8 x i64>, ptr %p26 %c = load volatile <vscale x 8 x i64>, ptr %p27 %d = load volatile <vscale x 8 x i64>, ptr %p28 store volatile <vscale x 8 x i64> %d, ptr %p29 store volatile <vscale x 8 x i64> %c, ptr %p30 store volatile <vscale x 8 x i64> %b, ptr %p31 store volatile <vscale x 8 x i64> %a, ptr %p32 33 store volatile <vscale x 8 x i64> %vid, ptr %p34 ret void35}36 37 38define void @vid_passthru(ptr %p, <vscale x 8 x i64> %v) {39; CHECK-LABEL: vid_passthru:40; CHECK: # %bb.0:41; CHECK-NEXT: addi sp, sp, -1642; CHECK-NEXT: .cfi_def_cfa_offset 1643; CHECK-NEXT: csrr a1, vlenb44; CHECK-NEXT: slli a1, a1, 345; CHECK-NEXT: sub sp, sp, a146; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb47; CHECK-NEXT: vsetivli zero, 1, e64, m8, tu, ma48; CHECK-NEXT: vid.v v849; CHECK-NEXT: vs8r.v v8, (a0)50; CHECK-NEXT: vl8re64.v v16, (a0)51; CHECK-NEXT: addi a1, sp, 1652; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill53; CHECK-NEXT: vl8re64.v v24, (a0)54; CHECK-NEXT: vl8re64.v v0, (a0)55; CHECK-NEXT: vl8re64.v v16, (a0)56; CHECK-NEXT: vs8r.v v16, (a0)57; CHECK-NEXT: vs8r.v v0, (a0)58; CHECK-NEXT: vs8r.v v24, (a0)59; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload60; CHECK-NEXT: vs8r.v v16, (a0)61; CHECK-NEXT: vs8r.v v8, (a0)62; CHECK-NEXT: csrr a0, vlenb63; CHECK-NEXT: slli a0, a0, 364; CHECK-NEXT: add sp, sp, a065; CHECK-NEXT: .cfi_def_cfa sp, 1666; CHECK-NEXT: addi sp, sp, 1667; CHECK-NEXT: .cfi_def_cfa_offset 068; CHECK-NEXT: ret69 %vid = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(<vscale x 8 x i64> %v, i64 1)70 store volatile <vscale x 8 x i64> %vid, ptr %p71 72 %a = load volatile <vscale x 8 x i64>, ptr %p73 %b = load volatile <vscale x 8 x i64>, ptr %p74 %c = load volatile <vscale x 8 x i64>, ptr %p75 %d = load volatile <vscale x 8 x i64>, ptr %p76 store volatile <vscale x 8 x i64> %d, ptr %p77 store volatile <vscale x 8 x i64> %c, ptr %p78 store volatile <vscale x 8 x i64> %b, ptr %p79 store volatile <vscale x 8 x i64> %a, ptr %p80 81 store volatile <vscale x 8 x i64> %vid, ptr %p82 ret void83}84 85define void @vmv.v.i(ptr %p) {86; CHECK-LABEL: vmv.v.i:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma89; CHECK-NEXT: vmv.v.i v8, 190; CHECK-NEXT: vs8r.v v8, (a0)91; CHECK-NEXT: vl8re64.v v16, (a0)92; CHECK-NEXT: vl8re64.v v24, (a0)93; CHECK-NEXT: vl8re64.v v0, (a0)94; CHECK-NEXT: vl8re64.v v8, (a0)95; CHECK-NEXT: vs8r.v v8, (a0)96; CHECK-NEXT: vs8r.v v0, (a0)97; CHECK-NEXT: vs8r.v v24, (a0)98; CHECK-NEXT: vs8r.v v16, (a0)99; CHECK-NEXT: vmv.v.i v8, 1100; CHECK-NEXT: vs8r.v v8, (a0)101; CHECK-NEXT: ret102 %vmv.v.i = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(<vscale x 8 x i64> poison, i64 1, i64 -1)103 store volatile <vscale x 8 x i64> %vmv.v.i, ptr %p104 105 %a = load volatile <vscale x 8 x i64>, ptr %p106 %b = load volatile <vscale x 8 x i64>, ptr %p107 %c = load volatile <vscale x 8 x i64>, ptr %p108 %d = load volatile <vscale x 8 x i64>, ptr %p109 store volatile <vscale x 8 x i64> %d, ptr %p110 store volatile <vscale x 8 x i64> %c, ptr %p111 store volatile <vscale x 8 x i64> %b, ptr %p112 store volatile <vscale x 8 x i64> %a, ptr %p113 114 store volatile <vscale x 8 x i64> %vmv.v.i, ptr %p115 ret void116}117 118define void @vmv.v.x_needs_extended(ptr %p, i64 %x) {119; CHECK-LABEL: vmv.v.x_needs_extended:120; CHECK: # %bb.0:121; CHECK-NEXT: addi sp, sp, -16122; CHECK-NEXT: .cfi_def_cfa_offset 16123; CHECK-NEXT: csrr a2, vlenb124; CHECK-NEXT: slli a2, a2, 3125; CHECK-NEXT: sub sp, sp, a2126; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb127; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma128; CHECK-NEXT: vmv.v.x v8, a1129; CHECK-NEXT: vs8r.v v8, (a0)130; CHECK-NEXT: vl8re64.v v16, (a0)131; CHECK-NEXT: addi a1, sp, 16132; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill133; CHECK-NEXT: vl8re64.v v24, (a0)134; CHECK-NEXT: vl8re64.v v0, (a0)135; CHECK-NEXT: vl8re64.v v16, (a0)136; CHECK-NEXT: vs8r.v v16, (a0)137; CHECK-NEXT: vs8r.v v0, (a0)138; CHECK-NEXT: vs8r.v v24, (a0)139; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload140; CHECK-NEXT: vs8r.v v16, (a0)141; CHECK-NEXT: vs8r.v v8, (a0)142; CHECK-NEXT: csrr a0, vlenb143; CHECK-NEXT: slli a0, a0, 3144; CHECK-NEXT: add sp, sp, a0145; CHECK-NEXT: .cfi_def_cfa sp, 16146; CHECK-NEXT: addi sp, sp, 16147; CHECK-NEXT: .cfi_def_cfa_offset 0148; CHECK-NEXT: ret149 %vmv.v.x = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(<vscale x 8 x i64> poison, i64 %x, i64 -1)150 store volatile <vscale x 8 x i64> %vmv.v.x, ptr %p151 152 %a = load volatile <vscale x 8 x i64>, ptr %p153 %b = load volatile <vscale x 8 x i64>, ptr %p154 %c = load volatile <vscale x 8 x i64>, ptr %p155 %d = load volatile <vscale x 8 x i64>, ptr %p156 store volatile <vscale x 8 x i64> %d, ptr %p157 store volatile <vscale x 8 x i64> %c, ptr %p158 store volatile <vscale x 8 x i64> %b, ptr %p159 store volatile <vscale x 8 x i64> %a, ptr %p160 161 store volatile <vscale x 8 x i64> %vmv.v.x, ptr %p162 ret void163}164 165define void @vmv.v.x_live(ptr %p, i64 %x) {166; CHECK-LABEL: vmv.v.x_live:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma169; CHECK-NEXT: vmv.v.x v8, a1170; CHECK-NEXT: vs8r.v v8, (a0)171; CHECK-NEXT: vl8re64.v v16, (a0)172; CHECK-NEXT: vl8re64.v v24, (a0)173; CHECK-NEXT: vl8re64.v v0, (a0)174; CHECK-NEXT: vl8re64.v v8, (a0)175; CHECK-NEXT: vs8r.v v8, (a0)176; CHECK-NEXT: vs8r.v v0, (a0)177; CHECK-NEXT: vs8r.v v24, (a0)178; CHECK-NEXT: vs8r.v v16, (a0)179; CHECK-NEXT: vmv.v.x v8, a1180; CHECK-NEXT: vs8r.v v8, (a0)181; CHECK-NEXT: sd a1, 0(a0)182; CHECK-NEXT: ret183 %vmv.v.x = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(<vscale x 8 x i64> poison, i64 %x, i64 -1)184 store volatile <vscale x 8 x i64> %vmv.v.x, ptr %p185 186 %a = load volatile <vscale x 8 x i64>, ptr %p187 %b = load volatile <vscale x 8 x i64>, ptr %p188 %c = load volatile <vscale x 8 x i64>, ptr %p189 %d = load volatile <vscale x 8 x i64>, ptr %p190 store volatile <vscale x 8 x i64> %d, ptr %p191 store volatile <vscale x 8 x i64> %c, ptr %p192 store volatile <vscale x 8 x i64> %b, ptr %p193 store volatile <vscale x 8 x i64> %a, ptr %p194 195 store volatile <vscale x 8 x i64> %vmv.v.x, ptr %p196 store volatile i64 %x, ptr %p197 ret void198}199 200define void @vfmv.v.f(ptr %p, double %x) {201; CHECK-LABEL: vfmv.v.f:202; CHECK: # %bb.0:203; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma204; CHECK-NEXT: vfmv.v.f v8, fa0205; CHECK-NEXT: vs8r.v v8, (a0)206; CHECK-NEXT: vl8re64.v v16, (a0)207; CHECK-NEXT: vl8re64.v v24, (a0)208; CHECK-NEXT: vl8re64.v v0, (a0)209; CHECK-NEXT: vl8re64.v v8, (a0)210; CHECK-NEXT: vs8r.v v8, (a0)211; CHECK-NEXT: vs8r.v v0, (a0)212; CHECK-NEXT: vs8r.v v24, (a0)213; CHECK-NEXT: vs8r.v v16, (a0)214; CHECK-NEXT: vfmv.v.f v8, fa0215; CHECK-NEXT: vs8r.v v8, (a0)216; CHECK-NEXT: fsd fa0, 0(a0)217; CHECK-NEXT: ret218 %vfmv.v.f = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64(<vscale x 8 x double> poison, double %x, i64 -1)219 store volatile <vscale x 8 x double> %vfmv.v.f, ptr %p220 221 %a = load volatile <vscale x 8 x double>, ptr %p222 %b = load volatile <vscale x 8 x double>, ptr %p223 %c = load volatile <vscale x 8 x double>, ptr %p224 %d = load volatile <vscale x 8 x double>, ptr %p225 store volatile <vscale x 8 x double> %d, ptr %p226 store volatile <vscale x 8 x double> %c, ptr %p227 store volatile <vscale x 8 x double> %b, ptr %p228 store volatile <vscale x 8 x double> %a, ptr %p229 230 store volatile <vscale x 8 x double> %vfmv.v.f, ptr %p231 store volatile double %x, ptr %p232 ret void233}234 235define void @vmv.s.x(ptr %p, i64 %x) {236; CHECK-LABEL: vmv.s.x:237; CHECK: # %bb.0:238; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma239; CHECK-NEXT: vmv.s.x v8, a1240; CHECK-NEXT: vs8r.v v8, (a0)241; CHECK-NEXT: vl8re64.v v16, (a0)242; CHECK-NEXT: vl8re64.v v24, (a0)243; CHECK-NEXT: vl8re64.v v0, (a0)244; CHECK-NEXT: vl8re64.v v8, (a0)245; CHECK-NEXT: vs8r.v v8, (a0)246; CHECK-NEXT: vs8r.v v0, (a0)247; CHECK-NEXT: vs8r.v v24, (a0)248; CHECK-NEXT: vs8r.v v16, (a0)249; CHECK-NEXT: vmv.s.x v8, a1250; CHECK-NEXT: vs8r.v v8, (a0)251; CHECK-NEXT: sd a1, 0(a0)252; CHECK-NEXT: ret253 %vmv.s.x = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64> poison, i64 %x, i64 -1)254 store volatile <vscale x 8 x i64> %vmv.s.x, ptr %p255 256 %a = load volatile <vscale x 8 x i64>, ptr %p257 %b = load volatile <vscale x 8 x i64>, ptr %p258 %c = load volatile <vscale x 8 x i64>, ptr %p259 %d = load volatile <vscale x 8 x i64>, ptr %p260 store volatile <vscale x 8 x i64> %d, ptr %p261 store volatile <vscale x 8 x i64> %c, ptr %p262 store volatile <vscale x 8 x i64> %b, ptr %p263 store volatile <vscale x 8 x i64> %a, ptr %p264 265 store volatile <vscale x 8 x i64> %vmv.s.x, ptr %p266 store volatile i64 %x, ptr %p267 ret void268}269 270define void @vfmv.s.f(ptr %p, double %x) {271; CHECK-LABEL: vfmv.s.f:272; CHECK: # %bb.0:273; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma274; CHECK-NEXT: vfmv.s.f v8, fa0275; CHECK-NEXT: vs8r.v v8, (a0)276; CHECK-NEXT: vl8re64.v v16, (a0)277; CHECK-NEXT: vl8re64.v v24, (a0)278; CHECK-NEXT: vl8re64.v v0, (a0)279; CHECK-NEXT: vl8re64.v v8, (a0)280; CHECK-NEXT: vs8r.v v8, (a0)281; CHECK-NEXT: vs8r.v v0, (a0)282; CHECK-NEXT: vs8r.v v24, (a0)283; CHECK-NEXT: vs8r.v v16, (a0)284; CHECK-NEXT: vfmv.s.f v8, fa0285; CHECK-NEXT: vs8r.v v8, (a0)286; CHECK-NEXT: fsd fa0, 0(a0)287; CHECK-NEXT: ret288 %vfmv.s.f = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> poison, double %x, i64 -1)289 store volatile <vscale x 8 x double> %vfmv.s.f, ptr %p290 291 %a = load volatile <vscale x 8 x double>, ptr %p292 %b = load volatile <vscale x 8 x double>, ptr %p293 %c = load volatile <vscale x 8 x double>, ptr %p294 %d = load volatile <vscale x 8 x double>, ptr %p295 store volatile <vscale x 8 x double> %d, ptr %p296 store volatile <vscale x 8 x double> %c, ptr %p297 store volatile <vscale x 8 x double> %b, ptr %p298 store volatile <vscale x 8 x double> %a, ptr %p299 300 store volatile <vscale x 8 x double> %vfmv.s.f, ptr %p301 store volatile double %x, ptr %p302 ret void303}304 305; This test is fairly fragile, but it's trying to cover the case which306; caused the revert of bba9172 due to interaction with how rematerialize307; instructions are pruned from the original live interval. In the result308; below, we remat the vmv.v.x into the loop, but fail to remat the vmv.v.x309; a second time after further splitting it's live range. We shouldn't need310; to spill it to the stack at all.311define i64 @dual_remat(i64 %0, <vscale x 16 x i64> %1, <vscale x 16 x i64> %2, ptr %p) #0 {312; CHECK-LABEL: dual_remat:313; CHECK: # %bb.0: # %entry314; CHECK-NEXT: addi sp, sp, -16315; CHECK-NEXT: .cfi_def_cfa_offset 16316; CHECK-NEXT: csrr a1, vlenb317; CHECK-NEXT: mv a2, a1318; CHECK-NEXT: slli a1, a1, 3319; CHECK-NEXT: add a2, a2, a1320; CHECK-NEXT: slli a1, a1, 1321; CHECK-NEXT: add a1, a1, a2322; CHECK-NEXT: sub sp, sp, a1323; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb324; CHECK-NEXT: csrr a1, vlenb325; CHECK-NEXT: slli a1, a1, 3326; CHECK-NEXT: add a1, sp, a1327; CHECK-NEXT: addi a1, a1, 16328; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill329; CHECK-NEXT: addi a1, sp, 16330; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill331; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma332; CHECK-NEXT: vmv.v.i v24, 0333; CHECK-NEXT: csrr a2, vlenb334; CHECK-NEXT: srli a1, a2, 3335; CHECK-NEXT: slli a2, a2, 3336; CHECK-NEXT: add a2, a3, a2337; CHECK-NEXT: vmv.v.i v0, 0338; CHECK-NEXT: .LBB8_1: # %vector.body339; CHECK-NEXT: # =>This Inner Loop Header: Depth=1340; CHECK-NEXT: vmv.v.x v8, a0341; CHECK-NEXT: csrr a4, vlenb342; CHECK-NEXT: slli a5, a4, 4343; CHECK-NEXT: add a4, a5, a4344; CHECK-NEXT: add a4, sp, a4345; CHECK-NEXT: addi a4, a4, 16346; CHECK-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill347; CHECK-NEXT: vand.vv v16, v0, v8348; CHECK-NEXT: vmv8r.v v8, v24349; CHECK-NEXT: vmsne.vi v24, v16, 0350; CHECK-NEXT: csrr a4, vlenb351; CHECK-NEXT: slli a4, a4, 4352; CHECK-NEXT: add a4, sp, a4353; CHECK-NEXT: addi a4, a4, 16354; CHECK-NEXT: vs1r.v v24, (a4) # vscale x 8-byte Folded Spill355; CHECK-NEXT: vmv8r.v v24, v8356; CHECK-NEXT: csrr a4, vlenb357; CHECK-NEXT: slli a5, a4, 4358; CHECK-NEXT: add a4, a5, a4359; CHECK-NEXT: add a4, sp, a4360; CHECK-NEXT: addi a4, a4, 16361; CHECK-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload362; CHECK-NEXT: vand.vv v16, v24, v8363; CHECK-NEXT: vmsne.vi v8, v16, 0364; CHECK-NEXT: csrr a4, vlenb365; CHECK-NEXT: slli a4, a4, 4366; CHECK-NEXT: add a4, sp, a4367; CHECK-NEXT: addi a4, a4, 16368; CHECK-NEXT: vl1r.v v9, (a4) # vscale x 8-byte Folded Reload369; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma370; CHECK-NEXT: vslideup.vx v9, v8, a1371; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma372; CHECK-NEXT: vcpop.m a4, v9373; CHECK-NEXT: csrr a5, vlenb374; CHECK-NEXT: slli a6, a5, 4375; CHECK-NEXT: add a5, a6, a5376; CHECK-NEXT: add a5, sp, a5377; CHECK-NEXT: addi a5, a5, 16378; CHECK-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload379; CHECK-NEXT: vs8r.v v8, (a3)380; CHECK-NEXT: vs8r.v v8, (a2)381; CHECK-NEXT: addi a5, sp, 16382; CHECK-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload383; CHECK-NEXT: vsetvli a5, zero, e64, m8, ta, ma384; CHECK-NEXT: vor.vv v0, v0, v8385; CHECK-NEXT: csrr a5, vlenb386; CHECK-NEXT: slli a5, a5, 3387; CHECK-NEXT: add a5, sp, a5388; CHECK-NEXT: addi a5, a5, 16389; CHECK-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload390; CHECK-NEXT: vor.vv v24, v24, v8391; CHECK-NEXT: beqz a4, .LBB8_1392; CHECK-NEXT: # %bb.2: # %middle.block393; CHECK-NEXT: andi a0, a0, 1394; CHECK-NEXT: csrr a1, vlenb395; CHECK-NEXT: mv a2, a1396; CHECK-NEXT: slli a1, a1, 3397; CHECK-NEXT: add a2, a2, a1398; CHECK-NEXT: slli a1, a1, 1399; CHECK-NEXT: add a1, a1, a2400; CHECK-NEXT: add sp, sp, a1401; CHECK-NEXT: .cfi_def_cfa sp, 16402; CHECK-NEXT: addi sp, sp, 16403; CHECK-NEXT: .cfi_def_cfa_offset 0404; CHECK-NEXT: ret405entry:406 %broadcast.splatinsert = insertelement <vscale x 16 x i64> zeroinitializer, i64 %0, i64 0407 %broadcast.splat = shufflevector <vscale x 16 x i64> %broadcast.splatinsert, <vscale x 16 x i64> zeroinitializer, <vscale x 16 x i32> zeroinitializer408 br label %vector.body409 410vector.body: ; preds = %vector.body, %entry411 %vec.ind = phi <vscale x 16 x i64> [ zeroinitializer, %entry ], [ %vec.ind.next, %vector.body ]412 %3 = and <vscale x 16 x i64> %vec.ind, %broadcast.splat413 %4 = icmp ne <vscale x 16 x i64> %3, zeroinitializer414 store <vscale x 16 x i64> %broadcast.splat, ptr %p415 %5 = tail call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %4)416 %vec.ind.next = or <vscale x 16 x i64> %vec.ind, %1417 br i1 %5, label %middle.block, label %vector.body418 419middle.block: ; preds = %vector.body420 %and.i = and i64 1, %0421 ret i64 %and.i422}423