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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"4target triple = "riscv64-unknown-linux-gnu"5 6define i32 @_ZN4Mesh12rezone_countESt6vectorIiSaIiEERiS3_(<vscale x 4 x i32> %wide.load, <vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %3) #0 {7; CHECK-LABEL: _ZN4Mesh12rezone_countESt6vectorIiSaIiEERiS3_:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, ma10; CHECK-NEXT: vmv1r.v v8, v011; CHECK-NEXT: li a0, 012; CHECK-NEXT: vmv.v.i v10, 013; CHECK-NEXT: vmv.v.i v12, 014; CHECK-NEXT: vmv.v.i v14, 015; CHECK-NEXT: .LBB0_1: # %vector.body16; CHECK-NEXT: # =>This Inner Loop Header: Depth=117; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, mu18; CHECK-NEXT: vmv1r.v v0, v819; CHECK-NEXT: slli a0, a0, 220; CHECK-NEXT: vmv2r.v v16, v1021; CHECK-NEXT: vle32.v v16, (a0), v0.t22; CHECK-NEXT: vand.vi v16, v16, 123; CHECK-NEXT: vmsne.vi v9, v16, 024; CHECK-NEXT: vmand.mm v0, v8, v925; CHECK-NEXT: vmerge.vim v12, v12, -1, v026; CHECK-NEXT: vmv1r.v v0, v827; CHECK-NEXT: vor.vi v14, v14, 1, v0.t28; CHECK-NEXT: li a0, 129; CHECK-NEXT: j .LBB0_130entry:31 br label %vector.body32 33vector.body: ; preds = %vector.body, %entry34 %index = phi i64 [ 0, %entry ], [ 1, %vector.body ]35 %vec.phi = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %predphi88, %vector.body ]36 %vec.phi81 = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %predphi93, %vector.body ]37 %wide.load1 = load <vscale x 4 x i32>, ptr null, align 438 %4 = icmp slt <vscale x 4 x i32> %wide.load, zeroinitializer39 %5 = icmp sgt <vscale x 4 x i32> %wide.load, zeroinitializer40 %wide.masked.load82 = tail call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr null, i32 1, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> zeroinitializer)41 %6 = icmp eq <vscale x 4 x i32> zeroinitializer, zeroinitializer42 %7 = getelementptr i32, ptr null, i64 %index43 %wide.masked.load83 = tail call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr %7, i32 1, <vscale x 4 x i1> %0, <vscale x 4 x i32> zeroinitializer)44 %8 = select <vscale x 4 x i1> %0, <vscale x 4 x i1> %0, <vscale x 4 x i1> zeroinitializer45 %9 = trunc <vscale x 4 x i32> %wide.masked.load83 to <vscale x 4 x i1>46 %narrow = select <vscale x 4 x i1> %0, <vscale x 4 x i1> %9, <vscale x 4 x i1> zeroinitializer47 %10 = sext <vscale x 4 x i1> %narrow to <vscale x 4 x i32>48 %predphi88 = or <vscale x 4 x i32> %vec.phi, %1049 %11 = zext <vscale x 4 x i1> %0 to <vscale x 4 x i32>50 %predphi93 = or <vscale x 4 x i32> %vec.phi81, %1151 %index.next = add i64 0, 152 br i1 false, label %middle.block, label %vector.body53 54middle.block: ; preds = %vector.body55 %12 = tail call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %vec.phi)56 %13 = tail call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %vec.phi81)57 ret i32 %1358}59 60; uselistorder directives61uselistorder ptr @llvm.masked.load.nxv4i32.p0, { 1, 0 }62uselistorder ptr @llvm.vector.reduce.add.nxv4i32, { 1, 0 }63 64attributes #0 = { "target-features"="+v" }65