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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH,RV32ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH,RV64ZVFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN,RV32ZVFMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN14 15define <vscale x 1 x bfloat> @vp_rint_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {16; CHECK-LABEL: vp_rint_nxv1bf16:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma19; CHECK-NEXT: vmv1r.v v9, v020; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t21; CHECK-NEXT: lui a0, 30720022; CHECK-NEXT: vmv1r.v v8, v023; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma24; CHECK-NEXT: vfabs.v v11, v10, v0.t25; CHECK-NEXT: fmv.w.x fa5, a026; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu27; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t28; CHECK-NEXT: vmv1r.v v0, v829; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma30; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t31; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t32; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu33; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t34; CHECK-NEXT: vmv1r.v v0, v935; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma36; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t37; CHECK-NEXT: ret38 %v = call <vscale x 1 x bfloat> @llvm.vp.rint.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)39 ret <vscale x 1 x bfloat> %v40}41 42define <vscale x 1 x bfloat> @vp_rint_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, i32 zeroext %evl) {43; CHECK-LABEL: vp_rint_nxv1bf16_unmasked:44; CHECK: # %bb.0:45; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma46; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v847; CHECK-NEXT: lui a0, 30720048; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma49; CHECK-NEXT: vfabs.v v8, v950; CHECK-NEXT: fmv.w.x fa5, a051; CHECK-NEXT: vmflt.vf v0, v8, fa552; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t53; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t54; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu55; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t56; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma57; CHECK-NEXT: vfncvtbf16.f.f.w v8, v958; CHECK-NEXT: ret59 %v = call <vscale x 1 x bfloat> @llvm.vp.rint.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)60 ret <vscale x 1 x bfloat> %v61}62 63define <vscale x 2 x bfloat> @vp_rint_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {64; CHECK-LABEL: vp_rint_nxv2bf16:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma67; CHECK-NEXT: vmv1r.v v9, v068; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t69; CHECK-NEXT: lui a0, 30720070; CHECK-NEXT: vmv1r.v v8, v071; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma72; CHECK-NEXT: vfabs.v v11, v10, v0.t73; CHECK-NEXT: fmv.w.x fa5, a074; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu75; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t76; CHECK-NEXT: vmv.v.v v0, v877; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma78; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t79; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t80; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu81; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t82; CHECK-NEXT: vmv1r.v v0, v983; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma84; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t85; CHECK-NEXT: ret86 %v = call <vscale x 2 x bfloat> @llvm.vp.rint.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)87 ret <vscale x 2 x bfloat> %v88}89 90define <vscale x 2 x bfloat> @vp_rint_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, i32 zeroext %evl) {91; CHECK-LABEL: vp_rint_nxv2bf16_unmasked:92; CHECK: # %bb.0:93; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma94; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v895; CHECK-NEXT: lui a0, 30720096; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma97; CHECK-NEXT: vfabs.v v8, v998; CHECK-NEXT: fmv.w.x fa5, a099; CHECK-NEXT: vmflt.vf v0, v8, fa5100; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t101; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t102; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu103; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t104; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma105; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9106; CHECK-NEXT: ret107 %v = call <vscale x 2 x bfloat> @llvm.vp.rint.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)108 ret <vscale x 2 x bfloat> %v109}110 111define <vscale x 4 x bfloat> @vp_rint_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {112; CHECK-LABEL: vp_rint_nxv4bf16:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma115; CHECK-NEXT: vmv1r.v v9, v0116; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t117; CHECK-NEXT: lui a0, 307200118; CHECK-NEXT: vmv1r.v v8, v0119; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma120; CHECK-NEXT: vfabs.v v12, v10, v0.t121; CHECK-NEXT: fmv.w.x fa5, a0122; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu123; CHECK-NEXT: vmflt.vf v8, v12, fa5, v0.t124; CHECK-NEXT: vmv1r.v v0, v8125; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma126; CHECK-NEXT: vfcvt.x.f.v v12, v10, v0.t127; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t128; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu129; CHECK-NEXT: vfsgnj.vv v10, v12, v10, v0.t130; CHECK-NEXT: vmv1r.v v0, v9131; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma132; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t133; CHECK-NEXT: ret134 %v = call <vscale x 4 x bfloat> @llvm.vp.rint.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 %evl)135 ret <vscale x 4 x bfloat> %v136}137 138define <vscale x 4 x bfloat> @vp_rint_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, i32 zeroext %evl) {139; CHECK-LABEL: vp_rint_nxv4bf16_unmasked:140; CHECK: # %bb.0:141; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma142; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8143; CHECK-NEXT: lui a0, 307200144; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma145; CHECK-NEXT: vfabs.v v8, v10146; CHECK-NEXT: fmv.w.x fa5, a0147; CHECK-NEXT: vmflt.vf v0, v8, fa5148; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t149; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t150; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu151; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t152; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma153; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10154; CHECK-NEXT: ret155 %v = call <vscale x 4 x bfloat> @llvm.vp.rint.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)156 ret <vscale x 4 x bfloat> %v157}158 159define <vscale x 8 x bfloat> @vp_rint_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {160; CHECK-LABEL: vp_rint_nxv8bf16:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma163; CHECK-NEXT: vmv1r.v v10, v0164; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t165; CHECK-NEXT: lui a0, 307200166; CHECK-NEXT: vmv1r.v v8, v0167; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma168; CHECK-NEXT: vfabs.v v16, v12, v0.t169; CHECK-NEXT: fmv.w.x fa5, a0170; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu171; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t172; CHECK-NEXT: vmv1r.v v0, v8173; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma174; CHECK-NEXT: vfcvt.x.f.v v16, v12, v0.t175; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t176; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu177; CHECK-NEXT: vfsgnj.vv v12, v16, v12, v0.t178; CHECK-NEXT: vmv1r.v v0, v10179; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma180; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t181; CHECK-NEXT: ret182 %v = call <vscale x 8 x bfloat> @llvm.vp.rint.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 %evl)183 ret <vscale x 8 x bfloat> %v184}185 186define <vscale x 8 x bfloat> @vp_rint_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, i32 zeroext %evl) {187; CHECK-LABEL: vp_rint_nxv8bf16_unmasked:188; CHECK: # %bb.0:189; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma190; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8191; CHECK-NEXT: lui a0, 307200192; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma193; CHECK-NEXT: vfabs.v v8, v12194; CHECK-NEXT: fmv.w.x fa5, a0195; CHECK-NEXT: vmflt.vf v0, v8, fa5196; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t197; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t198; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu199; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t200; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma201; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12202; CHECK-NEXT: ret203 %v = call <vscale x 8 x bfloat> @llvm.vp.rint.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)204 ret <vscale x 8 x bfloat> %v205}206 207define <vscale x 16 x bfloat> @vp_rint_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {208; CHECK-LABEL: vp_rint_nxv16bf16:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma211; CHECK-NEXT: vmv1r.v v12, v0212; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t213; CHECK-NEXT: lui a0, 307200214; CHECK-NEXT: vmv1r.v v8, v0215; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma216; CHECK-NEXT: vfabs.v v24, v16, v0.t217; CHECK-NEXT: fmv.w.x fa5, a0218; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu219; CHECK-NEXT: vmflt.vf v8, v24, fa5, v0.t220; CHECK-NEXT: vmv1r.v v0, v8221; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma222; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t223; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t224; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu225; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t226; CHECK-NEXT: vmv1r.v v0, v12227; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma228; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t229; CHECK-NEXT: ret230 %v = call <vscale x 16 x bfloat> @llvm.vp.rint.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 %evl)231 ret <vscale x 16 x bfloat> %v232}233 234define <vscale x 16 x bfloat> @vp_rint_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, i32 zeroext %evl) {235; CHECK-LABEL: vp_rint_nxv16bf16_unmasked:236; CHECK: # %bb.0:237; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma238; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8239; CHECK-NEXT: lui a0, 307200240; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma241; CHECK-NEXT: vfabs.v v8, v16242; CHECK-NEXT: fmv.w.x fa5, a0243; CHECK-NEXT: vmflt.vf v0, v8, fa5244; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t245; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t246; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu247; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t248; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma249; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16250; CHECK-NEXT: ret251 %v = call <vscale x 16 x bfloat> @llvm.vp.rint.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)252 ret <vscale x 16 x bfloat> %v253}254 255define <vscale x 32 x bfloat> @vp_rint_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {256; CHECK-LABEL: vp_rint_nxv32bf16:257; CHECK: # %bb.0:258; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma259; CHECK-NEXT: vmv1r.v v7, v0260; CHECK-NEXT: csrr a2, vlenb261; CHECK-NEXT: lui a3, 307200262; CHECK-NEXT: slli a1, a2, 1263; CHECK-NEXT: srli a2, a2, 2264; CHECK-NEXT: fmv.w.x fa5, a3265; CHECK-NEXT: sub a3, a0, a1266; CHECK-NEXT: vslidedown.vx v6, v0, a2267; CHECK-NEXT: sltu a2, a0, a3268; CHECK-NEXT: vmv1r.v v5, v6269; CHECK-NEXT: addi a2, a2, -1270; CHECK-NEXT: and a2, a2, a3271; CHECK-NEXT: vmv1r.v v0, v6272; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma273; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t274; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma275; CHECK-NEXT: vfabs.v v16, v24, v0.t276; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu277; CHECK-NEXT: vmflt.vf v5, v16, fa5, v0.t278; CHECK-NEXT: vmv1r.v v0, v5279; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma280; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t281; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t282; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu283; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t284; CHECK-NEXT: vmv1r.v v0, v6285; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma286; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t287; CHECK-NEXT: bltu a0, a1, .LBB10_2288; CHECK-NEXT: # %bb.1:289; CHECK-NEXT: mv a0, a1290; CHECK-NEXT: .LBB10_2:291; CHECK-NEXT: vmv1r.v v0, v7292; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma293; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t294; CHECK-NEXT: vmv1r.v v8, v7295; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma296; CHECK-NEXT: vfabs.v v16, v24, v0.t297; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu298; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t299; CHECK-NEXT: vmv1r.v v0, v8300; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma301; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t302; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t303; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu304; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t305; CHECK-NEXT: vmv1r.v v0, v7306; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma307; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t308; CHECK-NEXT: ret309 %v = call <vscale x 32 x bfloat> @llvm.vp.rint.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)310 ret <vscale x 32 x bfloat> %v311}312 313define <vscale x 32 x bfloat> @vp_rint_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, i32 zeroext %evl) {314; CHECK-LABEL: vp_rint_nxv32bf16_unmasked:315; CHECK: # %bb.0:316; CHECK-NEXT: csrr a2, vlenb317; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma318; CHECK-NEXT: vmset.m v16319; CHECK-NEXT: lui a3, 307200320; CHECK-NEXT: slli a1, a2, 1321; CHECK-NEXT: srli a2, a2, 2322; CHECK-NEXT: fmv.w.x fa5, a3323; CHECK-NEXT: sub a3, a0, a1324; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma325; CHECK-NEXT: vslidedown.vx v7, v16, a2326; CHECK-NEXT: sltu a2, a0, a3327; CHECK-NEXT: vmv1r.v v6, v7328; CHECK-NEXT: addi a2, a2, -1329; CHECK-NEXT: and a2, a2, a3330; CHECK-NEXT: vmv1r.v v0, v7331; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma332; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t333; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma334; CHECK-NEXT: vfabs.v v16, v24, v0.t335; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu336; CHECK-NEXT: vmflt.vf v6, v16, fa5, v0.t337; CHECK-NEXT: vmv1r.v v0, v6338; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma339; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t340; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t341; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu342; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t343; CHECK-NEXT: vmv1r.v v0, v7344; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma345; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t346; CHECK-NEXT: bltu a0, a1, .LBB11_2347; CHECK-NEXT: # %bb.1:348; CHECK-NEXT: mv a0, a1349; CHECK-NEXT: .LBB11_2:350; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma351; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8352; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma353; CHECK-NEXT: vfabs.v v24, v16354; CHECK-NEXT: vmflt.vf v0, v24, fa5355; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t356; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t357; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu358; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t359; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma360; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16361; CHECK-NEXT: ret362 %v = call <vscale x 32 x bfloat> @llvm.vp.rint.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)363 ret <vscale x 32 x bfloat> %v364}365 366define <vscale x 1 x half> @vp_rint_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {367; ZVFH-LABEL: vp_rint_nxv1f16:368; ZVFH: # %bb.0:369; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma370; ZVFH-NEXT: vfabs.v v9, v8, v0.t371; ZVFH-NEXT: li a0, 25372; ZVFH-NEXT: slli a0, a0, 10373; ZVFH-NEXT: fmv.h.x fa5, a0374; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu375; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t376; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma377; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t378; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t379; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu380; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t381; ZVFH-NEXT: ret382;383; ZVFHMIN-LABEL: vp_rint_nxv1f16:384; ZVFHMIN: # %bb.0:385; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma386; ZVFHMIN-NEXT: vmv1r.v v9, v0387; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t388; ZVFHMIN-NEXT: lui a0, 307200389; ZVFHMIN-NEXT: vmv1r.v v8, v0390; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma391; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t392; ZVFHMIN-NEXT: fmv.w.x fa5, a0393; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu394; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t395; ZVFHMIN-NEXT: vmv1r.v v0, v8396; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma397; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t398; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t399; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu400; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t401; ZVFHMIN-NEXT: vmv1r.v v0, v9402; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma403; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t404; ZVFHMIN-NEXT: ret405 %v = call <vscale x 1 x half> @llvm.vp.rint.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)406 ret <vscale x 1 x half> %v407}408 409define <vscale x 1 x half> @vp_rint_nxv1f16_unmasked(<vscale x 1 x half> %va, i32 zeroext %evl) {410; ZVFH-LABEL: vp_rint_nxv1f16_unmasked:411; ZVFH: # %bb.0:412; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma413; ZVFH-NEXT: vfabs.v v9, v8414; ZVFH-NEXT: li a0, 25415; ZVFH-NEXT: slli a0, a0, 10416; ZVFH-NEXT: fmv.h.x fa5, a0417; ZVFH-NEXT: vmflt.vf v0, v9, fa5418; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t419; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t420; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu421; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t422; ZVFH-NEXT: ret423;424; ZVFHMIN-LABEL: vp_rint_nxv1f16_unmasked:425; ZVFHMIN: # %bb.0:426; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma427; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8428; ZVFHMIN-NEXT: lui a0, 307200429; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma430; ZVFHMIN-NEXT: vfabs.v v8, v9431; ZVFHMIN-NEXT: fmv.w.x fa5, a0432; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5433; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t434; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t435; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu436; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t437; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma438; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9439; ZVFHMIN-NEXT: ret440 %v = call <vscale x 1 x half> @llvm.vp.rint.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)441 ret <vscale x 1 x half> %v442}443 444define <vscale x 2 x half> @vp_rint_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {445; ZVFH-LABEL: vp_rint_nxv2f16:446; ZVFH: # %bb.0:447; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma448; ZVFH-NEXT: vfabs.v v9, v8, v0.t449; ZVFH-NEXT: li a0, 25450; ZVFH-NEXT: slli a0, a0, 10451; ZVFH-NEXT: fmv.h.x fa5, a0452; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu453; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t454; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma455; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t456; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t457; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu458; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t459; ZVFH-NEXT: ret460;461; ZVFHMIN-LABEL: vp_rint_nxv2f16:462; ZVFHMIN: # %bb.0:463; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma464; ZVFHMIN-NEXT: vmv1r.v v9, v0465; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t466; ZVFHMIN-NEXT: lui a0, 307200467; ZVFHMIN-NEXT: vmv1r.v v8, v0468; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma469; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t470; ZVFHMIN-NEXT: fmv.w.x fa5, a0471; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu472; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t473; ZVFHMIN-NEXT: vmv.v.v v0, v8474; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma475; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t476; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t477; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu478; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t479; ZVFHMIN-NEXT: vmv1r.v v0, v9480; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma481; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t482; ZVFHMIN-NEXT: ret483 %v = call <vscale x 2 x half> @llvm.vp.rint.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)484 ret <vscale x 2 x half> %v485}486 487define <vscale x 2 x half> @vp_rint_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {488; ZVFH-LABEL: vp_rint_nxv2f16_unmasked:489; ZVFH: # %bb.0:490; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma491; ZVFH-NEXT: vfabs.v v9, v8492; ZVFH-NEXT: li a0, 25493; ZVFH-NEXT: slli a0, a0, 10494; ZVFH-NEXT: fmv.h.x fa5, a0495; ZVFH-NEXT: vmflt.vf v0, v9, fa5496; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t497; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t498; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu499; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t500; ZVFH-NEXT: ret501;502; ZVFHMIN-LABEL: vp_rint_nxv2f16_unmasked:503; ZVFHMIN: # %bb.0:504; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma505; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8506; ZVFHMIN-NEXT: lui a0, 307200507; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma508; ZVFHMIN-NEXT: vfabs.v v8, v9509; ZVFHMIN-NEXT: fmv.w.x fa5, a0510; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5511; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t512; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t513; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu514; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t515; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma516; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9517; ZVFHMIN-NEXT: ret518 %v = call <vscale x 2 x half> @llvm.vp.rint.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)519 ret <vscale x 2 x half> %v520}521 522define <vscale x 4 x half> @vp_rint_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {523; ZVFH-LABEL: vp_rint_nxv4f16:524; ZVFH: # %bb.0:525; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma526; ZVFH-NEXT: vfabs.v v9, v8, v0.t527; ZVFH-NEXT: li a0, 25528; ZVFH-NEXT: slli a0, a0, 10529; ZVFH-NEXT: fmv.h.x fa5, a0530; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu531; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t532; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma533; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t534; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t535; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu536; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t537; ZVFH-NEXT: ret538;539; ZVFHMIN-LABEL: vp_rint_nxv4f16:540; ZVFHMIN: # %bb.0:541; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma542; ZVFHMIN-NEXT: vmv1r.v v9, v0543; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t544; ZVFHMIN-NEXT: lui a0, 307200545; ZVFHMIN-NEXT: vmv1r.v v8, v0546; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma547; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t548; ZVFHMIN-NEXT: fmv.w.x fa5, a0549; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu550; ZVFHMIN-NEXT: vmflt.vf v8, v12, fa5, v0.t551; ZVFHMIN-NEXT: vmv1r.v v0, v8552; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma553; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t554; ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t555; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu556; ZVFHMIN-NEXT: vfsgnj.vv v10, v12, v10, v0.t557; ZVFHMIN-NEXT: vmv1r.v v0, v9558; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma559; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t560; ZVFHMIN-NEXT: ret561 %v = call <vscale x 4 x half> @llvm.vp.rint.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 %evl)562 ret <vscale x 4 x half> %v563}564 565define <vscale x 4 x half> @vp_rint_nxv4f16_unmasked(<vscale x 4 x half> %va, i32 zeroext %evl) {566; ZVFH-LABEL: vp_rint_nxv4f16_unmasked:567; ZVFH: # %bb.0:568; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma569; ZVFH-NEXT: vfabs.v v9, v8570; ZVFH-NEXT: li a0, 25571; ZVFH-NEXT: slli a0, a0, 10572; ZVFH-NEXT: fmv.h.x fa5, a0573; ZVFH-NEXT: vmflt.vf v0, v9, fa5574; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t575; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t576; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu577; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t578; ZVFH-NEXT: ret579;580; ZVFHMIN-LABEL: vp_rint_nxv4f16_unmasked:581; ZVFHMIN: # %bb.0:582; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma583; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8584; ZVFHMIN-NEXT: lui a0, 307200585; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma586; ZVFHMIN-NEXT: vfabs.v v8, v10587; ZVFHMIN-NEXT: fmv.w.x fa5, a0588; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5589; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t590; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t591; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu592; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t593; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma594; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10595; ZVFHMIN-NEXT: ret596 %v = call <vscale x 4 x half> @llvm.vp.rint.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)597 ret <vscale x 4 x half> %v598}599 600define <vscale x 8 x half> @vp_rint_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {601; ZVFH-LABEL: vp_rint_nxv8f16:602; ZVFH: # %bb.0:603; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma604; ZVFH-NEXT: vmv1r.v v10, v0605; ZVFH-NEXT: vfabs.v v12, v8, v0.t606; ZVFH-NEXT: li a0, 25607; ZVFH-NEXT: slli a0, a0, 10608; ZVFH-NEXT: fmv.h.x fa5, a0609; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu610; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t611; ZVFH-NEXT: vmv1r.v v0, v10612; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma613; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t614; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t615; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu616; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t617; ZVFH-NEXT: ret618;619; ZVFHMIN-LABEL: vp_rint_nxv8f16:620; ZVFHMIN: # %bb.0:621; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma622; ZVFHMIN-NEXT: vmv1r.v v10, v0623; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t624; ZVFHMIN-NEXT: lui a0, 307200625; ZVFHMIN-NEXT: vmv1r.v v8, v0626; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma627; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t628; ZVFHMIN-NEXT: fmv.w.x fa5, a0629; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu630; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t631; ZVFHMIN-NEXT: vmv1r.v v0, v8632; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma633; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t634; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t635; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu636; ZVFHMIN-NEXT: vfsgnj.vv v12, v16, v12, v0.t637; ZVFHMIN-NEXT: vmv1r.v v0, v10638; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma639; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t640; ZVFHMIN-NEXT: ret641 %v = call <vscale x 8 x half> @llvm.vp.rint.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 %evl)642 ret <vscale x 8 x half> %v643}644 645define <vscale x 8 x half> @vp_rint_nxv8f16_unmasked(<vscale x 8 x half> %va, i32 zeroext %evl) {646; ZVFH-LABEL: vp_rint_nxv8f16_unmasked:647; ZVFH: # %bb.0:648; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma649; ZVFH-NEXT: vfabs.v v10, v8650; ZVFH-NEXT: li a0, 25651; ZVFH-NEXT: slli a0, a0, 10652; ZVFH-NEXT: fmv.h.x fa5, a0653; ZVFH-NEXT: vmflt.vf v0, v10, fa5654; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t655; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t656; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu657; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t658; ZVFH-NEXT: ret659;660; ZVFHMIN-LABEL: vp_rint_nxv8f16_unmasked:661; ZVFHMIN: # %bb.0:662; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma663; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8664; ZVFHMIN-NEXT: lui a0, 307200665; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma666; ZVFHMIN-NEXT: vfabs.v v8, v12667; ZVFHMIN-NEXT: fmv.w.x fa5, a0668; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5669; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t670; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t671; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu672; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t673; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma674; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12675; ZVFHMIN-NEXT: ret676 %v = call <vscale x 8 x half> @llvm.vp.rint.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)677 ret <vscale x 8 x half> %v678}679 680define <vscale x 16 x half> @vp_rint_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {681; ZVFH-LABEL: vp_rint_nxv16f16:682; ZVFH: # %bb.0:683; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma684; ZVFH-NEXT: vmv1r.v v12, v0685; ZVFH-NEXT: vfabs.v v16, v8, v0.t686; ZVFH-NEXT: li a0, 25687; ZVFH-NEXT: slli a0, a0, 10688; ZVFH-NEXT: fmv.h.x fa5, a0689; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu690; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t691; ZVFH-NEXT: vmv1r.v v0, v12692; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma693; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t694; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t695; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu696; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t697; ZVFH-NEXT: ret698;699; ZVFHMIN-LABEL: vp_rint_nxv16f16:700; ZVFHMIN: # %bb.0:701; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma702; ZVFHMIN-NEXT: vmv1r.v v12, v0703; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t704; ZVFHMIN-NEXT: lui a0, 307200705; ZVFHMIN-NEXT: vmv1r.v v8, v0706; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma707; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t708; ZVFHMIN-NEXT: fmv.w.x fa5, a0709; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu710; ZVFHMIN-NEXT: vmflt.vf v8, v24, fa5, v0.t711; ZVFHMIN-NEXT: vmv1r.v v0, v8712; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma713; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t714; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t715; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu716; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t717; ZVFHMIN-NEXT: vmv1r.v v0, v12718; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma719; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t720; ZVFHMIN-NEXT: ret721 %v = call <vscale x 16 x half> @llvm.vp.rint.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 %evl)722 ret <vscale x 16 x half> %v723}724 725define <vscale x 16 x half> @vp_rint_nxv16f16_unmasked(<vscale x 16 x half> %va, i32 zeroext %evl) {726; ZVFH-LABEL: vp_rint_nxv16f16_unmasked:727; ZVFH: # %bb.0:728; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma729; ZVFH-NEXT: vfabs.v v12, v8730; ZVFH-NEXT: li a0, 25731; ZVFH-NEXT: slli a0, a0, 10732; ZVFH-NEXT: fmv.h.x fa5, a0733; ZVFH-NEXT: vmflt.vf v0, v12, fa5734; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t735; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t736; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu737; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t738; ZVFH-NEXT: ret739;740; ZVFHMIN-LABEL: vp_rint_nxv16f16_unmasked:741; ZVFHMIN: # %bb.0:742; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma743; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8744; ZVFHMIN-NEXT: lui a0, 307200745; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma746; ZVFHMIN-NEXT: vfabs.v v8, v16747; ZVFHMIN-NEXT: fmv.w.x fa5, a0748; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5749; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t750; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t751; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu752; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t753; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma754; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16755; ZVFHMIN-NEXT: ret756 %v = call <vscale x 16 x half> @llvm.vp.rint.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)757 ret <vscale x 16 x half> %v758}759 760define <vscale x 32 x half> @vp_rint_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {761; ZVFH-LABEL: vp_rint_nxv32f16:762; ZVFH: # %bb.0:763; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma764; ZVFH-NEXT: vmv1r.v v16, v0765; ZVFH-NEXT: vfabs.v v24, v8, v0.t766; ZVFH-NEXT: li a0, 25767; ZVFH-NEXT: slli a0, a0, 10768; ZVFH-NEXT: fmv.h.x fa5, a0769; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu770; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t771; ZVFH-NEXT: vmv1r.v v0, v16772; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, ma773; ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t774; ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t775; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu776; ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t777; ZVFH-NEXT: ret778;779; ZVFHMIN-LABEL: vp_rint_nxv32f16:780; ZVFHMIN: # %bb.0:781; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma782; ZVFHMIN-NEXT: vmv1r.v v7, v0783; ZVFHMIN-NEXT: csrr a2, vlenb784; ZVFHMIN-NEXT: lui a3, 307200785; ZVFHMIN-NEXT: slli a1, a2, 1786; ZVFHMIN-NEXT: srli a2, a2, 2787; ZVFHMIN-NEXT: fmv.w.x fa5, a3788; ZVFHMIN-NEXT: sub a3, a0, a1789; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2790; ZVFHMIN-NEXT: sltu a2, a0, a3791; ZVFHMIN-NEXT: vmv1r.v v5, v6792; ZVFHMIN-NEXT: addi a2, a2, -1793; ZVFHMIN-NEXT: and a2, a2, a3794; ZVFHMIN-NEXT: vmv1r.v v0, v6795; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma796; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t797; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma798; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t799; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu800; ZVFHMIN-NEXT: vmflt.vf v5, v16, fa5, v0.t801; ZVFHMIN-NEXT: vmv1r.v v0, v5802; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma803; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t804; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t805; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu806; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t807; ZVFHMIN-NEXT: vmv1r.v v0, v6808; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma809; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t810; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2811; ZVFHMIN-NEXT: # %bb.1:812; ZVFHMIN-NEXT: mv a0, a1813; ZVFHMIN-NEXT: .LBB22_2:814; ZVFHMIN-NEXT: vmv1r.v v0, v7815; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma816; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t817; ZVFHMIN-NEXT: vmv1r.v v8, v7818; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma819; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t820; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu821; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t822; ZVFHMIN-NEXT: vmv1r.v v0, v8823; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma824; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t825; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t826; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu827; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t828; ZVFHMIN-NEXT: vmv1r.v v0, v7829; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma830; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t831; ZVFHMIN-NEXT: ret832 %v = call <vscale x 32 x half> @llvm.vp.rint.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)833 ret <vscale x 32 x half> %v834}835 836define <vscale x 32 x half> @vp_rint_nxv32f16_unmasked(<vscale x 32 x half> %va, i32 zeroext %evl) {837; ZVFH-LABEL: vp_rint_nxv32f16_unmasked:838; ZVFH: # %bb.0:839; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma840; ZVFH-NEXT: vfabs.v v16, v8841; ZVFH-NEXT: li a0, 25842; ZVFH-NEXT: slli a0, a0, 10843; ZVFH-NEXT: fmv.h.x fa5, a0844; ZVFH-NEXT: vmflt.vf v0, v16, fa5845; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t846; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t847; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu848; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t849; ZVFH-NEXT: ret850;851; ZVFHMIN-LABEL: vp_rint_nxv32f16_unmasked:852; ZVFHMIN: # %bb.0:853; ZVFHMIN-NEXT: csrr a2, vlenb854; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma855; ZVFHMIN-NEXT: vmset.m v16856; ZVFHMIN-NEXT: lui a3, 307200857; ZVFHMIN-NEXT: slli a1, a2, 1858; ZVFHMIN-NEXT: srli a2, a2, 2859; ZVFHMIN-NEXT: fmv.w.x fa5, a3860; ZVFHMIN-NEXT: sub a3, a0, a1861; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma862; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a2863; ZVFHMIN-NEXT: sltu a2, a0, a3864; ZVFHMIN-NEXT: vmv1r.v v6, v7865; ZVFHMIN-NEXT: addi a2, a2, -1866; ZVFHMIN-NEXT: and a2, a2, a3867; ZVFHMIN-NEXT: vmv1r.v v0, v7868; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma869; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t870; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma871; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t872; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu873; ZVFHMIN-NEXT: vmflt.vf v6, v16, fa5, v0.t874; ZVFHMIN-NEXT: vmv1r.v v0, v6875; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma876; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t877; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t878; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu879; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t880; ZVFHMIN-NEXT: vmv1r.v v0, v7881; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma882; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t883; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2884; ZVFHMIN-NEXT: # %bb.1:885; ZVFHMIN-NEXT: mv a0, a1886; ZVFHMIN-NEXT: .LBB23_2:887; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma888; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8889; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma890; ZVFHMIN-NEXT: vfabs.v v24, v16891; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5892; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t893; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t894; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu895; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t896; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma897; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16898; ZVFHMIN-NEXT: ret899 %v = call <vscale x 32 x half> @llvm.vp.rint.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)900 ret <vscale x 32 x half> %v901}902 903define <vscale x 1 x float> @vp_rint_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {904; CHECK-LABEL: vp_rint_nxv1f32:905; CHECK: # %bb.0:906; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma907; CHECK-NEXT: vfabs.v v9, v8, v0.t908; CHECK-NEXT: lui a0, 307200909; CHECK-NEXT: fmv.w.x fa5, a0910; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu911; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t912; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma913; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t914; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t915; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu916; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t917; CHECK-NEXT: ret918 %v = call <vscale x 1 x float> @llvm.vp.rint.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 %evl)919 ret <vscale x 1 x float> %v920}921 922define <vscale x 1 x float> @vp_rint_nxv1f32_unmasked(<vscale x 1 x float> %va, i32 zeroext %evl) {923; CHECK-LABEL: vp_rint_nxv1f32_unmasked:924; CHECK: # %bb.0:925; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma926; CHECK-NEXT: vfabs.v v9, v8927; CHECK-NEXT: lui a0, 307200928; CHECK-NEXT: fmv.w.x fa5, a0929; CHECK-NEXT: vmflt.vf v0, v9, fa5930; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t931; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t932; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu933; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t934; CHECK-NEXT: ret935 %v = call <vscale x 1 x float> @llvm.vp.rint.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)936 ret <vscale x 1 x float> %v937}938 939define <vscale x 2 x float> @vp_rint_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {940; CHECK-LABEL: vp_rint_nxv2f32:941; CHECK: # %bb.0:942; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma943; CHECK-NEXT: vfabs.v v9, v8, v0.t944; CHECK-NEXT: lui a0, 307200945; CHECK-NEXT: fmv.w.x fa5, a0946; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu947; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t948; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma949; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t950; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t951; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu952; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t953; CHECK-NEXT: ret954 %v = call <vscale x 2 x float> @llvm.vp.rint.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)955 ret <vscale x 2 x float> %v956}957 958define <vscale x 2 x float> @vp_rint_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {959; CHECK-LABEL: vp_rint_nxv2f32_unmasked:960; CHECK: # %bb.0:961; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma962; CHECK-NEXT: vfabs.v v9, v8963; CHECK-NEXT: lui a0, 307200964; CHECK-NEXT: fmv.w.x fa5, a0965; CHECK-NEXT: vmflt.vf v0, v9, fa5966; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t967; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t968; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu969; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t970; CHECK-NEXT: ret971 %v = call <vscale x 2 x float> @llvm.vp.rint.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)972 ret <vscale x 2 x float> %v973}974 975define <vscale x 4 x float> @vp_rint_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {976; CHECK-LABEL: vp_rint_nxv4f32:977; CHECK: # %bb.0:978; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma979; CHECK-NEXT: vmv1r.v v10, v0980; CHECK-NEXT: vfabs.v v12, v8, v0.t981; CHECK-NEXT: lui a0, 307200982; CHECK-NEXT: fmv.w.x fa5, a0983; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu984; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t985; CHECK-NEXT: vmv1r.v v0, v10986; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma987; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t988; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t989; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu990; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t991; CHECK-NEXT: ret992 %v = call <vscale x 4 x float> @llvm.vp.rint.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 %evl)993 ret <vscale x 4 x float> %v994}995 996define <vscale x 4 x float> @vp_rint_nxv4f32_unmasked(<vscale x 4 x float> %va, i32 zeroext %evl) {997; CHECK-LABEL: vp_rint_nxv4f32_unmasked:998; CHECK: # %bb.0:999; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1000; CHECK-NEXT: vfabs.v v10, v81001; CHECK-NEXT: lui a0, 3072001002; CHECK-NEXT: fmv.w.x fa5, a01003; CHECK-NEXT: vmflt.vf v0, v10, fa51004; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t1005; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t1006; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu1007; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t1008; CHECK-NEXT: ret1009 %v = call <vscale x 4 x float> @llvm.vp.rint.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)1010 ret <vscale x 4 x float> %v1011}1012 1013define <vscale x 8 x float> @vp_rint_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1014; CHECK-LABEL: vp_rint_nxv8f32:1015; CHECK: # %bb.0:1016; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1017; CHECK-NEXT: vmv1r.v v12, v01018; CHECK-NEXT: vfabs.v v16, v8, v0.t1019; CHECK-NEXT: lui a0, 3072001020; CHECK-NEXT: fmv.w.x fa5, a01021; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu1022; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t1023; CHECK-NEXT: vmv1r.v v0, v121024; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1025; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t1026; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t1027; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu1028; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t1029; CHECK-NEXT: ret1030 %v = call <vscale x 8 x float> @llvm.vp.rint.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 %evl)1031 ret <vscale x 8 x float> %v1032}1033 1034define <vscale x 8 x float> @vp_rint_nxv8f32_unmasked(<vscale x 8 x float> %va, i32 zeroext %evl) {1035; CHECK-LABEL: vp_rint_nxv8f32_unmasked:1036; CHECK: # %bb.0:1037; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1038; CHECK-NEXT: vfabs.v v12, v81039; CHECK-NEXT: lui a0, 3072001040; CHECK-NEXT: fmv.w.x fa5, a01041; CHECK-NEXT: vmflt.vf v0, v12, fa51042; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t1043; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t1044; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu1045; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t1046; CHECK-NEXT: ret1047 %v = call <vscale x 8 x float> @llvm.vp.rint.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)1048 ret <vscale x 8 x float> %v1049}1050 1051define <vscale x 16 x float> @vp_rint_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1052; CHECK-LABEL: vp_rint_nxv16f32:1053; CHECK: # %bb.0:1054; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1055; CHECK-NEXT: vmv1r.v v16, v01056; CHECK-NEXT: vfabs.v v24, v8, v0.t1057; CHECK-NEXT: lui a0, 3072001058; CHECK-NEXT: fmv.w.x fa5, a01059; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu1060; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t1061; CHECK-NEXT: vmv1r.v v0, v161062; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma1063; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t1064; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t1065; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu1066; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t1067; CHECK-NEXT: ret1068 %v = call <vscale x 16 x float> @llvm.vp.rint.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 %evl)1069 ret <vscale x 16 x float> %v1070}1071 1072define <vscale x 16 x float> @vp_rint_nxv16f32_unmasked(<vscale x 16 x float> %va, i32 zeroext %evl) {1073; CHECK-LABEL: vp_rint_nxv16f32_unmasked:1074; CHECK: # %bb.0:1075; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1076; CHECK-NEXT: vfabs.v v16, v81077; CHECK-NEXT: lui a0, 3072001078; CHECK-NEXT: fmv.w.x fa5, a01079; CHECK-NEXT: vmflt.vf v0, v16, fa51080; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t1081; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t1082; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu1083; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t1084; CHECK-NEXT: ret1085 %v = call <vscale x 16 x float> @llvm.vp.rint.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)1086 ret <vscale x 16 x float> %v1087}1088 1089define <vscale x 1 x double> @vp_rint_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1090; RV32ZVFH-LABEL: vp_rint_nxv1f64:1091; RV32ZVFH: # %bb.0:1092; RV32ZVFH-NEXT: lui a1, %hi(.LCPI34_0)1093; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI34_0)(a1)1094; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1095; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t1096; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1097; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t1098; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma1099; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1100; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1101; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1102; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1103; RV32ZVFH-NEXT: ret1104;1105; RV64ZVFH-LABEL: vp_rint_nxv1f64:1106; RV64ZVFH: # %bb.0:1107; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1108; RV64ZVFH-NEXT: vfabs.v v9, v8, v0.t1109; RV64ZVFH-NEXT: li a0, 10751110; RV64ZVFH-NEXT: slli a0, a0, 521111; RV64ZVFH-NEXT: fmv.d.x fa5, a01112; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1113; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t1114; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma1115; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1116; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1117; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1118; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1119; RV64ZVFH-NEXT: ret1120;1121; RV32ZVFMIN-LABEL: vp_rint_nxv1f64:1122; RV32ZVFMIN: # %bb.0:1123; RV32ZVFMIN-NEXT: lui a1, %hi(.LCPI34_0)1124; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI34_0)(a1)1125; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma1126; RV32ZVFMIN-NEXT: vfabs.v v9, v8, v0.t1127; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1128; RV32ZVFMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t1129; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma1130; RV32ZVFMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t1131; RV32ZVFMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t1132; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1133; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t1134; RV32ZVFMIN-NEXT: ret1135;1136; RV64ZVFHMIN-LABEL: vp_rint_nxv1f64:1137; RV64ZVFHMIN: # %bb.0:1138; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma1139; RV64ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t1140; RV64ZVFHMIN-NEXT: li a0, 10751141; RV64ZVFHMIN-NEXT: slli a0, a0, 521142; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01143; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1144; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t1145; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma1146; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t1147; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t1148; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1149; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t1150; RV64ZVFHMIN-NEXT: ret1151 %v = call <vscale x 1 x double> @llvm.vp.rint.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 %evl)1152 ret <vscale x 1 x double> %v1153}1154 1155define <vscale x 1 x double> @vp_rint_nxv1f64_unmasked(<vscale x 1 x double> %va, i32 zeroext %evl) {1156; RV32ZVFH-LABEL: vp_rint_nxv1f64_unmasked:1157; RV32ZVFH: # %bb.0:1158; RV32ZVFH-NEXT: lui a1, %hi(.LCPI35_0)1159; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI35_0)(a1)1160; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1161; RV32ZVFH-NEXT: vfabs.v v9, v81162; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa51163; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1164; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1165; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1166; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1167; RV32ZVFH-NEXT: ret1168;1169; RV64ZVFH-LABEL: vp_rint_nxv1f64_unmasked:1170; RV64ZVFH: # %bb.0:1171; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1172; RV64ZVFH-NEXT: vfabs.v v9, v81173; RV64ZVFH-NEXT: li a0, 10751174; RV64ZVFH-NEXT: slli a0, a0, 521175; RV64ZVFH-NEXT: fmv.d.x fa5, a01176; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa51177; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1178; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1179; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1180; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1181; RV64ZVFH-NEXT: ret1182;1183; RV32ZVFMIN-LABEL: vp_rint_nxv1f64_unmasked:1184; RV32ZVFMIN: # %bb.0:1185; RV32ZVFMIN-NEXT: lui a1, %hi(.LCPI35_0)1186; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI35_0)(a1)1187; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma1188; RV32ZVFMIN-NEXT: vfabs.v v9, v81189; RV32ZVFMIN-NEXT: vmflt.vf v0, v9, fa51190; RV32ZVFMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t1191; RV32ZVFMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t1192; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1193; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t1194; RV32ZVFMIN-NEXT: ret1195;1196; RV64ZVFHMIN-LABEL: vp_rint_nxv1f64_unmasked:1197; RV64ZVFHMIN: # %bb.0:1198; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma1199; RV64ZVFHMIN-NEXT: vfabs.v v9, v81200; RV64ZVFHMIN-NEXT: li a0, 10751201; RV64ZVFHMIN-NEXT: slli a0, a0, 521202; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01203; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa51204; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t1205; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t1206; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1207; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t1208; RV64ZVFHMIN-NEXT: ret1209 %v = call <vscale x 1 x double> @llvm.vp.rint.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)1210 ret <vscale x 1 x double> %v1211}1212 1213define <vscale x 2 x double> @vp_rint_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1214; RV32ZVFH-LABEL: vp_rint_nxv2f64:1215; RV32ZVFH: # %bb.0:1216; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1217; RV32ZVFH-NEXT: vmv1r.v v10, v01218; RV32ZVFH-NEXT: lui a0, %hi(.LCPI36_0)1219; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI36_0)(a0)1220; RV32ZVFH-NEXT: vfabs.v v12, v8, v0.t1221; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1222; RV32ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t1223; RV32ZVFH-NEXT: vmv1r.v v0, v101224; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, ma1225; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1226; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1227; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1228; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1229; RV32ZVFH-NEXT: ret1230;1231; RV64ZVFH-LABEL: vp_rint_nxv2f64:1232; RV64ZVFH: # %bb.0:1233; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1234; RV64ZVFH-NEXT: vmv1r.v v10, v01235; RV64ZVFH-NEXT: vfabs.v v12, v8, v0.t1236; RV64ZVFH-NEXT: li a0, 10751237; RV64ZVFH-NEXT: slli a0, a0, 521238; RV64ZVFH-NEXT: fmv.d.x fa5, a01239; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1240; RV64ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t1241; RV64ZVFH-NEXT: vmv1r.v v0, v101242; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, ma1243; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1244; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1245; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1246; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1247; RV64ZVFH-NEXT: ret1248;1249; RV32ZVFMIN-LABEL: vp_rint_nxv2f64:1250; RV32ZVFMIN: # %bb.0:1251; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma1252; RV32ZVFMIN-NEXT: vmv1r.v v10, v01253; RV32ZVFMIN-NEXT: lui a0, %hi(.LCPI36_0)1254; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI36_0)(a0)1255; RV32ZVFMIN-NEXT: vfabs.v v12, v8, v0.t1256; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1257; RV32ZVFMIN-NEXT: vmflt.vf v10, v12, fa5, v0.t1258; RV32ZVFMIN-NEXT: vmv1r.v v0, v101259; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m2, ta, ma1260; RV32ZVFMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t1261; RV32ZVFMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t1262; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1263; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t1264; RV32ZVFMIN-NEXT: ret1265;1266; RV64ZVFHMIN-LABEL: vp_rint_nxv2f64:1267; RV64ZVFHMIN: # %bb.0:1268; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma1269; RV64ZVFHMIN-NEXT: vmv1r.v v10, v01270; RV64ZVFHMIN-NEXT: vfabs.v v12, v8, v0.t1271; RV64ZVFHMIN-NEXT: li a0, 10751272; RV64ZVFHMIN-NEXT: slli a0, a0, 521273; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01274; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1275; RV64ZVFHMIN-NEXT: vmflt.vf v10, v12, fa5, v0.t1276; RV64ZVFHMIN-NEXT: vmv1r.v v0, v101277; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, ma1278; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t1279; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t1280; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1281; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t1282; RV64ZVFHMIN-NEXT: ret1283 %v = call <vscale x 2 x double> @llvm.vp.rint.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)1284 ret <vscale x 2 x double> %v1285}1286 1287define <vscale x 2 x double> @vp_rint_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {1288; RV32ZVFH-LABEL: vp_rint_nxv2f64_unmasked:1289; RV32ZVFH: # %bb.0:1290; RV32ZVFH-NEXT: lui a1, %hi(.LCPI37_0)1291; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI37_0)(a1)1292; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1293; RV32ZVFH-NEXT: vfabs.v v10, v81294; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa51295; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t1296; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t1297; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1298; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t1299; RV32ZVFH-NEXT: ret1300;1301; RV64ZVFH-LABEL: vp_rint_nxv2f64_unmasked:1302; RV64ZVFH: # %bb.0:1303; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1304; RV64ZVFH-NEXT: vfabs.v v10, v81305; RV64ZVFH-NEXT: li a0, 10751306; RV64ZVFH-NEXT: slli a0, a0, 521307; RV64ZVFH-NEXT: fmv.d.x fa5, a01308; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa51309; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t1310; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t1311; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1312; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t1313; RV64ZVFH-NEXT: ret1314;1315; RV32ZVFMIN-LABEL: vp_rint_nxv2f64_unmasked:1316; RV32ZVFMIN: # %bb.0:1317; RV32ZVFMIN-NEXT: lui a1, %hi(.LCPI37_0)1318; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI37_0)(a1)1319; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma1320; RV32ZVFMIN-NEXT: vfabs.v v10, v81321; RV32ZVFMIN-NEXT: vmflt.vf v0, v10, fa51322; RV32ZVFMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t1323; RV32ZVFMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t1324; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1325; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t1326; RV32ZVFMIN-NEXT: ret1327;1328; RV64ZVFHMIN-LABEL: vp_rint_nxv2f64_unmasked:1329; RV64ZVFHMIN: # %bb.0:1330; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma1331; RV64ZVFHMIN-NEXT: vfabs.v v10, v81332; RV64ZVFHMIN-NEXT: li a0, 10751333; RV64ZVFHMIN-NEXT: slli a0, a0, 521334; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01335; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa51336; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t1337; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t1338; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1339; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t1340; RV64ZVFHMIN-NEXT: ret1341 %v = call <vscale x 2 x double> @llvm.vp.rint.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)1342 ret <vscale x 2 x double> %v1343}1344 1345define <vscale x 4 x double> @vp_rint_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1346; RV32ZVFH-LABEL: vp_rint_nxv4f64:1347; RV32ZVFH: # %bb.0:1348; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1349; RV32ZVFH-NEXT: vmv1r.v v12, v01350; RV32ZVFH-NEXT: lui a0, %hi(.LCPI38_0)1351; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI38_0)(a0)1352; RV32ZVFH-NEXT: vfabs.v v16, v8, v0.t1353; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1354; RV32ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t1355; RV32ZVFH-NEXT: vmv1r.v v0, v121356; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, ma1357; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1358; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1359; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1360; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1361; RV32ZVFH-NEXT: ret1362;1363; RV64ZVFH-LABEL: vp_rint_nxv4f64:1364; RV64ZVFH: # %bb.0:1365; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1366; RV64ZVFH-NEXT: vmv1r.v v12, v01367; RV64ZVFH-NEXT: vfabs.v v16, v8, v0.t1368; RV64ZVFH-NEXT: li a0, 10751369; RV64ZVFH-NEXT: slli a0, a0, 521370; RV64ZVFH-NEXT: fmv.d.x fa5, a01371; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1372; RV64ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t1373; RV64ZVFH-NEXT: vmv1r.v v0, v121374; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, ma1375; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1376; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1377; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1378; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1379; RV64ZVFH-NEXT: ret1380;1381; RV32ZVFMIN-LABEL: vp_rint_nxv4f64:1382; RV32ZVFMIN: # %bb.0:1383; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma1384; RV32ZVFMIN-NEXT: vmv1r.v v12, v01385; RV32ZVFMIN-NEXT: lui a0, %hi(.LCPI38_0)1386; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI38_0)(a0)1387; RV32ZVFMIN-NEXT: vfabs.v v16, v8, v0.t1388; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1389; RV32ZVFMIN-NEXT: vmflt.vf v12, v16, fa5, v0.t1390; RV32ZVFMIN-NEXT: vmv1r.v v0, v121391; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m4, ta, ma1392; RV32ZVFMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1393; RV32ZVFMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1394; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1395; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1396; RV32ZVFMIN-NEXT: ret1397;1398; RV64ZVFHMIN-LABEL: vp_rint_nxv4f64:1399; RV64ZVFHMIN: # %bb.0:1400; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma1401; RV64ZVFHMIN-NEXT: vmv1r.v v12, v01402; RV64ZVFHMIN-NEXT: vfabs.v v16, v8, v0.t1403; RV64ZVFHMIN-NEXT: li a0, 10751404; RV64ZVFHMIN-NEXT: slli a0, a0, 521405; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01406; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1407; RV64ZVFHMIN-NEXT: vmflt.vf v12, v16, fa5, v0.t1408; RV64ZVFHMIN-NEXT: vmv1r.v v0, v121409; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, ma1410; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1411; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1412; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1413; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1414; RV64ZVFHMIN-NEXT: ret1415 %v = call <vscale x 4 x double> @llvm.vp.rint.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 %evl)1416 ret <vscale x 4 x double> %v1417}1418 1419define <vscale x 4 x double> @vp_rint_nxv4f64_unmasked(<vscale x 4 x double> %va, i32 zeroext %evl) {1420; RV32ZVFH-LABEL: vp_rint_nxv4f64_unmasked:1421; RV32ZVFH: # %bb.0:1422; RV32ZVFH-NEXT: lui a1, %hi(.LCPI39_0)1423; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI39_0)(a1)1424; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1425; RV32ZVFH-NEXT: vfabs.v v12, v81426; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa51427; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1428; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1429; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1430; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1431; RV32ZVFH-NEXT: ret1432;1433; RV64ZVFH-LABEL: vp_rint_nxv4f64_unmasked:1434; RV64ZVFH: # %bb.0:1435; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1436; RV64ZVFH-NEXT: vfabs.v v12, v81437; RV64ZVFH-NEXT: li a0, 10751438; RV64ZVFH-NEXT: slli a0, a0, 521439; RV64ZVFH-NEXT: fmv.d.x fa5, a01440; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa51441; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1442; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1443; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1444; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1445; RV64ZVFH-NEXT: ret1446;1447; RV32ZVFMIN-LABEL: vp_rint_nxv4f64_unmasked:1448; RV32ZVFMIN: # %bb.0:1449; RV32ZVFMIN-NEXT: lui a1, %hi(.LCPI39_0)1450; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI39_0)(a1)1451; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma1452; RV32ZVFMIN-NEXT: vfabs.v v12, v81453; RV32ZVFMIN-NEXT: vmflt.vf v0, v12, fa51454; RV32ZVFMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t1455; RV32ZVFMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t1456; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1457; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t1458; RV32ZVFMIN-NEXT: ret1459;1460; RV64ZVFHMIN-LABEL: vp_rint_nxv4f64_unmasked:1461; RV64ZVFHMIN: # %bb.0:1462; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma1463; RV64ZVFHMIN-NEXT: vfabs.v v12, v81464; RV64ZVFHMIN-NEXT: li a0, 10751465; RV64ZVFHMIN-NEXT: slli a0, a0, 521466; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01467; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa51468; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t1469; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t1470; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1471; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t1472; RV64ZVFHMIN-NEXT: ret1473 %v = call <vscale x 4 x double> @llvm.vp.rint.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)1474 ret <vscale x 4 x double> %v1475}1476 1477define <vscale x 7 x double> @vp_rint_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {1478; RV32ZVFH-LABEL: vp_rint_nxv7f64:1479; RV32ZVFH: # %bb.0:1480; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1481; RV32ZVFH-NEXT: vmv1r.v v16, v01482; RV32ZVFH-NEXT: lui a0, %hi(.LCPI40_0)1483; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI40_0)(a0)1484; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t1485; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1486; RV32ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1487; RV32ZVFH-NEXT: vmv1r.v v0, v161488; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1489; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1490; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1491; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1492; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1493; RV32ZVFH-NEXT: ret1494;1495; RV64ZVFH-LABEL: vp_rint_nxv7f64:1496; RV64ZVFH: # %bb.0:1497; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1498; RV64ZVFH-NEXT: vmv1r.v v16, v01499; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t1500; RV64ZVFH-NEXT: li a0, 10751501; RV64ZVFH-NEXT: slli a0, a0, 521502; RV64ZVFH-NEXT: fmv.d.x fa5, a01503; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1504; RV64ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1505; RV64ZVFH-NEXT: vmv1r.v v0, v161506; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1507; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1508; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1509; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1510; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1511; RV64ZVFH-NEXT: ret1512;1513; RV32ZVFMIN-LABEL: vp_rint_nxv7f64:1514; RV32ZVFMIN: # %bb.0:1515; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1516; RV32ZVFMIN-NEXT: vmv1r.v v16, v01517; RV32ZVFMIN-NEXT: lui a0, %hi(.LCPI40_0)1518; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI40_0)(a0)1519; RV32ZVFMIN-NEXT: vfabs.v v24, v8, v0.t1520; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1521; RV32ZVFMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1522; RV32ZVFMIN-NEXT: vmv1r.v v0, v161523; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1524; RV32ZVFMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1525; RV32ZVFMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1526; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1527; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1528; RV32ZVFMIN-NEXT: ret1529;1530; RV64ZVFHMIN-LABEL: vp_rint_nxv7f64:1531; RV64ZVFHMIN: # %bb.0:1532; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1533; RV64ZVFHMIN-NEXT: vmv1r.v v16, v01534; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1535; RV64ZVFHMIN-NEXT: li a0, 10751536; RV64ZVFHMIN-NEXT: slli a0, a0, 521537; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01538; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1539; RV64ZVFHMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1540; RV64ZVFHMIN-NEXT: vmv1r.v v0, v161541; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1542; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1543; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1544; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1545; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1546; RV64ZVFHMIN-NEXT: ret1547 %v = call <vscale x 7 x double> @llvm.vp.rint.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)1548 ret <vscale x 7 x double> %v1549}1550 1551define <vscale x 7 x double> @vp_rint_nxv7f64_unmasked(<vscale x 7 x double> %va, i32 zeroext %evl) {1552; RV32ZVFH-LABEL: vp_rint_nxv7f64_unmasked:1553; RV32ZVFH: # %bb.0:1554; RV32ZVFH-NEXT: lui a1, %hi(.LCPI41_0)1555; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI41_0)(a1)1556; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1557; RV32ZVFH-NEXT: vfabs.v v16, v81558; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa51559; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1560; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1561; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1562; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1563; RV32ZVFH-NEXT: ret1564;1565; RV64ZVFH-LABEL: vp_rint_nxv7f64_unmasked:1566; RV64ZVFH: # %bb.0:1567; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1568; RV64ZVFH-NEXT: vfabs.v v16, v81569; RV64ZVFH-NEXT: li a0, 10751570; RV64ZVFH-NEXT: slli a0, a0, 521571; RV64ZVFH-NEXT: fmv.d.x fa5, a01572; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa51573; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1574; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1575; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1576; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1577; RV64ZVFH-NEXT: ret1578;1579; RV32ZVFMIN-LABEL: vp_rint_nxv7f64_unmasked:1580; RV32ZVFMIN: # %bb.0:1581; RV32ZVFMIN-NEXT: lui a1, %hi(.LCPI41_0)1582; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI41_0)(a1)1583; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1584; RV32ZVFMIN-NEXT: vfabs.v v16, v81585; RV32ZVFMIN-NEXT: vmflt.vf v0, v16, fa51586; RV32ZVFMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1587; RV32ZVFMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1588; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1589; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1590; RV32ZVFMIN-NEXT: ret1591;1592; RV64ZVFHMIN-LABEL: vp_rint_nxv7f64_unmasked:1593; RV64ZVFHMIN: # %bb.0:1594; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1595; RV64ZVFHMIN-NEXT: vfabs.v v16, v81596; RV64ZVFHMIN-NEXT: li a0, 10751597; RV64ZVFHMIN-NEXT: slli a0, a0, 521598; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01599; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa51600; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1601; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1602; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1603; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1604; RV64ZVFHMIN-NEXT: ret1605 %v = call <vscale x 7 x double> @llvm.vp.rint.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)1606 ret <vscale x 7 x double> %v1607}1608 1609define <vscale x 8 x double> @vp_rint_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1610; RV32ZVFH-LABEL: vp_rint_nxv8f64:1611; RV32ZVFH: # %bb.0:1612; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1613; RV32ZVFH-NEXT: vmv1r.v v16, v01614; RV32ZVFH-NEXT: lui a0, %hi(.LCPI42_0)1615; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI42_0)(a0)1616; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t1617; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1618; RV32ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1619; RV32ZVFH-NEXT: vmv1r.v v0, v161620; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1621; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1622; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1623; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1624; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1625; RV32ZVFH-NEXT: ret1626;1627; RV64ZVFH-LABEL: vp_rint_nxv8f64:1628; RV64ZVFH: # %bb.0:1629; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1630; RV64ZVFH-NEXT: vmv1r.v v16, v01631; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t1632; RV64ZVFH-NEXT: li a0, 10751633; RV64ZVFH-NEXT: slli a0, a0, 521634; RV64ZVFH-NEXT: fmv.d.x fa5, a01635; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1636; RV64ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1637; RV64ZVFH-NEXT: vmv1r.v v0, v161638; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1639; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1640; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1641; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1642; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1643; RV64ZVFH-NEXT: ret1644;1645; RV32ZVFMIN-LABEL: vp_rint_nxv8f64:1646; RV32ZVFMIN: # %bb.0:1647; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1648; RV32ZVFMIN-NEXT: vmv1r.v v16, v01649; RV32ZVFMIN-NEXT: lui a0, %hi(.LCPI42_0)1650; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI42_0)(a0)1651; RV32ZVFMIN-NEXT: vfabs.v v24, v8, v0.t1652; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1653; RV32ZVFMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1654; RV32ZVFMIN-NEXT: vmv1r.v v0, v161655; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1656; RV32ZVFMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1657; RV32ZVFMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1658; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1659; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1660; RV32ZVFMIN-NEXT: ret1661;1662; RV64ZVFHMIN-LABEL: vp_rint_nxv8f64:1663; RV64ZVFHMIN: # %bb.0:1664; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1665; RV64ZVFHMIN-NEXT: vmv1r.v v16, v01666; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1667; RV64ZVFHMIN-NEXT: li a0, 10751668; RV64ZVFHMIN-NEXT: slli a0, a0, 521669; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01670; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1671; RV64ZVFHMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1672; RV64ZVFHMIN-NEXT: vmv1r.v v0, v161673; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1674; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1675; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1676; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1677; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1678; RV64ZVFHMIN-NEXT: ret1679 %v = call <vscale x 8 x double> @llvm.vp.rint.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)1680 ret <vscale x 8 x double> %v1681}1682 1683define <vscale x 8 x double> @vp_rint_nxv8f64_unmasked(<vscale x 8 x double> %va, i32 zeroext %evl) {1684; RV32ZVFH-LABEL: vp_rint_nxv8f64_unmasked:1685; RV32ZVFH: # %bb.0:1686; RV32ZVFH-NEXT: lui a1, %hi(.LCPI43_0)1687; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI43_0)(a1)1688; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1689; RV32ZVFH-NEXT: vfabs.v v16, v81690; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa51691; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1692; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1693; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1694; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1695; RV32ZVFH-NEXT: ret1696;1697; RV64ZVFH-LABEL: vp_rint_nxv8f64_unmasked:1698; RV64ZVFH: # %bb.0:1699; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1700; RV64ZVFH-NEXT: vfabs.v v16, v81701; RV64ZVFH-NEXT: li a0, 10751702; RV64ZVFH-NEXT: slli a0, a0, 521703; RV64ZVFH-NEXT: fmv.d.x fa5, a01704; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa51705; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1706; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1707; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1708; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1709; RV64ZVFH-NEXT: ret1710;1711; RV32ZVFMIN-LABEL: vp_rint_nxv8f64_unmasked:1712; RV32ZVFMIN: # %bb.0:1713; RV32ZVFMIN-NEXT: lui a1, %hi(.LCPI43_0)1714; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI43_0)(a1)1715; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1716; RV32ZVFMIN-NEXT: vfabs.v v16, v81717; RV32ZVFMIN-NEXT: vmflt.vf v0, v16, fa51718; RV32ZVFMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1719; RV32ZVFMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1720; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1721; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1722; RV32ZVFMIN-NEXT: ret1723;1724; RV64ZVFHMIN-LABEL: vp_rint_nxv8f64_unmasked:1725; RV64ZVFHMIN: # %bb.0:1726; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1727; RV64ZVFHMIN-NEXT: vfabs.v v16, v81728; RV64ZVFHMIN-NEXT: li a0, 10751729; RV64ZVFHMIN-NEXT: slli a0, a0, 521730; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01731; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa51732; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1733; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1734; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1735; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1736; RV64ZVFHMIN-NEXT: ret1737 %v = call <vscale x 8 x double> @llvm.vp.rint.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)1738 ret <vscale x 8 x double> %v1739}1740 1741; Test splitting.1742 1743define <vscale x 16 x double> @vp_rint_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1744; RV32ZVFH-LABEL: vp_rint_nxv16f64:1745; RV32ZVFH: # %bb.0:1746; RV32ZVFH-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1747; RV32ZVFH-NEXT: vmv1r.v v7, v01748; RV32ZVFH-NEXT: csrr a1, vlenb1749; RV32ZVFH-NEXT: lui a2, %hi(.LCPI44_0)1750; RV32ZVFH-NEXT: srli a3, a1, 31751; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI44_0)(a2)1752; RV32ZVFH-NEXT: sub a2, a0, a11753; RV32ZVFH-NEXT: vslidedown.vx v6, v0, a31754; RV32ZVFH-NEXT: sltu a3, a0, a21755; RV32ZVFH-NEXT: addi a3, a3, -11756; RV32ZVFH-NEXT: and a2, a3, a21757; RV32ZVFH-NEXT: vmv1r.v v0, v61758; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma1759; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t1760; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1761; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t1762; RV32ZVFH-NEXT: vmv1r.v v0, v61763; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1764; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1765; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1766; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1767; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1768; RV32ZVFH-NEXT: bltu a0, a1, .LBB44_21769; RV32ZVFH-NEXT: # %bb.1:1770; RV32ZVFH-NEXT: mv a0, a11771; RV32ZVFH-NEXT: .LBB44_2:1772; RV32ZVFH-NEXT: vmv1r.v v0, v71773; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1774; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t1775; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1776; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t1777; RV32ZVFH-NEXT: vmv1r.v v0, v71778; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1779; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1780; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1781; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1782; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1783; RV32ZVFH-NEXT: ret1784;1785; RV64ZVFH-LABEL: vp_rint_nxv16f64:1786; RV64ZVFH: # %bb.0:1787; RV64ZVFH-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1788; RV64ZVFH-NEXT: vmv1r.v v7, v01789; RV64ZVFH-NEXT: csrr a1, vlenb1790; RV64ZVFH-NEXT: li a2, 10751791; RV64ZVFH-NEXT: srli a3, a1, 31792; RV64ZVFH-NEXT: vslidedown.vx v6, v0, a31793; RV64ZVFH-NEXT: sub a3, a0, a11794; RV64ZVFH-NEXT: slli a2, a2, 521795; RV64ZVFH-NEXT: fmv.d.x fa5, a21796; RV64ZVFH-NEXT: sltu a2, a0, a31797; RV64ZVFH-NEXT: addi a2, a2, -11798; RV64ZVFH-NEXT: and a2, a2, a31799; RV64ZVFH-NEXT: vmv1r.v v0, v61800; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma1801; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t1802; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1803; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t1804; RV64ZVFH-NEXT: vmv1r.v v0, v61805; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1806; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1807; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1808; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1809; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1810; RV64ZVFH-NEXT: bltu a0, a1, .LBB44_21811; RV64ZVFH-NEXT: # %bb.1:1812; RV64ZVFH-NEXT: mv a0, a11813; RV64ZVFH-NEXT: .LBB44_2:1814; RV64ZVFH-NEXT: vmv1r.v v0, v71815; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1816; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t1817; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1818; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t1819; RV64ZVFH-NEXT: vmv1r.v v0, v71820; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1821; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1822; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1823; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1824; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1825; RV64ZVFH-NEXT: ret1826;1827; RV32ZVFMIN-LABEL: vp_rint_nxv16f64:1828; RV32ZVFMIN: # %bb.0:1829; RV32ZVFMIN-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1830; RV32ZVFMIN-NEXT: vmv1r.v v7, v01831; RV32ZVFMIN-NEXT: csrr a1, vlenb1832; RV32ZVFMIN-NEXT: lui a2, %hi(.LCPI44_0)1833; RV32ZVFMIN-NEXT: srli a3, a1, 31834; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI44_0)(a2)1835; RV32ZVFMIN-NEXT: sub a2, a0, a11836; RV32ZVFMIN-NEXT: vslidedown.vx v6, v0, a31837; RV32ZVFMIN-NEXT: sltu a3, a0, a21838; RV32ZVFMIN-NEXT: addi a3, a3, -11839; RV32ZVFMIN-NEXT: and a2, a3, a21840; RV32ZVFMIN-NEXT: vmv1r.v v0, v61841; RV32ZVFMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma1842; RV32ZVFMIN-NEXT: vfabs.v v24, v16, v0.t1843; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1844; RV32ZVFMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t1845; RV32ZVFMIN-NEXT: vmv1r.v v0, v61846; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1847; RV32ZVFMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t1848; RV32ZVFMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1849; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1850; RV32ZVFMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t1851; RV32ZVFMIN-NEXT: bltu a0, a1, .LBB44_21852; RV32ZVFMIN-NEXT: # %bb.1:1853; RV32ZVFMIN-NEXT: mv a0, a11854; RV32ZVFMIN-NEXT: .LBB44_2:1855; RV32ZVFMIN-NEXT: vmv1r.v v0, v71856; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1857; RV32ZVFMIN-NEXT: vfabs.v v24, v8, v0.t1858; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1859; RV32ZVFMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t1860; RV32ZVFMIN-NEXT: vmv1r.v v0, v71861; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1862; RV32ZVFMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1863; RV32ZVFMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1864; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1865; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1866; RV32ZVFMIN-NEXT: ret1867;1868; RV64ZVFHMIN-LABEL: vp_rint_nxv16f64:1869; RV64ZVFHMIN: # %bb.0:1870; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1871; RV64ZVFHMIN-NEXT: vmv1r.v v7, v01872; RV64ZVFHMIN-NEXT: csrr a1, vlenb1873; RV64ZVFHMIN-NEXT: li a2, 10751874; RV64ZVFHMIN-NEXT: srli a3, a1, 31875; RV64ZVFHMIN-NEXT: vslidedown.vx v6, v0, a31876; RV64ZVFHMIN-NEXT: sub a3, a0, a11877; RV64ZVFHMIN-NEXT: slli a2, a2, 521878; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a21879; RV64ZVFHMIN-NEXT: sltu a2, a0, a31880; RV64ZVFHMIN-NEXT: addi a2, a2, -11881; RV64ZVFHMIN-NEXT: and a2, a2, a31882; RV64ZVFHMIN-NEXT: vmv1r.v v0, v61883; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma1884; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t1885; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1886; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t1887; RV64ZVFHMIN-NEXT: vmv1r.v v0, v61888; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1889; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t1890; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1891; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1892; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t1893; RV64ZVFHMIN-NEXT: bltu a0, a1, .LBB44_21894; RV64ZVFHMIN-NEXT: # %bb.1:1895; RV64ZVFHMIN-NEXT: mv a0, a11896; RV64ZVFHMIN-NEXT: .LBB44_2:1897; RV64ZVFHMIN-NEXT: vmv1r.v v0, v71898; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1899; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1900; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1901; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t1902; RV64ZVFHMIN-NEXT: vmv1r.v v0, v71903; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1904; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1905; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1906; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1907; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1908; RV64ZVFHMIN-NEXT: ret1909 %v = call <vscale x 16 x double> @llvm.vp.rint.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)1910 ret <vscale x 16 x double> %v1911}1912 1913define <vscale x 16 x double> @vp_rint_nxv16f64_unmasked(<vscale x 16 x double> %va, i32 zeroext %evl) {1914; RV32ZVFH-LABEL: vp_rint_nxv16f64_unmasked:1915; RV32ZVFH: # %bb.0:1916; RV32ZVFH-NEXT: csrr a1, vlenb1917; RV32ZVFH-NEXT: lui a2, %hi(.LCPI45_0)1918; RV32ZVFH-NEXT: sub a3, a0, a11919; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI45_0)(a2)1920; RV32ZVFH-NEXT: sltu a2, a0, a31921; RV32ZVFH-NEXT: addi a2, a2, -11922; RV32ZVFH-NEXT: and a2, a2, a31923; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma1924; RV32ZVFH-NEXT: vfabs.v v24, v161925; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa51926; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1927; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1928; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1929; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1930; RV32ZVFH-NEXT: bltu a0, a1, .LBB45_21931; RV32ZVFH-NEXT: # %bb.1:1932; RV32ZVFH-NEXT: mv a0, a11933; RV32ZVFH-NEXT: .LBB45_2:1934; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1935; RV32ZVFH-NEXT: vfabs.v v24, v81936; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa51937; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1938; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1939; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1940; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1941; RV32ZVFH-NEXT: ret1942;1943; RV64ZVFH-LABEL: vp_rint_nxv16f64_unmasked:1944; RV64ZVFH: # %bb.0:1945; RV64ZVFH-NEXT: csrr a1, vlenb1946; RV64ZVFH-NEXT: li a2, 10751947; RV64ZVFH-NEXT: sub a3, a0, a11948; RV64ZVFH-NEXT: slli a2, a2, 521949; RV64ZVFH-NEXT: fmv.d.x fa5, a21950; RV64ZVFH-NEXT: sltu a2, a0, a31951; RV64ZVFH-NEXT: addi a2, a2, -11952; RV64ZVFH-NEXT: and a2, a2, a31953; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma1954; RV64ZVFH-NEXT: vfabs.v v24, v161955; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa51956; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1957; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1958; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1959; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1960; RV64ZVFH-NEXT: bltu a0, a1, .LBB45_21961; RV64ZVFH-NEXT: # %bb.1:1962; RV64ZVFH-NEXT: mv a0, a11963; RV64ZVFH-NEXT: .LBB45_2:1964; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1965; RV64ZVFH-NEXT: vfabs.v v24, v81966; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa51967; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1968; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1969; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1970; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1971; RV64ZVFH-NEXT: ret1972;1973; RV32ZVFMIN-LABEL: vp_rint_nxv16f64_unmasked:1974; RV32ZVFMIN: # %bb.0:1975; RV32ZVFMIN-NEXT: csrr a1, vlenb1976; RV32ZVFMIN-NEXT: lui a2, %hi(.LCPI45_0)1977; RV32ZVFMIN-NEXT: sub a3, a0, a11978; RV32ZVFMIN-NEXT: fld fa5, %lo(.LCPI45_0)(a2)1979; RV32ZVFMIN-NEXT: sltu a2, a0, a31980; RV32ZVFMIN-NEXT: addi a2, a2, -11981; RV32ZVFMIN-NEXT: and a2, a2, a31982; RV32ZVFMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma1983; RV32ZVFMIN-NEXT: vfabs.v v24, v161984; RV32ZVFMIN-NEXT: vmflt.vf v0, v24, fa51985; RV32ZVFMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t1986; RV32ZVFMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1987; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1988; RV32ZVFMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t1989; RV32ZVFMIN-NEXT: bltu a0, a1, .LBB45_21990; RV32ZVFMIN-NEXT: # %bb.1:1991; RV32ZVFMIN-NEXT: mv a0, a11992; RV32ZVFMIN-NEXT: .LBB45_2:1993; RV32ZVFMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1994; RV32ZVFMIN-NEXT: vfabs.v v24, v81995; RV32ZVFMIN-NEXT: vmflt.vf v0, v24, fa51996; RV32ZVFMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1997; RV32ZVFMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1998; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1999; RV32ZVFMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t2000; RV32ZVFMIN-NEXT: ret2001;2002; RV64ZVFHMIN-LABEL: vp_rint_nxv16f64_unmasked:2003; RV64ZVFHMIN: # %bb.0:2004; RV64ZVFHMIN-NEXT: csrr a1, vlenb2005; RV64ZVFHMIN-NEXT: li a2, 10752006; RV64ZVFHMIN-NEXT: sub a3, a0, a12007; RV64ZVFHMIN-NEXT: slli a2, a2, 522008; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a22009; RV64ZVFHMIN-NEXT: sltu a2, a0, a32010; RV64ZVFHMIN-NEXT: addi a2, a2, -12011; RV64ZVFHMIN-NEXT: and a2, a2, a32012; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma2013; RV64ZVFHMIN-NEXT: vfabs.v v24, v162014; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa52015; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t2016; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t2017; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2018; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t2019; RV64ZVFHMIN-NEXT: bltu a0, a1, .LBB45_22020; RV64ZVFHMIN-NEXT: # %bb.1:2021; RV64ZVFHMIN-NEXT: mv a0, a12022; RV64ZVFHMIN-NEXT: .LBB45_2:2023; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma2024; RV64ZVFHMIN-NEXT: vfabs.v v24, v82025; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa52026; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t2027; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t2028; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2029; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t2030; RV64ZVFHMIN-NEXT: ret2031 %v = call <vscale x 16 x double> @llvm.vp.rint.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)2032 ret <vscale x 16 x double> %v2033}2034