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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH,RV32ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH,RV64ZVFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN14 15define <vscale x 1 x bfloat> @vp_roundeven_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {16; CHECK-LABEL: vp_roundeven_nxv1bf16:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma19; CHECK-NEXT: vmv1r.v v9, v020; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t21; CHECK-NEXT: lui a0, 30720022; CHECK-NEXT: vmv1r.v v8, v023; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma24; CHECK-NEXT: vfabs.v v11, v10, v0.t25; CHECK-NEXT: fmv.w.x fa5, a026; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu27; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t28; CHECK-NEXT: fsrmi a0, 029; CHECK-NEXT: vmv1r.v v0, v830; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma31; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t32; CHECK-NEXT: fsrm a033; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t34; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu35; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t36; CHECK-NEXT: vmv1r.v v0, v937; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma38; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t39; CHECK-NEXT: ret40 %v = call <vscale x 1 x bfloat> @llvm.vp.roundeven.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)41 ret <vscale x 1 x bfloat> %v42}43 44define <vscale x 1 x bfloat> @vp_roundeven_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, i32 zeroext %evl) {45; CHECK-LABEL: vp_roundeven_nxv1bf16_unmasked:46; CHECK: # %bb.0:47; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma48; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v849; CHECK-NEXT: lui a0, 30720050; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma51; CHECK-NEXT: vfabs.v v8, v952; CHECK-NEXT: fmv.w.x fa5, a053; CHECK-NEXT: vmflt.vf v0, v8, fa554; CHECK-NEXT: fsrmi a0, 055; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t56; CHECK-NEXT: fsrm a057; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t58; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu59; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t60; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma61; CHECK-NEXT: vfncvtbf16.f.f.w v8, v962; CHECK-NEXT: ret63 %v = call <vscale x 1 x bfloat> @llvm.vp.roundeven.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)64 ret <vscale x 1 x bfloat> %v65}66 67define <vscale x 2 x bfloat> @vp_roundeven_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {68; CHECK-LABEL: vp_roundeven_nxv2bf16:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma71; CHECK-NEXT: vmv1r.v v9, v072; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t73; CHECK-NEXT: lui a0, 30720074; CHECK-NEXT: vmv1r.v v8, v075; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma76; CHECK-NEXT: vfabs.v v11, v10, v0.t77; CHECK-NEXT: fmv.w.x fa5, a078; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu79; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t80; CHECK-NEXT: fsrmi a0, 081; CHECK-NEXT: vmv.v.v v0, v882; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma83; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t84; CHECK-NEXT: fsrm a085; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t86; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu87; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t88; CHECK-NEXT: vmv1r.v v0, v989; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma90; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t91; CHECK-NEXT: ret92 %v = call <vscale x 2 x bfloat> @llvm.vp.roundeven.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)93 ret <vscale x 2 x bfloat> %v94}95 96define <vscale x 2 x bfloat> @vp_roundeven_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, i32 zeroext %evl) {97; CHECK-LABEL: vp_roundeven_nxv2bf16_unmasked:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma100; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8101; CHECK-NEXT: lui a0, 307200102; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma103; CHECK-NEXT: vfabs.v v8, v9104; CHECK-NEXT: fmv.w.x fa5, a0105; CHECK-NEXT: vmflt.vf v0, v8, fa5106; CHECK-NEXT: fsrmi a0, 0107; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t108; CHECK-NEXT: fsrm a0109; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t110; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu111; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t112; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma113; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9114; CHECK-NEXT: ret115 %v = call <vscale x 2 x bfloat> @llvm.vp.roundeven.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)116 ret <vscale x 2 x bfloat> %v117}118 119define <vscale x 4 x bfloat> @vp_roundeven_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {120; CHECK-LABEL: vp_roundeven_nxv4bf16:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma123; CHECK-NEXT: vmv1r.v v9, v0124; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t125; CHECK-NEXT: lui a0, 307200126; CHECK-NEXT: vmv1r.v v8, v0127; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma128; CHECK-NEXT: vfabs.v v12, v10, v0.t129; CHECK-NEXT: fmv.w.x fa5, a0130; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu131; CHECK-NEXT: vmflt.vf v8, v12, fa5, v0.t132; CHECK-NEXT: fsrmi a0, 0133; CHECK-NEXT: vmv1r.v v0, v8134; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma135; CHECK-NEXT: vfcvt.x.f.v v12, v10, v0.t136; CHECK-NEXT: fsrm a0137; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t138; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu139; CHECK-NEXT: vfsgnj.vv v10, v12, v10, v0.t140; CHECK-NEXT: vmv1r.v v0, v9141; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma142; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t143; CHECK-NEXT: ret144 %v = call <vscale x 4 x bfloat> @llvm.vp.roundeven.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 %evl)145 ret <vscale x 4 x bfloat> %v146}147 148define <vscale x 4 x bfloat> @vp_roundeven_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, i32 zeroext %evl) {149; CHECK-LABEL: vp_roundeven_nxv4bf16_unmasked:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma152; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8153; CHECK-NEXT: lui a0, 307200154; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma155; CHECK-NEXT: vfabs.v v8, v10156; CHECK-NEXT: fmv.w.x fa5, a0157; CHECK-NEXT: vmflt.vf v0, v8, fa5158; CHECK-NEXT: fsrmi a0, 0159; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t160; CHECK-NEXT: fsrm a0161; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t162; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu163; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t164; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma165; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10166; CHECK-NEXT: ret167 %v = call <vscale x 4 x bfloat> @llvm.vp.roundeven.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)168 ret <vscale x 4 x bfloat> %v169}170 171define <vscale x 8 x bfloat> @vp_roundeven_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {172; CHECK-LABEL: vp_roundeven_nxv8bf16:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma175; CHECK-NEXT: vmv1r.v v10, v0176; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t177; CHECK-NEXT: lui a0, 307200178; CHECK-NEXT: vmv1r.v v8, v0179; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma180; CHECK-NEXT: vfabs.v v16, v12, v0.t181; CHECK-NEXT: fmv.w.x fa5, a0182; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu183; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t184; CHECK-NEXT: fsrmi a0, 0185; CHECK-NEXT: vmv1r.v v0, v8186; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma187; CHECK-NEXT: vfcvt.x.f.v v16, v12, v0.t188; CHECK-NEXT: fsrm a0189; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t190; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu191; CHECK-NEXT: vfsgnj.vv v12, v16, v12, v0.t192; CHECK-NEXT: vmv1r.v v0, v10193; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma194; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t195; CHECK-NEXT: ret196 %v = call <vscale x 8 x bfloat> @llvm.vp.roundeven.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 %evl)197 ret <vscale x 8 x bfloat> %v198}199 200define <vscale x 8 x bfloat> @vp_roundeven_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, i32 zeroext %evl) {201; CHECK-LABEL: vp_roundeven_nxv8bf16_unmasked:202; CHECK: # %bb.0:203; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma204; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8205; CHECK-NEXT: lui a0, 307200206; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma207; CHECK-NEXT: vfabs.v v8, v12208; CHECK-NEXT: fmv.w.x fa5, a0209; CHECK-NEXT: vmflt.vf v0, v8, fa5210; CHECK-NEXT: fsrmi a0, 0211; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t212; CHECK-NEXT: fsrm a0213; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t214; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu215; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t216; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma217; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12218; CHECK-NEXT: ret219 %v = call <vscale x 8 x bfloat> @llvm.vp.roundeven.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)220 ret <vscale x 8 x bfloat> %v221}222 223define <vscale x 16 x bfloat> @vp_roundeven_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {224; CHECK-LABEL: vp_roundeven_nxv16bf16:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma227; CHECK-NEXT: vmv1r.v v12, v0228; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t229; CHECK-NEXT: lui a0, 307200230; CHECK-NEXT: vmv1r.v v8, v0231; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma232; CHECK-NEXT: vfabs.v v24, v16, v0.t233; CHECK-NEXT: fmv.w.x fa5, a0234; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu235; CHECK-NEXT: vmflt.vf v8, v24, fa5, v0.t236; CHECK-NEXT: fsrmi a0, 0237; CHECK-NEXT: vmv1r.v v0, v8238; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma239; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t240; CHECK-NEXT: fsrm a0241; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t242; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu243; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t244; CHECK-NEXT: vmv1r.v v0, v12245; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma246; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t247; CHECK-NEXT: ret248 %v = call <vscale x 16 x bfloat> @llvm.vp.roundeven.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 %evl)249 ret <vscale x 16 x bfloat> %v250}251 252define <vscale x 16 x bfloat> @vp_roundeven_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, i32 zeroext %evl) {253; CHECK-LABEL: vp_roundeven_nxv16bf16_unmasked:254; CHECK: # %bb.0:255; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma256; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8257; CHECK-NEXT: lui a0, 307200258; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma259; CHECK-NEXT: vfabs.v v8, v16260; CHECK-NEXT: fmv.w.x fa5, a0261; CHECK-NEXT: vmflt.vf v0, v8, fa5262; CHECK-NEXT: fsrmi a0, 0263; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t264; CHECK-NEXT: fsrm a0265; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t266; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu267; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t268; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma269; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16270; CHECK-NEXT: ret271 %v = call <vscale x 16 x bfloat> @llvm.vp.roundeven.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)272 ret <vscale x 16 x bfloat> %v273}274 275define <vscale x 32 x bfloat> @vp_roundeven_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {276; CHECK-LABEL: vp_roundeven_nxv32bf16:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma279; CHECK-NEXT: vmv1r.v v7, v0280; CHECK-NEXT: csrr a2, vlenb281; CHECK-NEXT: lui a3, 307200282; CHECK-NEXT: slli a1, a2, 1283; CHECK-NEXT: srli a2, a2, 2284; CHECK-NEXT: fmv.w.x fa5, a3285; CHECK-NEXT: sub a3, a0, a1286; CHECK-NEXT: vslidedown.vx v6, v0, a2287; CHECK-NEXT: sltu a2, a0, a3288; CHECK-NEXT: vmv1r.v v5, v6289; CHECK-NEXT: addi a2, a2, -1290; CHECK-NEXT: and a2, a2, a3291; CHECK-NEXT: vmv1r.v v0, v6292; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma293; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t294; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma295; CHECK-NEXT: vfabs.v v16, v24, v0.t296; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu297; CHECK-NEXT: vmflt.vf v5, v16, fa5, v0.t298; CHECK-NEXT: fsrmi a2, 0299; CHECK-NEXT: vmv1r.v v0, v5300; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma301; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t302; CHECK-NEXT: fsrm a2303; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t304; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu305; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t306; CHECK-NEXT: vmv1r.v v0, v6307; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma308; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t309; CHECK-NEXT: bltu a0, a1, .LBB10_2310; CHECK-NEXT: # %bb.1:311; CHECK-NEXT: mv a0, a1312; CHECK-NEXT: .LBB10_2:313; CHECK-NEXT: vmv1r.v v0, v7314; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma315; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t316; CHECK-NEXT: vmv1r.v v8, v7317; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma318; CHECK-NEXT: vfabs.v v16, v24, v0.t319; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu320; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t321; CHECK-NEXT: fsrmi a0, 0322; CHECK-NEXT: vmv1r.v v0, v8323; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma324; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t325; CHECK-NEXT: fsrm a0326; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t327; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu328; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t329; CHECK-NEXT: vmv1r.v v0, v7330; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma331; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t332; CHECK-NEXT: ret333 %v = call <vscale x 32 x bfloat> @llvm.vp.roundeven.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)334 ret <vscale x 32 x bfloat> %v335}336 337define <vscale x 32 x bfloat> @vp_roundeven_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, i32 zeroext %evl) {338; CHECK-LABEL: vp_roundeven_nxv32bf16_unmasked:339; CHECK: # %bb.0:340; CHECK-NEXT: csrr a2, vlenb341; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma342; CHECK-NEXT: vmset.m v16343; CHECK-NEXT: lui a3, 307200344; CHECK-NEXT: slli a1, a2, 1345; CHECK-NEXT: srli a2, a2, 2346; CHECK-NEXT: fmv.w.x fa5, a3347; CHECK-NEXT: sub a3, a0, a1348; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma349; CHECK-NEXT: vslidedown.vx v7, v16, a2350; CHECK-NEXT: sltu a2, a0, a3351; CHECK-NEXT: vmv1r.v v6, v7352; CHECK-NEXT: addi a2, a2, -1353; CHECK-NEXT: and a2, a2, a3354; CHECK-NEXT: vmv1r.v v0, v7355; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma356; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t357; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma358; CHECK-NEXT: vfabs.v v16, v24, v0.t359; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu360; CHECK-NEXT: vmflt.vf v6, v16, fa5, v0.t361; CHECK-NEXT: fsrmi a2, 0362; CHECK-NEXT: vmv1r.v v0, v6363; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma364; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t365; CHECK-NEXT: fsrm a2366; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t367; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu368; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t369; CHECK-NEXT: vmv1r.v v0, v7370; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma371; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t372; CHECK-NEXT: bltu a0, a1, .LBB11_2373; CHECK-NEXT: # %bb.1:374; CHECK-NEXT: mv a0, a1375; CHECK-NEXT: .LBB11_2:376; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma377; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8378; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma379; CHECK-NEXT: vfabs.v v24, v16380; CHECK-NEXT: vmflt.vf v0, v24, fa5381; CHECK-NEXT: fsrmi a0, 0382; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t383; CHECK-NEXT: fsrm a0384; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t385; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu386; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t387; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma388; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16389; CHECK-NEXT: ret390 %v = call <vscale x 32 x bfloat> @llvm.vp.roundeven.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)391 ret <vscale x 32 x bfloat> %v392}393 394define <vscale x 1 x half> @vp_roundeven_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {395; ZVFH-LABEL: vp_roundeven_nxv1f16:396; ZVFH: # %bb.0:397; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma398; ZVFH-NEXT: vfabs.v v9, v8, v0.t399; ZVFH-NEXT: li a0, 25400; ZVFH-NEXT: slli a0, a0, 10401; ZVFH-NEXT: fmv.h.x fa5, a0402; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu403; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t404; ZVFH-NEXT: fsrmi a0, 0405; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma406; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t407; ZVFH-NEXT: fsrm a0408; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t409; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu410; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t411; ZVFH-NEXT: ret412;413; ZVFHMIN-LABEL: vp_roundeven_nxv1f16:414; ZVFHMIN: # %bb.0:415; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma416; ZVFHMIN-NEXT: vmv1r.v v9, v0417; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t418; ZVFHMIN-NEXT: lui a0, 307200419; ZVFHMIN-NEXT: vmv1r.v v8, v0420; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma421; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t422; ZVFHMIN-NEXT: fmv.w.x fa5, a0423; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu424; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t425; ZVFHMIN-NEXT: fsrmi a0, 0426; ZVFHMIN-NEXT: vmv1r.v v0, v8427; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma428; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t429; ZVFHMIN-NEXT: fsrm a0430; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t431; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu432; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t433; ZVFHMIN-NEXT: vmv1r.v v0, v9434; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma435; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t436; ZVFHMIN-NEXT: ret437 %v = call <vscale x 1 x half> @llvm.vp.roundeven.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)438 ret <vscale x 1 x half> %v439}440 441define <vscale x 1 x half> @vp_roundeven_nxv1f16_unmasked(<vscale x 1 x half> %va, i32 zeroext %evl) {442; ZVFH-LABEL: vp_roundeven_nxv1f16_unmasked:443; ZVFH: # %bb.0:444; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma445; ZVFH-NEXT: vfabs.v v9, v8446; ZVFH-NEXT: li a0, 25447; ZVFH-NEXT: slli a0, a0, 10448; ZVFH-NEXT: fmv.h.x fa5, a0449; ZVFH-NEXT: vmflt.vf v0, v9, fa5450; ZVFH-NEXT: fsrmi a0, 0451; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t452; ZVFH-NEXT: fsrm a0453; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t454; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu455; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t456; ZVFH-NEXT: ret457;458; ZVFHMIN-LABEL: vp_roundeven_nxv1f16_unmasked:459; ZVFHMIN: # %bb.0:460; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma461; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8462; ZVFHMIN-NEXT: lui a0, 307200463; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma464; ZVFHMIN-NEXT: vfabs.v v8, v9465; ZVFHMIN-NEXT: fmv.w.x fa5, a0466; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5467; ZVFHMIN-NEXT: fsrmi a0, 0468; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t469; ZVFHMIN-NEXT: fsrm a0470; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t471; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu472; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t473; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma474; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9475; ZVFHMIN-NEXT: ret476 %v = call <vscale x 1 x half> @llvm.vp.roundeven.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)477 ret <vscale x 1 x half> %v478}479 480define <vscale x 2 x half> @vp_roundeven_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {481; ZVFH-LABEL: vp_roundeven_nxv2f16:482; ZVFH: # %bb.0:483; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma484; ZVFH-NEXT: vfabs.v v9, v8, v0.t485; ZVFH-NEXT: li a0, 25486; ZVFH-NEXT: slli a0, a0, 10487; ZVFH-NEXT: fmv.h.x fa5, a0488; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu489; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t490; ZVFH-NEXT: fsrmi a0, 0491; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma492; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t493; ZVFH-NEXT: fsrm a0494; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t495; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu496; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t497; ZVFH-NEXT: ret498;499; ZVFHMIN-LABEL: vp_roundeven_nxv2f16:500; ZVFHMIN: # %bb.0:501; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma502; ZVFHMIN-NEXT: vmv1r.v v9, v0503; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t504; ZVFHMIN-NEXT: lui a0, 307200505; ZVFHMIN-NEXT: vmv1r.v v8, v0506; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma507; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t508; ZVFHMIN-NEXT: fmv.w.x fa5, a0509; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu510; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t511; ZVFHMIN-NEXT: fsrmi a0, 0512; ZVFHMIN-NEXT: vmv.v.v v0, v8513; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma514; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t515; ZVFHMIN-NEXT: fsrm a0516; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t517; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu518; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t519; ZVFHMIN-NEXT: vmv1r.v v0, v9520; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma521; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t522; ZVFHMIN-NEXT: ret523 %v = call <vscale x 2 x half> @llvm.vp.roundeven.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)524 ret <vscale x 2 x half> %v525}526 527define <vscale x 2 x half> @vp_roundeven_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {528; ZVFH-LABEL: vp_roundeven_nxv2f16_unmasked:529; ZVFH: # %bb.0:530; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma531; ZVFH-NEXT: vfabs.v v9, v8532; ZVFH-NEXT: li a0, 25533; ZVFH-NEXT: slli a0, a0, 10534; ZVFH-NEXT: fmv.h.x fa5, a0535; ZVFH-NEXT: vmflt.vf v0, v9, fa5536; ZVFH-NEXT: fsrmi a0, 0537; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t538; ZVFH-NEXT: fsrm a0539; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t540; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu541; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t542; ZVFH-NEXT: ret543;544; ZVFHMIN-LABEL: vp_roundeven_nxv2f16_unmasked:545; ZVFHMIN: # %bb.0:546; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma547; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8548; ZVFHMIN-NEXT: lui a0, 307200549; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma550; ZVFHMIN-NEXT: vfabs.v v8, v9551; ZVFHMIN-NEXT: fmv.w.x fa5, a0552; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5553; ZVFHMIN-NEXT: fsrmi a0, 0554; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t555; ZVFHMIN-NEXT: fsrm a0556; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t557; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu558; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t559; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma560; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9561; ZVFHMIN-NEXT: ret562 %v = call <vscale x 2 x half> @llvm.vp.roundeven.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)563 ret <vscale x 2 x half> %v564}565 566define <vscale x 4 x half> @vp_roundeven_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {567; ZVFH-LABEL: vp_roundeven_nxv4f16:568; ZVFH: # %bb.0:569; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma570; ZVFH-NEXT: vfabs.v v9, v8, v0.t571; ZVFH-NEXT: li a0, 25572; ZVFH-NEXT: slli a0, a0, 10573; ZVFH-NEXT: fmv.h.x fa5, a0574; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu575; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t576; ZVFH-NEXT: fsrmi a0, 0577; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma578; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t579; ZVFH-NEXT: fsrm a0580; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t581; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu582; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t583; ZVFH-NEXT: ret584;585; ZVFHMIN-LABEL: vp_roundeven_nxv4f16:586; ZVFHMIN: # %bb.0:587; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma588; ZVFHMIN-NEXT: vmv1r.v v9, v0589; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t590; ZVFHMIN-NEXT: lui a0, 307200591; ZVFHMIN-NEXT: vmv1r.v v8, v0592; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma593; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t594; ZVFHMIN-NEXT: fmv.w.x fa5, a0595; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu596; ZVFHMIN-NEXT: vmflt.vf v8, v12, fa5, v0.t597; ZVFHMIN-NEXT: fsrmi a0, 0598; ZVFHMIN-NEXT: vmv1r.v v0, v8599; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma600; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t601; ZVFHMIN-NEXT: fsrm a0602; ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t603; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu604; ZVFHMIN-NEXT: vfsgnj.vv v10, v12, v10, v0.t605; ZVFHMIN-NEXT: vmv1r.v v0, v9606; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma607; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t608; ZVFHMIN-NEXT: ret609 %v = call <vscale x 4 x half> @llvm.vp.roundeven.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 %evl)610 ret <vscale x 4 x half> %v611}612 613define <vscale x 4 x half> @vp_roundeven_nxv4f16_unmasked(<vscale x 4 x half> %va, i32 zeroext %evl) {614; ZVFH-LABEL: vp_roundeven_nxv4f16_unmasked:615; ZVFH: # %bb.0:616; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma617; ZVFH-NEXT: vfabs.v v9, v8618; ZVFH-NEXT: li a0, 25619; ZVFH-NEXT: slli a0, a0, 10620; ZVFH-NEXT: fmv.h.x fa5, a0621; ZVFH-NEXT: vmflt.vf v0, v9, fa5622; ZVFH-NEXT: fsrmi a0, 0623; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t624; ZVFH-NEXT: fsrm a0625; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t626; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu627; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t628; ZVFH-NEXT: ret629;630; ZVFHMIN-LABEL: vp_roundeven_nxv4f16_unmasked:631; ZVFHMIN: # %bb.0:632; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma633; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8634; ZVFHMIN-NEXT: lui a0, 307200635; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma636; ZVFHMIN-NEXT: vfabs.v v8, v10637; ZVFHMIN-NEXT: fmv.w.x fa5, a0638; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5639; ZVFHMIN-NEXT: fsrmi a0, 0640; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t641; ZVFHMIN-NEXT: fsrm a0642; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t643; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu644; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t645; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma646; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10647; ZVFHMIN-NEXT: ret648 %v = call <vscale x 4 x half> @llvm.vp.roundeven.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)649 ret <vscale x 4 x half> %v650}651 652define <vscale x 8 x half> @vp_roundeven_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {653; ZVFH-LABEL: vp_roundeven_nxv8f16:654; ZVFH: # %bb.0:655; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma656; ZVFH-NEXT: vmv1r.v v10, v0657; ZVFH-NEXT: vfabs.v v12, v8, v0.t658; ZVFH-NEXT: li a0, 25659; ZVFH-NEXT: slli a0, a0, 10660; ZVFH-NEXT: fmv.h.x fa5, a0661; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu662; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t663; ZVFH-NEXT: fsrmi a0, 0664; ZVFH-NEXT: vmv1r.v v0, v10665; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma666; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t667; ZVFH-NEXT: fsrm a0668; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t669; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu670; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t671; ZVFH-NEXT: ret672;673; ZVFHMIN-LABEL: vp_roundeven_nxv8f16:674; ZVFHMIN: # %bb.0:675; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma676; ZVFHMIN-NEXT: vmv1r.v v10, v0677; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t678; ZVFHMIN-NEXT: lui a0, 307200679; ZVFHMIN-NEXT: vmv1r.v v8, v0680; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma681; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t682; ZVFHMIN-NEXT: fmv.w.x fa5, a0683; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu684; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t685; ZVFHMIN-NEXT: fsrmi a0, 0686; ZVFHMIN-NEXT: vmv1r.v v0, v8687; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma688; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t689; ZVFHMIN-NEXT: fsrm a0690; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t691; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu692; ZVFHMIN-NEXT: vfsgnj.vv v12, v16, v12, v0.t693; ZVFHMIN-NEXT: vmv1r.v v0, v10694; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma695; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t696; ZVFHMIN-NEXT: ret697 %v = call <vscale x 8 x half> @llvm.vp.roundeven.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 %evl)698 ret <vscale x 8 x half> %v699}700 701define <vscale x 8 x half> @vp_roundeven_nxv8f16_unmasked(<vscale x 8 x half> %va, i32 zeroext %evl) {702; ZVFH-LABEL: vp_roundeven_nxv8f16_unmasked:703; ZVFH: # %bb.0:704; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma705; ZVFH-NEXT: vfabs.v v10, v8706; ZVFH-NEXT: li a0, 25707; ZVFH-NEXT: slli a0, a0, 10708; ZVFH-NEXT: fmv.h.x fa5, a0709; ZVFH-NEXT: vmflt.vf v0, v10, fa5710; ZVFH-NEXT: fsrmi a0, 0711; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t712; ZVFH-NEXT: fsrm a0713; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t714; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu715; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t716; ZVFH-NEXT: ret717;718; ZVFHMIN-LABEL: vp_roundeven_nxv8f16_unmasked:719; ZVFHMIN: # %bb.0:720; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma721; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8722; ZVFHMIN-NEXT: lui a0, 307200723; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma724; ZVFHMIN-NEXT: vfabs.v v8, v12725; ZVFHMIN-NEXT: fmv.w.x fa5, a0726; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5727; ZVFHMIN-NEXT: fsrmi a0, 0728; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t729; ZVFHMIN-NEXT: fsrm a0730; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t731; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu732; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t733; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma734; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12735; ZVFHMIN-NEXT: ret736 %v = call <vscale x 8 x half> @llvm.vp.roundeven.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)737 ret <vscale x 8 x half> %v738}739 740define <vscale x 16 x half> @vp_roundeven_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {741; ZVFH-LABEL: vp_roundeven_nxv16f16:742; ZVFH: # %bb.0:743; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma744; ZVFH-NEXT: vmv1r.v v12, v0745; ZVFH-NEXT: vfabs.v v16, v8, v0.t746; ZVFH-NEXT: li a0, 25747; ZVFH-NEXT: slli a0, a0, 10748; ZVFH-NEXT: fmv.h.x fa5, a0749; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu750; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t751; ZVFH-NEXT: fsrmi a0, 0752; ZVFH-NEXT: vmv1r.v v0, v12753; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma754; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t755; ZVFH-NEXT: fsrm a0756; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t757; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu758; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t759; ZVFH-NEXT: ret760;761; ZVFHMIN-LABEL: vp_roundeven_nxv16f16:762; ZVFHMIN: # %bb.0:763; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma764; ZVFHMIN-NEXT: vmv1r.v v12, v0765; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t766; ZVFHMIN-NEXT: lui a0, 307200767; ZVFHMIN-NEXT: vmv1r.v v8, v0768; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma769; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t770; ZVFHMIN-NEXT: fmv.w.x fa5, a0771; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu772; ZVFHMIN-NEXT: vmflt.vf v8, v24, fa5, v0.t773; ZVFHMIN-NEXT: fsrmi a0, 0774; ZVFHMIN-NEXT: vmv1r.v v0, v8775; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma776; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t777; ZVFHMIN-NEXT: fsrm a0778; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t779; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu780; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t781; ZVFHMIN-NEXT: vmv1r.v v0, v12782; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma783; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t784; ZVFHMIN-NEXT: ret785 %v = call <vscale x 16 x half> @llvm.vp.roundeven.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 %evl)786 ret <vscale x 16 x half> %v787}788 789define <vscale x 16 x half> @vp_roundeven_nxv16f16_unmasked(<vscale x 16 x half> %va, i32 zeroext %evl) {790; ZVFH-LABEL: vp_roundeven_nxv16f16_unmasked:791; ZVFH: # %bb.0:792; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma793; ZVFH-NEXT: vfabs.v v12, v8794; ZVFH-NEXT: li a0, 25795; ZVFH-NEXT: slli a0, a0, 10796; ZVFH-NEXT: fmv.h.x fa5, a0797; ZVFH-NEXT: vmflt.vf v0, v12, fa5798; ZVFH-NEXT: fsrmi a0, 0799; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t800; ZVFH-NEXT: fsrm a0801; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t802; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu803; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t804; ZVFH-NEXT: ret805;806; ZVFHMIN-LABEL: vp_roundeven_nxv16f16_unmasked:807; ZVFHMIN: # %bb.0:808; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma809; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8810; ZVFHMIN-NEXT: lui a0, 307200811; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma812; ZVFHMIN-NEXT: vfabs.v v8, v16813; ZVFHMIN-NEXT: fmv.w.x fa5, a0814; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5815; ZVFHMIN-NEXT: fsrmi a0, 0816; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t817; ZVFHMIN-NEXT: fsrm a0818; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t819; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu820; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t821; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma822; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16823; ZVFHMIN-NEXT: ret824 %v = call <vscale x 16 x half> @llvm.vp.roundeven.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)825 ret <vscale x 16 x half> %v826}827 828define <vscale x 32 x half> @vp_roundeven_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {829; ZVFH-LABEL: vp_roundeven_nxv32f16:830; ZVFH: # %bb.0:831; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma832; ZVFH-NEXT: vmv1r.v v16, v0833; ZVFH-NEXT: vfabs.v v24, v8, v0.t834; ZVFH-NEXT: li a0, 25835; ZVFH-NEXT: slli a0, a0, 10836; ZVFH-NEXT: fmv.h.x fa5, a0837; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu838; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t839; ZVFH-NEXT: fsrmi a0, 0840; ZVFH-NEXT: vmv1r.v v0, v16841; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, ma842; ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t843; ZVFH-NEXT: fsrm a0844; ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t845; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu846; ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t847; ZVFH-NEXT: ret848;849; ZVFHMIN-LABEL: vp_roundeven_nxv32f16:850; ZVFHMIN: # %bb.0:851; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma852; ZVFHMIN-NEXT: vmv1r.v v7, v0853; ZVFHMIN-NEXT: csrr a2, vlenb854; ZVFHMIN-NEXT: lui a3, 307200855; ZVFHMIN-NEXT: slli a1, a2, 1856; ZVFHMIN-NEXT: srli a2, a2, 2857; ZVFHMIN-NEXT: fmv.w.x fa5, a3858; ZVFHMIN-NEXT: sub a3, a0, a1859; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2860; ZVFHMIN-NEXT: sltu a2, a0, a3861; ZVFHMIN-NEXT: vmv1r.v v5, v6862; ZVFHMIN-NEXT: addi a2, a2, -1863; ZVFHMIN-NEXT: and a2, a2, a3864; ZVFHMIN-NEXT: vmv1r.v v0, v6865; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma866; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t867; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma868; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t869; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu870; ZVFHMIN-NEXT: vmflt.vf v5, v16, fa5, v0.t871; ZVFHMIN-NEXT: fsrmi a2, 0872; ZVFHMIN-NEXT: vmv1r.v v0, v5873; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma874; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t875; ZVFHMIN-NEXT: fsrm a2876; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t877; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu878; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t879; ZVFHMIN-NEXT: vmv1r.v v0, v6880; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma881; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t882; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2883; ZVFHMIN-NEXT: # %bb.1:884; ZVFHMIN-NEXT: mv a0, a1885; ZVFHMIN-NEXT: .LBB22_2:886; ZVFHMIN-NEXT: vmv1r.v v0, v7887; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma888; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t889; ZVFHMIN-NEXT: vmv1r.v v8, v7890; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma891; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t892; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu893; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t894; ZVFHMIN-NEXT: fsrmi a0, 0895; ZVFHMIN-NEXT: vmv1r.v v0, v8896; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma897; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t898; ZVFHMIN-NEXT: fsrm a0899; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t900; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu901; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t902; ZVFHMIN-NEXT: vmv1r.v v0, v7903; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma904; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t905; ZVFHMIN-NEXT: ret906 %v = call <vscale x 32 x half> @llvm.vp.roundeven.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)907 ret <vscale x 32 x half> %v908}909 910define <vscale x 32 x half> @vp_roundeven_nxv32f16_unmasked(<vscale x 32 x half> %va, i32 zeroext %evl) {911; ZVFH-LABEL: vp_roundeven_nxv32f16_unmasked:912; ZVFH: # %bb.0:913; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma914; ZVFH-NEXT: vfabs.v v16, v8915; ZVFH-NEXT: li a0, 25916; ZVFH-NEXT: slli a0, a0, 10917; ZVFH-NEXT: fmv.h.x fa5, a0918; ZVFH-NEXT: vmflt.vf v0, v16, fa5919; ZVFH-NEXT: fsrmi a0, 0920; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t921; ZVFH-NEXT: fsrm a0922; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t923; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu924; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t925; ZVFH-NEXT: ret926;927; ZVFHMIN-LABEL: vp_roundeven_nxv32f16_unmasked:928; ZVFHMIN: # %bb.0:929; ZVFHMIN-NEXT: csrr a2, vlenb930; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma931; ZVFHMIN-NEXT: vmset.m v16932; ZVFHMIN-NEXT: lui a3, 307200933; ZVFHMIN-NEXT: slli a1, a2, 1934; ZVFHMIN-NEXT: srli a2, a2, 2935; ZVFHMIN-NEXT: fmv.w.x fa5, a3936; ZVFHMIN-NEXT: sub a3, a0, a1937; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma938; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a2939; ZVFHMIN-NEXT: sltu a2, a0, a3940; ZVFHMIN-NEXT: vmv1r.v v6, v7941; ZVFHMIN-NEXT: addi a2, a2, -1942; ZVFHMIN-NEXT: and a2, a2, a3943; ZVFHMIN-NEXT: vmv1r.v v0, v7944; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma945; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t946; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma947; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t948; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu949; ZVFHMIN-NEXT: vmflt.vf v6, v16, fa5, v0.t950; ZVFHMIN-NEXT: fsrmi a2, 0951; ZVFHMIN-NEXT: vmv1r.v v0, v6952; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma953; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t954; ZVFHMIN-NEXT: fsrm a2955; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t956; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu957; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t958; ZVFHMIN-NEXT: vmv1r.v v0, v7959; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma960; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t961; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2962; ZVFHMIN-NEXT: # %bb.1:963; ZVFHMIN-NEXT: mv a0, a1964; ZVFHMIN-NEXT: .LBB23_2:965; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma966; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8967; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma968; ZVFHMIN-NEXT: vfabs.v v24, v16969; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5970; ZVFHMIN-NEXT: fsrmi a0, 0971; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t972; ZVFHMIN-NEXT: fsrm a0973; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t974; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu975; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t976; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma977; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16978; ZVFHMIN-NEXT: ret979 %v = call <vscale x 32 x half> @llvm.vp.roundeven.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)980 ret <vscale x 32 x half> %v981}982 983define <vscale x 1 x float> @vp_roundeven_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {984; CHECK-LABEL: vp_roundeven_nxv1f32:985; CHECK: # %bb.0:986; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma987; CHECK-NEXT: vfabs.v v9, v8, v0.t988; CHECK-NEXT: lui a0, 307200989; CHECK-NEXT: fmv.w.x fa5, a0990; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu991; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t992; CHECK-NEXT: fsrmi a0, 0993; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma994; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t995; CHECK-NEXT: fsrm a0996; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t997; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu998; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t999; CHECK-NEXT: ret1000 %v = call <vscale x 1 x float> @llvm.vp.roundeven.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 %evl)1001 ret <vscale x 1 x float> %v1002}1003 1004define <vscale x 1 x float> @vp_roundeven_nxv1f32_unmasked(<vscale x 1 x float> %va, i32 zeroext %evl) {1005; CHECK-LABEL: vp_roundeven_nxv1f32_unmasked:1006; CHECK: # %bb.0:1007; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1008; CHECK-NEXT: vfabs.v v9, v81009; CHECK-NEXT: lui a0, 3072001010; CHECK-NEXT: fmv.w.x fa5, a01011; CHECK-NEXT: vmflt.vf v0, v9, fa51012; CHECK-NEXT: fsrmi a0, 01013; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t1014; CHECK-NEXT: fsrm a01015; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t1016; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu1017; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t1018; CHECK-NEXT: ret1019 %v = call <vscale x 1 x float> @llvm.vp.roundeven.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)1020 ret <vscale x 1 x float> %v1021}1022 1023define <vscale x 2 x float> @vp_roundeven_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1024; CHECK-LABEL: vp_roundeven_nxv2f32:1025; CHECK: # %bb.0:1026; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1027; CHECK-NEXT: vfabs.v v9, v8, v0.t1028; CHECK-NEXT: lui a0, 3072001029; CHECK-NEXT: fmv.w.x fa5, a01030; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu1031; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t1032; CHECK-NEXT: fsrmi a0, 01033; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma1034; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t1035; CHECK-NEXT: fsrm a01036; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t1037; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu1038; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t1039; CHECK-NEXT: ret1040 %v = call <vscale x 2 x float> @llvm.vp.roundeven.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)1041 ret <vscale x 2 x float> %v1042}1043 1044define <vscale x 2 x float> @vp_roundeven_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {1045; CHECK-LABEL: vp_roundeven_nxv2f32_unmasked:1046; CHECK: # %bb.0:1047; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1048; CHECK-NEXT: vfabs.v v9, v81049; CHECK-NEXT: lui a0, 3072001050; CHECK-NEXT: fmv.w.x fa5, a01051; CHECK-NEXT: vmflt.vf v0, v9, fa51052; CHECK-NEXT: fsrmi a0, 01053; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t1054; CHECK-NEXT: fsrm a01055; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t1056; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu1057; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t1058; CHECK-NEXT: ret1059 %v = call <vscale x 2 x float> @llvm.vp.roundeven.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)1060 ret <vscale x 2 x float> %v1061}1062 1063define <vscale x 4 x float> @vp_roundeven_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1064; CHECK-LABEL: vp_roundeven_nxv4f32:1065; CHECK: # %bb.0:1066; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1067; CHECK-NEXT: vmv1r.v v10, v01068; CHECK-NEXT: vfabs.v v12, v8, v0.t1069; CHECK-NEXT: lui a0, 3072001070; CHECK-NEXT: fmv.w.x fa5, a01071; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu1072; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t1073; CHECK-NEXT: fsrmi a0, 01074; CHECK-NEXT: vmv1r.v v0, v101075; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1076; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t1077; CHECK-NEXT: fsrm a01078; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t1079; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu1080; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t1081; CHECK-NEXT: ret1082 %v = call <vscale x 4 x float> @llvm.vp.roundeven.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 %evl)1083 ret <vscale x 4 x float> %v1084}1085 1086define <vscale x 4 x float> @vp_roundeven_nxv4f32_unmasked(<vscale x 4 x float> %va, i32 zeroext %evl) {1087; CHECK-LABEL: vp_roundeven_nxv4f32_unmasked:1088; CHECK: # %bb.0:1089; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1090; CHECK-NEXT: vfabs.v v10, v81091; CHECK-NEXT: lui a0, 3072001092; CHECK-NEXT: fmv.w.x fa5, a01093; CHECK-NEXT: vmflt.vf v0, v10, fa51094; CHECK-NEXT: fsrmi a0, 01095; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t1096; CHECK-NEXT: fsrm a01097; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t1098; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu1099; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t1100; CHECK-NEXT: ret1101 %v = call <vscale x 4 x float> @llvm.vp.roundeven.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)1102 ret <vscale x 4 x float> %v1103}1104 1105define <vscale x 8 x float> @vp_roundeven_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1106; CHECK-LABEL: vp_roundeven_nxv8f32:1107; CHECK: # %bb.0:1108; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1109; CHECK-NEXT: vmv1r.v v12, v01110; CHECK-NEXT: vfabs.v v16, v8, v0.t1111; CHECK-NEXT: lui a0, 3072001112; CHECK-NEXT: fmv.w.x fa5, a01113; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu1114; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t1115; CHECK-NEXT: fsrmi a0, 01116; CHECK-NEXT: vmv1r.v v0, v121117; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1118; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t1119; CHECK-NEXT: fsrm a01120; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t1121; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu1122; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t1123; CHECK-NEXT: ret1124 %v = call <vscale x 8 x float> @llvm.vp.roundeven.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 %evl)1125 ret <vscale x 8 x float> %v1126}1127 1128define <vscale x 8 x float> @vp_roundeven_nxv8f32_unmasked(<vscale x 8 x float> %va, i32 zeroext %evl) {1129; CHECK-LABEL: vp_roundeven_nxv8f32_unmasked:1130; CHECK: # %bb.0:1131; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1132; CHECK-NEXT: vfabs.v v12, v81133; CHECK-NEXT: lui a0, 3072001134; CHECK-NEXT: fmv.w.x fa5, a01135; CHECK-NEXT: vmflt.vf v0, v12, fa51136; CHECK-NEXT: fsrmi a0, 01137; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t1138; CHECK-NEXT: fsrm a01139; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t1140; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu1141; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t1142; CHECK-NEXT: ret1143 %v = call <vscale x 8 x float> @llvm.vp.roundeven.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)1144 ret <vscale x 8 x float> %v1145}1146 1147define <vscale x 16 x float> @vp_roundeven_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1148; CHECK-LABEL: vp_roundeven_nxv16f32:1149; CHECK: # %bb.0:1150; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1151; CHECK-NEXT: vmv1r.v v16, v01152; CHECK-NEXT: vfabs.v v24, v8, v0.t1153; CHECK-NEXT: lui a0, 3072001154; CHECK-NEXT: fmv.w.x fa5, a01155; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu1156; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t1157; CHECK-NEXT: fsrmi a0, 01158; CHECK-NEXT: vmv1r.v v0, v161159; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma1160; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t1161; CHECK-NEXT: fsrm a01162; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t1163; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu1164; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t1165; CHECK-NEXT: ret1166 %v = call <vscale x 16 x float> @llvm.vp.roundeven.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 %evl)1167 ret <vscale x 16 x float> %v1168}1169 1170define <vscale x 16 x float> @vp_roundeven_nxv16f32_unmasked(<vscale x 16 x float> %va, i32 zeroext %evl) {1171; CHECK-LABEL: vp_roundeven_nxv16f32_unmasked:1172; CHECK: # %bb.0:1173; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1174; CHECK-NEXT: vfabs.v v16, v81175; CHECK-NEXT: lui a0, 3072001176; CHECK-NEXT: fmv.w.x fa5, a01177; CHECK-NEXT: vmflt.vf v0, v16, fa51178; CHECK-NEXT: fsrmi a0, 01179; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t1180; CHECK-NEXT: fsrm a01181; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t1182; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu1183; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t1184; CHECK-NEXT: ret1185 %v = call <vscale x 16 x float> @llvm.vp.roundeven.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)1186 ret <vscale x 16 x float> %v1187}1188 1189define <vscale x 1 x double> @vp_roundeven_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1190; RV32ZVFH-LABEL: vp_roundeven_nxv1f64:1191; RV32ZVFH: # %bb.0:1192; RV32ZVFH-NEXT: lui a1, %hi(.LCPI34_0)1193; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI34_0)(a1)1194; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1195; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t1196; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1197; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t1198; RV32ZVFH-NEXT: fsrmi a0, 01199; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma1200; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1201; RV32ZVFH-NEXT: fsrm a01202; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1203; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1204; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1205; RV32ZVFH-NEXT: ret1206;1207; RV64ZVFH-LABEL: vp_roundeven_nxv1f64:1208; RV64ZVFH: # %bb.0:1209; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1210; RV64ZVFH-NEXT: vfabs.v v9, v8, v0.t1211; RV64ZVFH-NEXT: li a0, 10751212; RV64ZVFH-NEXT: slli a0, a0, 521213; RV64ZVFH-NEXT: fmv.d.x fa5, a01214; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1215; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t1216; RV64ZVFH-NEXT: fsrmi a0, 01217; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma1218; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1219; RV64ZVFH-NEXT: fsrm a01220; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1221; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1222; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1223; RV64ZVFH-NEXT: ret1224;1225; RV32ZVFHMIN-LABEL: vp_roundeven_nxv1f64:1226; RV32ZVFHMIN: # %bb.0:1227; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI34_0)1228; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI34_0)(a1)1229; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma1230; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t1231; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1232; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t1233; RV32ZVFHMIN-NEXT: fsrmi a0, 01234; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma1235; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t1236; RV32ZVFHMIN-NEXT: fsrm a01237; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t1238; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1239; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t1240; RV32ZVFHMIN-NEXT: ret1241;1242; RV64ZVFHMIN-LABEL: vp_roundeven_nxv1f64:1243; RV64ZVFHMIN: # %bb.0:1244; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma1245; RV64ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t1246; RV64ZVFHMIN-NEXT: li a0, 10751247; RV64ZVFHMIN-NEXT: slli a0, a0, 521248; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01249; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1250; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t1251; RV64ZVFHMIN-NEXT: fsrmi a0, 01252; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma1253; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t1254; RV64ZVFHMIN-NEXT: fsrm a01255; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t1256; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1257; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t1258; RV64ZVFHMIN-NEXT: ret1259 %v = call <vscale x 1 x double> @llvm.vp.roundeven.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 %evl)1260 ret <vscale x 1 x double> %v1261}1262 1263define <vscale x 1 x double> @vp_roundeven_nxv1f64_unmasked(<vscale x 1 x double> %va, i32 zeroext %evl) {1264; RV32ZVFH-LABEL: vp_roundeven_nxv1f64_unmasked:1265; RV32ZVFH: # %bb.0:1266; RV32ZVFH-NEXT: lui a1, %hi(.LCPI35_0)1267; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI35_0)(a1)1268; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1269; RV32ZVFH-NEXT: vfabs.v v9, v81270; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa51271; RV32ZVFH-NEXT: fsrmi a0, 01272; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1273; RV32ZVFH-NEXT: fsrm a01274; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1275; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1276; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1277; RV32ZVFH-NEXT: ret1278;1279; RV64ZVFH-LABEL: vp_roundeven_nxv1f64_unmasked:1280; RV64ZVFH: # %bb.0:1281; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1282; RV64ZVFH-NEXT: vfabs.v v9, v81283; RV64ZVFH-NEXT: li a0, 10751284; RV64ZVFH-NEXT: slli a0, a0, 521285; RV64ZVFH-NEXT: fmv.d.x fa5, a01286; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa51287; RV64ZVFH-NEXT: fsrmi a0, 01288; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1289; RV64ZVFH-NEXT: fsrm a01290; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1291; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1292; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1293; RV64ZVFH-NEXT: ret1294;1295; RV32ZVFHMIN-LABEL: vp_roundeven_nxv1f64_unmasked:1296; RV32ZVFHMIN: # %bb.0:1297; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI35_0)1298; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI35_0)(a1)1299; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma1300; RV32ZVFHMIN-NEXT: vfabs.v v9, v81301; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa51302; RV32ZVFHMIN-NEXT: fsrmi a0, 01303; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t1304; RV32ZVFHMIN-NEXT: fsrm a01305; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t1306; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1307; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t1308; RV32ZVFHMIN-NEXT: ret1309;1310; RV64ZVFHMIN-LABEL: vp_roundeven_nxv1f64_unmasked:1311; RV64ZVFHMIN: # %bb.0:1312; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma1313; RV64ZVFHMIN-NEXT: vfabs.v v9, v81314; RV64ZVFHMIN-NEXT: li a0, 10751315; RV64ZVFHMIN-NEXT: slli a0, a0, 521316; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01317; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa51318; RV64ZVFHMIN-NEXT: fsrmi a0, 01319; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t1320; RV64ZVFHMIN-NEXT: fsrm a01321; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t1322; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu1323; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t1324; RV64ZVFHMIN-NEXT: ret1325 %v = call <vscale x 1 x double> @llvm.vp.roundeven.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)1326 ret <vscale x 1 x double> %v1327}1328 1329define <vscale x 2 x double> @vp_roundeven_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1330; RV32ZVFH-LABEL: vp_roundeven_nxv2f64:1331; RV32ZVFH: # %bb.0:1332; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1333; RV32ZVFH-NEXT: vmv1r.v v10, v01334; RV32ZVFH-NEXT: lui a0, %hi(.LCPI36_0)1335; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI36_0)(a0)1336; RV32ZVFH-NEXT: vfabs.v v12, v8, v0.t1337; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1338; RV32ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t1339; RV32ZVFH-NEXT: fsrmi a0, 01340; RV32ZVFH-NEXT: vmv1r.v v0, v101341; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, ma1342; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1343; RV32ZVFH-NEXT: fsrm a01344; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1345; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1346; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1347; RV32ZVFH-NEXT: ret1348;1349; RV64ZVFH-LABEL: vp_roundeven_nxv2f64:1350; RV64ZVFH: # %bb.0:1351; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1352; RV64ZVFH-NEXT: vmv1r.v v10, v01353; RV64ZVFH-NEXT: vfabs.v v12, v8, v0.t1354; RV64ZVFH-NEXT: li a0, 10751355; RV64ZVFH-NEXT: slli a0, a0, 521356; RV64ZVFH-NEXT: fmv.d.x fa5, a01357; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1358; RV64ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t1359; RV64ZVFH-NEXT: fsrmi a0, 01360; RV64ZVFH-NEXT: vmv1r.v v0, v101361; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, ma1362; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1363; RV64ZVFH-NEXT: fsrm a01364; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1365; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1366; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1367; RV64ZVFH-NEXT: ret1368;1369; RV32ZVFHMIN-LABEL: vp_roundeven_nxv2f64:1370; RV32ZVFHMIN: # %bb.0:1371; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma1372; RV32ZVFHMIN-NEXT: vmv1r.v v10, v01373; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI36_0)1374; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI36_0)(a0)1375; RV32ZVFHMIN-NEXT: vfabs.v v12, v8, v0.t1376; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1377; RV32ZVFHMIN-NEXT: vmflt.vf v10, v12, fa5, v0.t1378; RV32ZVFHMIN-NEXT: fsrmi a0, 01379; RV32ZVFHMIN-NEXT: vmv1r.v v0, v101380; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, ma1381; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t1382; RV32ZVFHMIN-NEXT: fsrm a01383; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t1384; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1385; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t1386; RV32ZVFHMIN-NEXT: ret1387;1388; RV64ZVFHMIN-LABEL: vp_roundeven_nxv2f64:1389; RV64ZVFHMIN: # %bb.0:1390; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma1391; RV64ZVFHMIN-NEXT: vmv1r.v v10, v01392; RV64ZVFHMIN-NEXT: vfabs.v v12, v8, v0.t1393; RV64ZVFHMIN-NEXT: li a0, 10751394; RV64ZVFHMIN-NEXT: slli a0, a0, 521395; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01396; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1397; RV64ZVFHMIN-NEXT: vmflt.vf v10, v12, fa5, v0.t1398; RV64ZVFHMIN-NEXT: fsrmi a0, 01399; RV64ZVFHMIN-NEXT: vmv1r.v v0, v101400; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, ma1401; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t1402; RV64ZVFHMIN-NEXT: fsrm a01403; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t1404; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1405; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t1406; RV64ZVFHMIN-NEXT: ret1407 %v = call <vscale x 2 x double> @llvm.vp.roundeven.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)1408 ret <vscale x 2 x double> %v1409}1410 1411define <vscale x 2 x double> @vp_roundeven_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {1412; RV32ZVFH-LABEL: vp_roundeven_nxv2f64_unmasked:1413; RV32ZVFH: # %bb.0:1414; RV32ZVFH-NEXT: lui a1, %hi(.LCPI37_0)1415; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI37_0)(a1)1416; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1417; RV32ZVFH-NEXT: vfabs.v v10, v81418; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa51419; RV32ZVFH-NEXT: fsrmi a0, 01420; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t1421; RV32ZVFH-NEXT: fsrm a01422; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t1423; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1424; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t1425; RV32ZVFH-NEXT: ret1426;1427; RV64ZVFH-LABEL: vp_roundeven_nxv2f64_unmasked:1428; RV64ZVFH: # %bb.0:1429; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1430; RV64ZVFH-NEXT: vfabs.v v10, v81431; RV64ZVFH-NEXT: li a0, 10751432; RV64ZVFH-NEXT: slli a0, a0, 521433; RV64ZVFH-NEXT: fmv.d.x fa5, a01434; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa51435; RV64ZVFH-NEXT: fsrmi a0, 01436; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t1437; RV64ZVFH-NEXT: fsrm a01438; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t1439; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1440; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t1441; RV64ZVFH-NEXT: ret1442;1443; RV32ZVFHMIN-LABEL: vp_roundeven_nxv2f64_unmasked:1444; RV32ZVFHMIN: # %bb.0:1445; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI37_0)1446; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI37_0)(a1)1447; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma1448; RV32ZVFHMIN-NEXT: vfabs.v v10, v81449; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa51450; RV32ZVFHMIN-NEXT: fsrmi a0, 01451; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t1452; RV32ZVFHMIN-NEXT: fsrm a01453; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t1454; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1455; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t1456; RV32ZVFHMIN-NEXT: ret1457;1458; RV64ZVFHMIN-LABEL: vp_roundeven_nxv2f64_unmasked:1459; RV64ZVFHMIN: # %bb.0:1460; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma1461; RV64ZVFHMIN-NEXT: vfabs.v v10, v81462; RV64ZVFHMIN-NEXT: li a0, 10751463; RV64ZVFHMIN-NEXT: slli a0, a0, 521464; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01465; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa51466; RV64ZVFHMIN-NEXT: fsrmi a0, 01467; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t1468; RV64ZVFHMIN-NEXT: fsrm a01469; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t1470; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu1471; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t1472; RV64ZVFHMIN-NEXT: ret1473 %v = call <vscale x 2 x double> @llvm.vp.roundeven.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)1474 ret <vscale x 2 x double> %v1475}1476 1477define <vscale x 4 x double> @vp_roundeven_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1478; RV32ZVFH-LABEL: vp_roundeven_nxv4f64:1479; RV32ZVFH: # %bb.0:1480; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1481; RV32ZVFH-NEXT: vmv1r.v v12, v01482; RV32ZVFH-NEXT: lui a0, %hi(.LCPI38_0)1483; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI38_0)(a0)1484; RV32ZVFH-NEXT: vfabs.v v16, v8, v0.t1485; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1486; RV32ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t1487; RV32ZVFH-NEXT: fsrmi a0, 01488; RV32ZVFH-NEXT: vmv1r.v v0, v121489; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, ma1490; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1491; RV32ZVFH-NEXT: fsrm a01492; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1493; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1494; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1495; RV32ZVFH-NEXT: ret1496;1497; RV64ZVFH-LABEL: vp_roundeven_nxv4f64:1498; RV64ZVFH: # %bb.0:1499; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1500; RV64ZVFH-NEXT: vmv1r.v v12, v01501; RV64ZVFH-NEXT: vfabs.v v16, v8, v0.t1502; RV64ZVFH-NEXT: li a0, 10751503; RV64ZVFH-NEXT: slli a0, a0, 521504; RV64ZVFH-NEXT: fmv.d.x fa5, a01505; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1506; RV64ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t1507; RV64ZVFH-NEXT: fsrmi a0, 01508; RV64ZVFH-NEXT: vmv1r.v v0, v121509; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, ma1510; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1511; RV64ZVFH-NEXT: fsrm a01512; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1513; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1514; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1515; RV64ZVFH-NEXT: ret1516;1517; RV32ZVFHMIN-LABEL: vp_roundeven_nxv4f64:1518; RV32ZVFHMIN: # %bb.0:1519; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma1520; RV32ZVFHMIN-NEXT: vmv1r.v v12, v01521; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI38_0)1522; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI38_0)(a0)1523; RV32ZVFHMIN-NEXT: vfabs.v v16, v8, v0.t1524; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1525; RV32ZVFHMIN-NEXT: vmflt.vf v12, v16, fa5, v0.t1526; RV32ZVFHMIN-NEXT: fsrmi a0, 01527; RV32ZVFHMIN-NEXT: vmv1r.v v0, v121528; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, ma1529; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1530; RV32ZVFHMIN-NEXT: fsrm a01531; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1532; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1533; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1534; RV32ZVFHMIN-NEXT: ret1535;1536; RV64ZVFHMIN-LABEL: vp_roundeven_nxv4f64:1537; RV64ZVFHMIN: # %bb.0:1538; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma1539; RV64ZVFHMIN-NEXT: vmv1r.v v12, v01540; RV64ZVFHMIN-NEXT: vfabs.v v16, v8, v0.t1541; RV64ZVFHMIN-NEXT: li a0, 10751542; RV64ZVFHMIN-NEXT: slli a0, a0, 521543; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01544; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1545; RV64ZVFHMIN-NEXT: vmflt.vf v12, v16, fa5, v0.t1546; RV64ZVFHMIN-NEXT: fsrmi a0, 01547; RV64ZVFHMIN-NEXT: vmv1r.v v0, v121548; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, ma1549; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1550; RV64ZVFHMIN-NEXT: fsrm a01551; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1552; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1553; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1554; RV64ZVFHMIN-NEXT: ret1555 %v = call <vscale x 4 x double> @llvm.vp.roundeven.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 %evl)1556 ret <vscale x 4 x double> %v1557}1558 1559define <vscale x 4 x double> @vp_roundeven_nxv4f64_unmasked(<vscale x 4 x double> %va, i32 zeroext %evl) {1560; RV32ZVFH-LABEL: vp_roundeven_nxv4f64_unmasked:1561; RV32ZVFH: # %bb.0:1562; RV32ZVFH-NEXT: lui a1, %hi(.LCPI39_0)1563; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI39_0)(a1)1564; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1565; RV32ZVFH-NEXT: vfabs.v v12, v81566; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa51567; RV32ZVFH-NEXT: fsrmi a0, 01568; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1569; RV32ZVFH-NEXT: fsrm a01570; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1571; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1572; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1573; RV32ZVFH-NEXT: ret1574;1575; RV64ZVFH-LABEL: vp_roundeven_nxv4f64_unmasked:1576; RV64ZVFH: # %bb.0:1577; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1578; RV64ZVFH-NEXT: vfabs.v v12, v81579; RV64ZVFH-NEXT: li a0, 10751580; RV64ZVFH-NEXT: slli a0, a0, 521581; RV64ZVFH-NEXT: fmv.d.x fa5, a01582; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa51583; RV64ZVFH-NEXT: fsrmi a0, 01584; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1585; RV64ZVFH-NEXT: fsrm a01586; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1587; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1588; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1589; RV64ZVFH-NEXT: ret1590;1591; RV32ZVFHMIN-LABEL: vp_roundeven_nxv4f64_unmasked:1592; RV32ZVFHMIN: # %bb.0:1593; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI39_0)1594; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI39_0)(a1)1595; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma1596; RV32ZVFHMIN-NEXT: vfabs.v v12, v81597; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa51598; RV32ZVFHMIN-NEXT: fsrmi a0, 01599; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t1600; RV32ZVFHMIN-NEXT: fsrm a01601; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t1602; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1603; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t1604; RV32ZVFHMIN-NEXT: ret1605;1606; RV64ZVFHMIN-LABEL: vp_roundeven_nxv4f64_unmasked:1607; RV64ZVFHMIN: # %bb.0:1608; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma1609; RV64ZVFHMIN-NEXT: vfabs.v v12, v81610; RV64ZVFHMIN-NEXT: li a0, 10751611; RV64ZVFHMIN-NEXT: slli a0, a0, 521612; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01613; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa51614; RV64ZVFHMIN-NEXT: fsrmi a0, 01615; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t1616; RV64ZVFHMIN-NEXT: fsrm a01617; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t1618; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu1619; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t1620; RV64ZVFHMIN-NEXT: ret1621 %v = call <vscale x 4 x double> @llvm.vp.roundeven.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)1622 ret <vscale x 4 x double> %v1623}1624 1625define <vscale x 7 x double> @vp_roundeven_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {1626; RV32ZVFH-LABEL: vp_roundeven_nxv7f64:1627; RV32ZVFH: # %bb.0:1628; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1629; RV32ZVFH-NEXT: vmv1r.v v16, v01630; RV32ZVFH-NEXT: lui a0, %hi(.LCPI40_0)1631; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI40_0)(a0)1632; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t1633; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1634; RV32ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1635; RV32ZVFH-NEXT: fsrmi a0, 01636; RV32ZVFH-NEXT: vmv1r.v v0, v161637; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1638; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1639; RV32ZVFH-NEXT: fsrm a01640; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1641; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1642; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1643; RV32ZVFH-NEXT: ret1644;1645; RV64ZVFH-LABEL: vp_roundeven_nxv7f64:1646; RV64ZVFH: # %bb.0:1647; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1648; RV64ZVFH-NEXT: vmv1r.v v16, v01649; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t1650; RV64ZVFH-NEXT: li a0, 10751651; RV64ZVFH-NEXT: slli a0, a0, 521652; RV64ZVFH-NEXT: fmv.d.x fa5, a01653; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1654; RV64ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1655; RV64ZVFH-NEXT: fsrmi a0, 01656; RV64ZVFH-NEXT: vmv1r.v v0, v161657; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1658; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1659; RV64ZVFH-NEXT: fsrm a01660; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1661; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1662; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1663; RV64ZVFH-NEXT: ret1664;1665; RV32ZVFHMIN-LABEL: vp_roundeven_nxv7f64:1666; RV32ZVFHMIN: # %bb.0:1667; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1668; RV32ZVFHMIN-NEXT: vmv1r.v v16, v01669; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI40_0)1670; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI40_0)(a0)1671; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1672; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1673; RV32ZVFHMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1674; RV32ZVFHMIN-NEXT: fsrmi a0, 01675; RV32ZVFHMIN-NEXT: vmv1r.v v0, v161676; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1677; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1678; RV32ZVFHMIN-NEXT: fsrm a01679; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1680; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1681; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1682; RV32ZVFHMIN-NEXT: ret1683;1684; RV64ZVFHMIN-LABEL: vp_roundeven_nxv7f64:1685; RV64ZVFHMIN: # %bb.0:1686; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1687; RV64ZVFHMIN-NEXT: vmv1r.v v16, v01688; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1689; RV64ZVFHMIN-NEXT: li a0, 10751690; RV64ZVFHMIN-NEXT: slli a0, a0, 521691; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01692; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1693; RV64ZVFHMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1694; RV64ZVFHMIN-NEXT: fsrmi a0, 01695; RV64ZVFHMIN-NEXT: vmv1r.v v0, v161696; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1697; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1698; RV64ZVFHMIN-NEXT: fsrm a01699; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1700; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1701; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1702; RV64ZVFHMIN-NEXT: ret1703 %v = call <vscale x 7 x double> @llvm.vp.roundeven.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)1704 ret <vscale x 7 x double> %v1705}1706 1707define <vscale x 7 x double> @vp_roundeven_nxv7f64_unmasked(<vscale x 7 x double> %va, i32 zeroext %evl) {1708; RV32ZVFH-LABEL: vp_roundeven_nxv7f64_unmasked:1709; RV32ZVFH: # %bb.0:1710; RV32ZVFH-NEXT: lui a1, %hi(.LCPI41_0)1711; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI41_0)(a1)1712; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1713; RV32ZVFH-NEXT: vfabs.v v16, v81714; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa51715; RV32ZVFH-NEXT: fsrmi a0, 01716; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1717; RV32ZVFH-NEXT: fsrm a01718; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1719; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1720; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1721; RV32ZVFH-NEXT: ret1722;1723; RV64ZVFH-LABEL: vp_roundeven_nxv7f64_unmasked:1724; RV64ZVFH: # %bb.0:1725; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1726; RV64ZVFH-NEXT: vfabs.v v16, v81727; RV64ZVFH-NEXT: li a0, 10751728; RV64ZVFH-NEXT: slli a0, a0, 521729; RV64ZVFH-NEXT: fmv.d.x fa5, a01730; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa51731; RV64ZVFH-NEXT: fsrmi a0, 01732; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1733; RV64ZVFH-NEXT: fsrm a01734; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1735; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1736; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1737; RV64ZVFH-NEXT: ret1738;1739; RV32ZVFHMIN-LABEL: vp_roundeven_nxv7f64_unmasked:1740; RV32ZVFHMIN: # %bb.0:1741; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI41_0)1742; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI41_0)(a1)1743; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1744; RV32ZVFHMIN-NEXT: vfabs.v v16, v81745; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa51746; RV32ZVFHMIN-NEXT: fsrmi a0, 01747; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1748; RV32ZVFHMIN-NEXT: fsrm a01749; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1750; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1751; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1752; RV32ZVFHMIN-NEXT: ret1753;1754; RV64ZVFHMIN-LABEL: vp_roundeven_nxv7f64_unmasked:1755; RV64ZVFHMIN: # %bb.0:1756; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1757; RV64ZVFHMIN-NEXT: vfabs.v v16, v81758; RV64ZVFHMIN-NEXT: li a0, 10751759; RV64ZVFHMIN-NEXT: slli a0, a0, 521760; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01761; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa51762; RV64ZVFHMIN-NEXT: fsrmi a0, 01763; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1764; RV64ZVFHMIN-NEXT: fsrm a01765; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1766; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1767; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1768; RV64ZVFHMIN-NEXT: ret1769 %v = call <vscale x 7 x double> @llvm.vp.roundeven.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)1770 ret <vscale x 7 x double> %v1771}1772 1773define <vscale x 8 x double> @vp_roundeven_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1774; RV32ZVFH-LABEL: vp_roundeven_nxv8f64:1775; RV32ZVFH: # %bb.0:1776; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1777; RV32ZVFH-NEXT: vmv1r.v v16, v01778; RV32ZVFH-NEXT: lui a0, %hi(.LCPI42_0)1779; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI42_0)(a0)1780; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t1781; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1782; RV32ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1783; RV32ZVFH-NEXT: fsrmi a0, 01784; RV32ZVFH-NEXT: vmv1r.v v0, v161785; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1786; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1787; RV32ZVFH-NEXT: fsrm a01788; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1789; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1790; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1791; RV32ZVFH-NEXT: ret1792;1793; RV64ZVFH-LABEL: vp_roundeven_nxv8f64:1794; RV64ZVFH: # %bb.0:1795; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1796; RV64ZVFH-NEXT: vmv1r.v v16, v01797; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t1798; RV64ZVFH-NEXT: li a0, 10751799; RV64ZVFH-NEXT: slli a0, a0, 521800; RV64ZVFH-NEXT: fmv.d.x fa5, a01801; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1802; RV64ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1803; RV64ZVFH-NEXT: fsrmi a0, 01804; RV64ZVFH-NEXT: vmv1r.v v0, v161805; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1806; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1807; RV64ZVFH-NEXT: fsrm a01808; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1809; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1810; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1811; RV64ZVFH-NEXT: ret1812;1813; RV32ZVFHMIN-LABEL: vp_roundeven_nxv8f64:1814; RV32ZVFHMIN: # %bb.0:1815; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1816; RV32ZVFHMIN-NEXT: vmv1r.v v16, v01817; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI42_0)1818; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI42_0)(a0)1819; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1820; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1821; RV32ZVFHMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1822; RV32ZVFHMIN-NEXT: fsrmi a0, 01823; RV32ZVFHMIN-NEXT: vmv1r.v v0, v161824; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1825; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1826; RV32ZVFHMIN-NEXT: fsrm a01827; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1828; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1829; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1830; RV32ZVFHMIN-NEXT: ret1831;1832; RV64ZVFHMIN-LABEL: vp_roundeven_nxv8f64:1833; RV64ZVFHMIN: # %bb.0:1834; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1835; RV64ZVFHMIN-NEXT: vmv1r.v v16, v01836; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t1837; RV64ZVFHMIN-NEXT: li a0, 10751838; RV64ZVFHMIN-NEXT: slli a0, a0, 521839; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01840; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1841; RV64ZVFHMIN-NEXT: vmflt.vf v16, v24, fa5, v0.t1842; RV64ZVFHMIN-NEXT: fsrmi a0, 01843; RV64ZVFHMIN-NEXT: vmv1r.v v0, v161844; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma1845; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t1846; RV64ZVFHMIN-NEXT: fsrm a01847; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t1848; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1849; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t1850; RV64ZVFHMIN-NEXT: ret1851 %v = call <vscale x 8 x double> @llvm.vp.roundeven.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)1852 ret <vscale x 8 x double> %v1853}1854 1855define <vscale x 8 x double> @vp_roundeven_nxv8f64_unmasked(<vscale x 8 x double> %va, i32 zeroext %evl) {1856; RV32ZVFH-LABEL: vp_roundeven_nxv8f64_unmasked:1857; RV32ZVFH: # %bb.0:1858; RV32ZVFH-NEXT: lui a1, %hi(.LCPI43_0)1859; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI43_0)(a1)1860; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1861; RV32ZVFH-NEXT: vfabs.v v16, v81862; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa51863; RV32ZVFH-NEXT: fsrmi a0, 01864; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1865; RV32ZVFH-NEXT: fsrm a01866; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1867; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1868; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1869; RV32ZVFH-NEXT: ret1870;1871; RV64ZVFH-LABEL: vp_roundeven_nxv8f64_unmasked:1872; RV64ZVFH: # %bb.0:1873; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1874; RV64ZVFH-NEXT: vfabs.v v16, v81875; RV64ZVFH-NEXT: li a0, 10751876; RV64ZVFH-NEXT: slli a0, a0, 521877; RV64ZVFH-NEXT: fmv.d.x fa5, a01878; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa51879; RV64ZVFH-NEXT: fsrmi a0, 01880; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1881; RV64ZVFH-NEXT: fsrm a01882; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1883; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1884; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1885; RV64ZVFH-NEXT: ret1886;1887; RV32ZVFHMIN-LABEL: vp_roundeven_nxv8f64_unmasked:1888; RV32ZVFHMIN: # %bb.0:1889; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI43_0)1890; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI43_0)(a1)1891; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1892; RV32ZVFHMIN-NEXT: vfabs.v v16, v81893; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa51894; RV32ZVFHMIN-NEXT: fsrmi a0, 01895; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1896; RV32ZVFHMIN-NEXT: fsrm a01897; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1898; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1899; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1900; RV32ZVFHMIN-NEXT: ret1901;1902; RV64ZVFHMIN-LABEL: vp_roundeven_nxv8f64_unmasked:1903; RV64ZVFHMIN: # %bb.0:1904; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma1905; RV64ZVFHMIN-NEXT: vfabs.v v16, v81906; RV64ZVFHMIN-NEXT: li a0, 10751907; RV64ZVFHMIN-NEXT: slli a0, a0, 521908; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a01909; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa51910; RV64ZVFHMIN-NEXT: fsrmi a0, 01911; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t1912; RV64ZVFHMIN-NEXT: fsrm a01913; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t1914; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu1915; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t1916; RV64ZVFHMIN-NEXT: ret1917 %v = call <vscale x 8 x double> @llvm.vp.roundeven.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)1918 ret <vscale x 8 x double> %v1919}1920 1921; Test splitting.1922 1923define <vscale x 16 x double> @vp_roundeven_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1924; RV32ZVFH-LABEL: vp_roundeven_nxv16f64:1925; RV32ZVFH: # %bb.0:1926; RV32ZVFH-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1927; RV32ZVFH-NEXT: vmv1r.v v7, v01928; RV32ZVFH-NEXT: csrr a1, vlenb1929; RV32ZVFH-NEXT: lui a2, %hi(.LCPI44_0)1930; RV32ZVFH-NEXT: srli a3, a1, 31931; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI44_0)(a2)1932; RV32ZVFH-NEXT: sub a2, a0, a11933; RV32ZVFH-NEXT: vslidedown.vx v6, v0, a31934; RV32ZVFH-NEXT: sltu a3, a0, a21935; RV32ZVFH-NEXT: addi a3, a3, -11936; RV32ZVFH-NEXT: and a2, a3, a21937; RV32ZVFH-NEXT: vmv1r.v v0, v61938; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma1939; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t1940; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1941; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t1942; RV32ZVFH-NEXT: fsrmi a2, 01943; RV32ZVFH-NEXT: vmv1r.v v0, v61944; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1945; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1946; RV32ZVFH-NEXT: fsrm a21947; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1948; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1949; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1950; RV32ZVFH-NEXT: bltu a0, a1, .LBB44_21951; RV32ZVFH-NEXT: # %bb.1:1952; RV32ZVFH-NEXT: mv a0, a11953; RV32ZVFH-NEXT: .LBB44_2:1954; RV32ZVFH-NEXT: vmv1r.v v0, v71955; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1956; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t1957; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1958; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t1959; RV32ZVFH-NEXT: fsrmi a0, 01960; RV32ZVFH-NEXT: vmv1r.v v0, v71961; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1962; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1963; RV32ZVFH-NEXT: fsrm a01964; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1965; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1966; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1967; RV32ZVFH-NEXT: ret1968;1969; RV64ZVFH-LABEL: vp_roundeven_nxv16f64:1970; RV64ZVFH: # %bb.0:1971; RV64ZVFH-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1972; RV64ZVFH-NEXT: vmv1r.v v7, v01973; RV64ZVFH-NEXT: csrr a1, vlenb1974; RV64ZVFH-NEXT: li a2, 10751975; RV64ZVFH-NEXT: srli a3, a1, 31976; RV64ZVFH-NEXT: vslidedown.vx v6, v0, a31977; RV64ZVFH-NEXT: sub a3, a0, a11978; RV64ZVFH-NEXT: slli a2, a2, 521979; RV64ZVFH-NEXT: fmv.d.x fa5, a21980; RV64ZVFH-NEXT: sltu a2, a0, a31981; RV64ZVFH-NEXT: addi a2, a2, -11982; RV64ZVFH-NEXT: and a2, a2, a31983; RV64ZVFH-NEXT: vmv1r.v v0, v61984; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma1985; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t1986; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1987; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t1988; RV64ZVFH-NEXT: fsrmi a2, 01989; RV64ZVFH-NEXT: vmv1r.v v0, v61990; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1991; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1992; RV64ZVFH-NEXT: fsrm a21993; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1994; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1995; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1996; RV64ZVFH-NEXT: bltu a0, a1, .LBB44_21997; RV64ZVFH-NEXT: # %bb.1:1998; RV64ZVFH-NEXT: mv a0, a11999; RV64ZVFH-NEXT: .LBB44_2:2000; RV64ZVFH-NEXT: vmv1r.v v0, v72001; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma2002; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t2003; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu2004; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t2005; RV64ZVFH-NEXT: fsrmi a0, 02006; RV64ZVFH-NEXT: vmv1r.v v0, v72007; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma2008; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t2009; RV64ZVFH-NEXT: fsrm a02010; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t2011; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu2012; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t2013; RV64ZVFH-NEXT: ret2014;2015; RV32ZVFHMIN-LABEL: vp_roundeven_nxv16f64:2016; RV32ZVFHMIN: # %bb.0:2017; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf4, ta, ma2018; RV32ZVFHMIN-NEXT: vmv1r.v v7, v02019; RV32ZVFHMIN-NEXT: csrr a1, vlenb2020; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI44_0)2021; RV32ZVFHMIN-NEXT: srli a3, a1, 32022; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI44_0)(a2)2023; RV32ZVFHMIN-NEXT: sub a2, a0, a12024; RV32ZVFHMIN-NEXT: vslidedown.vx v6, v0, a32025; RV32ZVFHMIN-NEXT: sltu a3, a0, a22026; RV32ZVFHMIN-NEXT: addi a3, a3, -12027; RV32ZVFHMIN-NEXT: and a2, a3, a22028; RV32ZVFHMIN-NEXT: vmv1r.v v0, v62029; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma2030; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t2031; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2032; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t2033; RV32ZVFHMIN-NEXT: fsrmi a2, 02034; RV32ZVFHMIN-NEXT: vmv1r.v v0, v62035; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma2036; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t2037; RV32ZVFHMIN-NEXT: fsrm a22038; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t2039; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2040; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t2041; RV32ZVFHMIN-NEXT: bltu a0, a1, .LBB44_22042; RV32ZVFHMIN-NEXT: # %bb.1:2043; RV32ZVFHMIN-NEXT: mv a0, a12044; RV32ZVFHMIN-NEXT: .LBB44_2:2045; RV32ZVFHMIN-NEXT: vmv1r.v v0, v72046; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma2047; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t2048; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2049; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t2050; RV32ZVFHMIN-NEXT: fsrmi a0, 02051; RV32ZVFHMIN-NEXT: vmv1r.v v0, v72052; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma2053; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t2054; RV32ZVFHMIN-NEXT: fsrm a02055; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t2056; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2057; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t2058; RV32ZVFHMIN-NEXT: ret2059;2060; RV64ZVFHMIN-LABEL: vp_roundeven_nxv16f64:2061; RV64ZVFHMIN: # %bb.0:2062; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf4, ta, ma2063; RV64ZVFHMIN-NEXT: vmv1r.v v7, v02064; RV64ZVFHMIN-NEXT: csrr a1, vlenb2065; RV64ZVFHMIN-NEXT: li a2, 10752066; RV64ZVFHMIN-NEXT: srli a3, a1, 32067; RV64ZVFHMIN-NEXT: vslidedown.vx v6, v0, a32068; RV64ZVFHMIN-NEXT: sub a3, a0, a12069; RV64ZVFHMIN-NEXT: slli a2, a2, 522070; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a22071; RV64ZVFHMIN-NEXT: sltu a2, a0, a32072; RV64ZVFHMIN-NEXT: addi a2, a2, -12073; RV64ZVFHMIN-NEXT: and a2, a2, a32074; RV64ZVFHMIN-NEXT: vmv1r.v v0, v62075; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma2076; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t2077; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2078; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t2079; RV64ZVFHMIN-NEXT: fsrmi a2, 02080; RV64ZVFHMIN-NEXT: vmv1r.v v0, v62081; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma2082; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t2083; RV64ZVFHMIN-NEXT: fsrm a22084; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t2085; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2086; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t2087; RV64ZVFHMIN-NEXT: bltu a0, a1, .LBB44_22088; RV64ZVFHMIN-NEXT: # %bb.1:2089; RV64ZVFHMIN-NEXT: mv a0, a12090; RV64ZVFHMIN-NEXT: .LBB44_2:2091; RV64ZVFHMIN-NEXT: vmv1r.v v0, v72092; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma2093; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t2094; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2095; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t2096; RV64ZVFHMIN-NEXT: fsrmi a0, 02097; RV64ZVFHMIN-NEXT: vmv1r.v v0, v72098; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma2099; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t2100; RV64ZVFHMIN-NEXT: fsrm a02101; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t2102; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2103; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t2104; RV64ZVFHMIN-NEXT: ret2105 %v = call <vscale x 16 x double> @llvm.vp.roundeven.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)2106 ret <vscale x 16 x double> %v2107}2108 2109define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x double> %va, i32 zeroext %evl) {2110; RV32ZVFH-LABEL: vp_roundeven_nxv16f64_unmasked:2111; RV32ZVFH: # %bb.0:2112; RV32ZVFH-NEXT: csrr a1, vlenb2113; RV32ZVFH-NEXT: lui a2, %hi(.LCPI45_0)2114; RV32ZVFH-NEXT: sub a3, a0, a12115; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI45_0)(a2)2116; RV32ZVFH-NEXT: sltu a2, a0, a32117; RV32ZVFH-NEXT: addi a2, a2, -12118; RV32ZVFH-NEXT: and a2, a2, a32119; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma2120; RV32ZVFH-NEXT: vfabs.v v24, v162121; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa52122; RV32ZVFH-NEXT: fsrmi a2, 02123; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t2124; RV32ZVFH-NEXT: fsrm a22125; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t2126; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu2127; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t2128; RV32ZVFH-NEXT: bltu a0, a1, .LBB45_22129; RV32ZVFH-NEXT: # %bb.1:2130; RV32ZVFH-NEXT: mv a0, a12131; RV32ZVFH-NEXT: .LBB45_2:2132; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma2133; RV32ZVFH-NEXT: vfabs.v v24, v82134; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa52135; RV32ZVFH-NEXT: fsrmi a0, 02136; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t2137; RV32ZVFH-NEXT: fsrm a02138; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t2139; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu2140; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t2141; RV32ZVFH-NEXT: ret2142;2143; RV64ZVFH-LABEL: vp_roundeven_nxv16f64_unmasked:2144; RV64ZVFH: # %bb.0:2145; RV64ZVFH-NEXT: csrr a1, vlenb2146; RV64ZVFH-NEXT: li a2, 10752147; RV64ZVFH-NEXT: sub a3, a0, a12148; RV64ZVFH-NEXT: slli a2, a2, 522149; RV64ZVFH-NEXT: fmv.d.x fa5, a22150; RV64ZVFH-NEXT: sltu a2, a0, a32151; RV64ZVFH-NEXT: addi a2, a2, -12152; RV64ZVFH-NEXT: and a2, a2, a32153; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma2154; RV64ZVFH-NEXT: vfabs.v v24, v162155; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa52156; RV64ZVFH-NEXT: fsrmi a2, 02157; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t2158; RV64ZVFH-NEXT: fsrm a22159; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t2160; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu2161; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t2162; RV64ZVFH-NEXT: bltu a0, a1, .LBB45_22163; RV64ZVFH-NEXT: # %bb.1:2164; RV64ZVFH-NEXT: mv a0, a12165; RV64ZVFH-NEXT: .LBB45_2:2166; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma2167; RV64ZVFH-NEXT: vfabs.v v24, v82168; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa52169; RV64ZVFH-NEXT: fsrmi a0, 02170; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t2171; RV64ZVFH-NEXT: fsrm a02172; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t2173; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu2174; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t2175; RV64ZVFH-NEXT: ret2176;2177; RV32ZVFHMIN-LABEL: vp_roundeven_nxv16f64_unmasked:2178; RV32ZVFHMIN: # %bb.0:2179; RV32ZVFHMIN-NEXT: csrr a1, vlenb2180; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI45_0)2181; RV32ZVFHMIN-NEXT: sub a3, a0, a12182; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI45_0)(a2)2183; RV32ZVFHMIN-NEXT: sltu a2, a0, a32184; RV32ZVFHMIN-NEXT: addi a2, a2, -12185; RV32ZVFHMIN-NEXT: and a2, a2, a32186; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma2187; RV32ZVFHMIN-NEXT: vfabs.v v24, v162188; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa52189; RV32ZVFHMIN-NEXT: fsrmi a2, 02190; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t2191; RV32ZVFHMIN-NEXT: fsrm a22192; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t2193; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2194; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t2195; RV32ZVFHMIN-NEXT: bltu a0, a1, .LBB45_22196; RV32ZVFHMIN-NEXT: # %bb.1:2197; RV32ZVFHMIN-NEXT: mv a0, a12198; RV32ZVFHMIN-NEXT: .LBB45_2:2199; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma2200; RV32ZVFHMIN-NEXT: vfabs.v v24, v82201; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa52202; RV32ZVFHMIN-NEXT: fsrmi a0, 02203; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t2204; RV32ZVFHMIN-NEXT: fsrm a02205; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t2206; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2207; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t2208; RV32ZVFHMIN-NEXT: ret2209;2210; RV64ZVFHMIN-LABEL: vp_roundeven_nxv16f64_unmasked:2211; RV64ZVFHMIN: # %bb.0:2212; RV64ZVFHMIN-NEXT: csrr a1, vlenb2213; RV64ZVFHMIN-NEXT: li a2, 10752214; RV64ZVFHMIN-NEXT: sub a3, a0, a12215; RV64ZVFHMIN-NEXT: slli a2, a2, 522216; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a22217; RV64ZVFHMIN-NEXT: sltu a2, a0, a32218; RV64ZVFHMIN-NEXT: addi a2, a2, -12219; RV64ZVFHMIN-NEXT: and a2, a2, a32220; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma2221; RV64ZVFHMIN-NEXT: vfabs.v v24, v162222; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa52223; RV64ZVFHMIN-NEXT: fsrmi a2, 02224; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t2225; RV64ZVFHMIN-NEXT: fsrm a22226; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t2227; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2228; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t2229; RV64ZVFHMIN-NEXT: bltu a0, a1, .LBB45_22230; RV64ZVFHMIN-NEXT: # %bb.1:2231; RV64ZVFHMIN-NEXT: mv a0, a12232; RV64ZVFHMIN-NEXT: .LBB45_2:2233; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma2234; RV64ZVFHMIN-NEXT: vfabs.v v24, v82235; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa52236; RV64ZVFHMIN-NEXT: fsrmi a0, 02237; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t2238; RV64ZVFHMIN-NEXT: fsrm a02239; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t2240; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu2241; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t2242; RV64ZVFHMIN-NEXT: ret2243 %v = call <vscale x 16 x double> @llvm.vp.roundeven.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)2244 ret <vscale x 16 x double> %v2245}2246