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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s3 4define void @rvv_vla(i64 %n, i64 %i) nounwind {5; CHECK-LABEL: rvv_vla:6; CHECK: # %bb.0:7; CHECK-NEXT: addi sp, sp, -328; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill9; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill10; CHECK-NEXT: addi s0, sp, 3211; CHECK-NEXT: csrr a2, vlenb12; CHECK-NEXT: slli a2, a2, 213; CHECK-NEXT: sub sp, sp, a214; CHECK-NEXT: slli a0, a0, 215; CHECK-NEXT: addi a0, a0, 1516; CHECK-NEXT: andi a0, a0, -1617; CHECK-NEXT: sub a0, sp, a018; CHECK-NEXT: mv sp, a019; CHECK-NEXT: csrr a2, vlenb20; CHECK-NEXT: sub a2, s0, a221; CHECK-NEXT: addi a2, a2, -3222; CHECK-NEXT: vl1re64.v v8, (a2)23; CHECK-NEXT: csrr a2, vlenb24; CHECK-NEXT: slli a2, a2, 225; CHECK-NEXT: sub a2, s0, a226; CHECK-NEXT: addi a2, a2, -3227; CHECK-NEXT: slli a1, a1, 228; CHECK-NEXT: vl2re64.v v8, (a2)29; CHECK-NEXT: add a0, a0, a130; CHECK-NEXT: lw zero, 0(a0)31; CHECK-NEXT: addi sp, s0, -3232; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload33; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload34; CHECK-NEXT: addi sp, sp, 3235; CHECK-NEXT: ret36 %vla.addr = alloca i32, i64 %n37 38 %v1.addr = alloca <vscale x 1 x i64>39 %v1 = load volatile <vscale x 1 x i64>, ptr %v1.addr40 41 %v2.addr = alloca <vscale x 2 x i64>42 %v2 = load volatile <vscale x 2 x i64>, ptr %v2.addr43 44 %p = getelementptr i32, ptr %vla.addr, i64 %i45 %s = load volatile i32, ptr %p46 ret void47}48 49define void @rvv_overaligned() nounwind {50; CHECK-LABEL: rvv_overaligned:51; CHECK: # %bb.0:52; CHECK-NEXT: addi sp, sp, -12853; CHECK-NEXT: sd ra, 120(sp) # 8-byte Folded Spill54; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill55; CHECK-NEXT: addi s0, sp, 12856; CHECK-NEXT: csrr a0, vlenb57; CHECK-NEXT: slli a0, a0, 258; CHECK-NEXT: sub sp, sp, a059; CHECK-NEXT: andi sp, sp, -6460; CHECK-NEXT: csrr a0, vlenb61; CHECK-NEXT: slli a1, a0, 162; CHECK-NEXT: add a0, a1, a063; CHECK-NEXT: add a0, sp, a064; CHECK-NEXT: addi a0, a0, 11265; CHECK-NEXT: vl1re64.v v8, (a0)66; CHECK-NEXT: addi a0, sp, 11267; CHECK-NEXT: vl2re64.v v8, (a0)68; CHECK-NEXT: lw zero, 64(sp)69; CHECK-NEXT: addi sp, s0, -12870; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload71; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload72; CHECK-NEXT: addi sp, sp, 12873; CHECK-NEXT: ret74 %overaligned = alloca i32, align 6475 76 %v1.addr = alloca <vscale x 1 x i64>77 %v1 = load volatile <vscale x 1 x i64>, ptr %v1.addr78 79 %v2.addr = alloca <vscale x 2 x i64>80 %v2 = load volatile <vscale x 2 x i64>, ptr %v2.addr81 82 %s = load volatile i32, ptr %overaligned, align 6483 ret void84}85 86define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {87; CHECK-LABEL: rvv_vla_and_overaligned:88; CHECK: # %bb.0:89; CHECK-NEXT: addi sp, sp, -14490; CHECK-NEXT: sd ra, 136(sp) # 8-byte Folded Spill91; CHECK-NEXT: sd s0, 128(sp) # 8-byte Folded Spill92; CHECK-NEXT: sd s1, 120(sp) # 8-byte Folded Spill93; CHECK-NEXT: addi s0, sp, 14494; CHECK-NEXT: csrr a2, vlenb95; CHECK-NEXT: slli a2, a2, 296; CHECK-NEXT: sub sp, sp, a297; CHECK-NEXT: andi sp, sp, -6498; CHECK-NEXT: mv s1, sp99; CHECK-NEXT: slli a0, a0, 2100; CHECK-NEXT: addi a0, a0, 15101; CHECK-NEXT: andi a0, a0, -16102; CHECK-NEXT: sub a0, sp, a0103; CHECK-NEXT: mv sp, a0104; CHECK-NEXT: csrr a2, vlenb105; CHECK-NEXT: slli a3, a2, 1106; CHECK-NEXT: add a2, a3, a2107; CHECK-NEXT: add a2, s1, a2108; CHECK-NEXT: addi a2, a2, 112109; CHECK-NEXT: vl1re64.v v8, (a2)110; CHECK-NEXT: addi a2, s1, 112111; CHECK-NEXT: slli a1, a1, 2112; CHECK-NEXT: vl2re64.v v8, (a2)113; CHECK-NEXT: lw zero, 64(s1)114; CHECK-NEXT: add a0, a0, a1115; CHECK-NEXT: lw zero, 0(a0)116; CHECK-NEXT: addi sp, s0, -144117; CHECK-NEXT: ld ra, 136(sp) # 8-byte Folded Reload118; CHECK-NEXT: ld s0, 128(sp) # 8-byte Folded Reload119; CHECK-NEXT: ld s1, 120(sp) # 8-byte Folded Reload120; CHECK-NEXT: addi sp, sp, 144121; CHECK-NEXT: ret122 %overaligned = alloca i32, align 64123 %vla.addr = alloca i32, i64 %n124 125 %v1.addr = alloca <vscale x 1 x i64>126 %v1 = load volatile <vscale x 1 x i64>, ptr %v1.addr127 128 %v2.addr = alloca <vscale x 2 x i64>129 %v2 = load volatile <vscale x 2 x i64>, ptr %v2.addr130 131 %s1 = load volatile i32, ptr %overaligned, align 64132 %p = getelementptr i32, ptr %vla.addr, i64 %i133 %s2 = load volatile i32, ptr %p134 ret void135 136}137