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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple riscv32 -mattr=+m,+v < %s \3; RUN: | FileCheck %s4 5define i32 @vscale_zero() nounwind {6; CHECK-LABEL: vscale_zero:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: li a0, 09; CHECK-NEXT: ret10entry:11 %0 = call i32 @llvm.vscale.i32()12 %1 = mul i32 %0, 013 ret i32 %114}15 16define i32 @vscale_one() nounwind {17; CHECK-LABEL: vscale_one:18; CHECK: # %bb.0: # %entry19; CHECK-NEXT: csrr a0, vlenb20; CHECK-NEXT: srli a0, a0, 321; CHECK-NEXT: ret22entry:23 %0 = call i32 @llvm.vscale.i32()24 %1 = mul i32 %0, 125 ret i32 %126}27 28define i32 @vscale_uimmpow2xlen() nounwind {29; CHECK-LABEL: vscale_uimmpow2xlen:30; CHECK: # %bb.0: # %entry31; CHECK-NEXT: csrr a0, vlenb32; CHECK-NEXT: slli a0, a0, 333; CHECK-NEXT: ret34entry:35 %0 = call i32 @llvm.vscale.i32()36 %1 = mul i32 %0, 6437 ret i32 %138}39 40define i32 @vscale_non_pow2() nounwind {41; CHECK-LABEL: vscale_non_pow2:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: csrr a0, vlenb44; CHECK-NEXT: slli a1, a0, 145; CHECK-NEXT: add a0, a1, a046; CHECK-NEXT: ret47entry:48 %0 = call i32 @llvm.vscale.i32()49 %1 = mul i32 %0, 2450 ret i32 %151}52 53