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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple riscv64 -mattr=+m,+v < %s \3; RUN: | FileCheck %s -check-prefixes=RV64,RV64-VLENUNK4; RUN: llc -mtriple riscv32 -mattr=+m,+v < %s \5; RUN: | FileCheck %s -check-prefix=RV326; RUN: llc -mtriple riscv64 -mattr=+m,+v,+zvl256b < %s \7; RUN: | FileCheck %s -check-prefixes=RV64,RV64-VLEN256MIN8; RUN: llc -mtriple riscv64 -mattr=+m,+v -riscv-v-vector-bits-max=256 < %s \9; RUN: | FileCheck %s -check-prefixes=RV64,RV64-VLEN256MAX10; RUN: llc -mtriple riscv64 -mattr=+m,+v,+zvl256b -riscv-v-vector-bits-max=256 < %s \11; RUN: | FileCheck %s -check-prefixes=RV64-VLEN256EXACT12 13define i64 @vscale_zero() nounwind {14; RV64-LABEL: vscale_zero:15; RV64: # %bb.0: # %entry16; RV64-NEXT: li a0, 017; RV64-NEXT: ret18;19; RV32-LABEL: vscale_zero:20; RV32: # %bb.0: # %entry21; RV32-NEXT: li a0, 022; RV32-NEXT: li a1, 023; RV32-NEXT: ret24;25; RV64-VLEN256EXACT-LABEL: vscale_zero:26; RV64-VLEN256EXACT: # %bb.0: # %entry27; RV64-VLEN256EXACT-NEXT: li a0, 028; RV64-VLEN256EXACT-NEXT: ret29entry:30 %0 = call i64 @llvm.vscale.i64()31 %1 = mul i64 %0, 032 ret i64 %133}34 35define i64 @vscale_one() nounwind {36; RV64-LABEL: vscale_one:37; RV64: # %bb.0: # %entry38; RV64-NEXT: csrr a0, vlenb39; RV64-NEXT: srli a0, a0, 340; RV64-NEXT: ret41;42; RV32-LABEL: vscale_one:43; RV32: # %bb.0: # %entry44; RV32-NEXT: csrr a0, vlenb45; RV32-NEXT: srli a0, a0, 346; RV32-NEXT: li a1, 047; RV32-NEXT: ret48;49; RV64-VLEN256EXACT-LABEL: vscale_one:50; RV64-VLEN256EXACT: # %bb.0: # %entry51; RV64-VLEN256EXACT-NEXT: li a0, 452; RV64-VLEN256EXACT-NEXT: ret53entry:54 %0 = call i64 @llvm.vscale.i64()55 %1 = mul i64 %0, 156 ret i64 %157}58 59define i64 @vscale_uimmpow2xlen() nounwind {60; RV64-LABEL: vscale_uimmpow2xlen:61; RV64: # %bb.0: # %entry62; RV64-NEXT: csrr a0, vlenb63; RV64-NEXT: slli a0, a0, 364; RV64-NEXT: ret65;66; RV32-LABEL: vscale_uimmpow2xlen:67; RV32: # %bb.0: # %entry68; RV32-NEXT: csrr a0, vlenb69; RV32-NEXT: slli a0, a0, 370; RV32-NEXT: li a1, 071; RV32-NEXT: ret72;73; RV64-VLEN256EXACT-LABEL: vscale_uimmpow2xlen:74; RV64-VLEN256EXACT: # %bb.0: # %entry75; RV64-VLEN256EXACT-NEXT: li a0, 25676; RV64-VLEN256EXACT-NEXT: ret77entry:78 %0 = call i64 @llvm.vscale.i64()79 %1 = mul i64 %0, 6480 ret i64 %181}82 83define i64 @vscale_non_pow2() nounwind {84; RV64-LABEL: vscale_non_pow2:85; RV64: # %bb.0: # %entry86; RV64-NEXT: csrr a0, vlenb87; RV64-NEXT: slli a1, a0, 188; RV64-NEXT: add a0, a1, a089; RV64-NEXT: ret90;91; RV32-LABEL: vscale_non_pow2:92; RV32: # %bb.0: # %entry93; RV32-NEXT: csrr a0, vlenb94; RV32-NEXT: slli a1, a0, 195; RV32-NEXT: add a0, a1, a096; RV32-NEXT: li a1, 097; RV32-NEXT: ret98;99; RV64-VLEN256EXACT-LABEL: vscale_non_pow2:100; RV64-VLEN256EXACT: # %bb.0: # %entry101; RV64-VLEN256EXACT-NEXT: li a0, 96102; RV64-VLEN256EXACT-NEXT: ret103entry:104 %0 = call i64 @llvm.vscale.i64()105 %1 = mul i64 %0, 24106 ret i64 %1107}108 109; vscale will always be a positive number, but we don't know that until after op110; legalization. The and will be considered a NOP and replaced with its input,111; but not until after the select becomes RISCVISD::SELECT_CC. Make sure we112; simplify this and don't leave behind any code for calculating the select113; condition.114define i64 @vscale_select(i32 %x, i32 %y) {115; RV64-LABEL: vscale_select:116; RV64: # %bb.0:117; RV64-NEXT: csrr a0, vlenb118; RV64-NEXT: srli a0, a0, 3119; RV64-NEXT: ret120;121; RV32-LABEL: vscale_select:122; RV32: # %bb.0:123; RV32-NEXT: csrr a0, vlenb124; RV32-NEXT: srli a0, a0, 3125; RV32-NEXT: li a1, 0126; RV32-NEXT: ret127;128; RV64-VLEN256EXACT-LABEL: vscale_select:129; RV64-VLEN256EXACT: # %bb.0:130; RV64-VLEN256EXACT-NEXT: li a0, 4131; RV64-VLEN256EXACT-NEXT: ret132 %a = call i64 @llvm.vscale.i64()133 %b = and i64 %a, 4294967295134 %c = icmp eq i32 %x, %y135 %d = select i1 %c, i64 %a, i64 %b136 ret i64 %d137}138 139define i64 @vscale_high_bits_zero() nounwind {140; RV64-LABEL: vscale_high_bits_zero:141; RV64: # %bb.0: # %entry142; RV64-NEXT: csrr a0, vlenb143; RV64-NEXT: srli a0, a0, 3144; RV64-NEXT: ret145;146; RV32-LABEL: vscale_high_bits_zero:147; RV32: # %bb.0: # %entry148; RV32-NEXT: csrr a0, vlenb149; RV32-NEXT: srli a0, a0, 3150; RV32-NEXT: li a1, 0151; RV32-NEXT: ret152;153; RV64-VLEN256EXACT-LABEL: vscale_high_bits_zero:154; RV64-VLEN256EXACT: # %bb.0: # %entry155; RV64-VLEN256EXACT-NEXT: li a0, 4156; RV64-VLEN256EXACT-NEXT: ret157entry:158 %0 = call i64 @llvm.vscale.i64()159 %1 = and i64 %0, 2047160 ret i64 %1161}162 163define i64 @vscale_masked() nounwind {164; RV64-VLENUNK-LABEL: vscale_masked:165; RV64-VLENUNK: # %bb.0: # %entry166; RV64-VLENUNK-NEXT: csrr a0, vlenb167; RV64-VLENUNK-NEXT: srli a0, a0, 3168; RV64-VLENUNK-NEXT: andi a0, a0, 510169; RV64-VLENUNK-NEXT: ret170;171; RV32-LABEL: vscale_masked:172; RV32: # %bb.0: # %entry173; RV32-NEXT: csrr a0, vlenb174; RV32-NEXT: srli a0, a0, 3175; RV32-NEXT: andi a0, a0, 510176; RV32-NEXT: li a1, 0177; RV32-NEXT: ret178;179; RV64-VLEN256MIN-LABEL: vscale_masked:180; RV64-VLEN256MIN: # %bb.0: # %entry181; RV64-VLEN256MIN-NEXT: csrr a0, vlenb182; RV64-VLEN256MIN-NEXT: srli a0, a0, 3183; RV64-VLEN256MIN-NEXT: andi a0, a0, 508184; RV64-VLEN256MIN-NEXT: ret185;186; RV64-VLEN256MAX-LABEL: vscale_masked:187; RV64-VLEN256MAX: # %bb.0: # %entry188; RV64-VLEN256MAX-NEXT: csrr a0, vlenb189; RV64-VLEN256MAX-NEXT: srli a0, a0, 3190; RV64-VLEN256MAX-NEXT: ret191;192; RV64-VLEN256EXACT-LABEL: vscale_masked:193; RV64-VLEN256EXACT: # %bb.0: # %entry194; RV64-VLEN256EXACT-NEXT: li a0, 4195; RV64-VLEN256EXACT-NEXT: ret196entry:197 %0 = call i64 @llvm.vscale.i64()198 %1 = and i64 %0, 511199 ret i64 %1200}201 202