186 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+zfbfmin,+zvfbfmin -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+zfbfmin,+zvfbfmin -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <vscale x 1 x bfloat> @select_nxv1bf16(i1 zeroext %c, <vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b) {8; CHECK-LABEL: select_nxv1bf16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma11; CHECK-NEXT: vmv.v.x v10, a012; CHECK-NEXT: vmsne.vi v0, v10, 013; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma14; CHECK-NEXT: vmerge.vvm v8, v9, v8, v015; CHECK-NEXT: ret16 %v = select i1 %c, <vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b17 ret <vscale x 1 x bfloat> %v18}19 20define <vscale x 1 x bfloat> @selectcc_nxv1bf16(bfloat %a, bfloat %b, <vscale x 1 x bfloat> %c, <vscale x 1 x bfloat> %d) {21; CHECK-LABEL: selectcc_nxv1bf16:22; CHECK: # %bb.0:23; CHECK-NEXT: fcvt.s.bf16 fa5, fa124; CHECK-NEXT: fcvt.s.bf16 fa4, fa025; CHECK-NEXT: feq.s a0, fa4, fa526; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma27; CHECK-NEXT: vmv.v.x v10, a028; CHECK-NEXT: vmsne.vi v0, v10, 029; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma30; CHECK-NEXT: vmerge.vvm v8, v9, v8, v031; CHECK-NEXT: ret32 %cmp = fcmp oeq bfloat %a, %b33 %v = select i1 %cmp, <vscale x 1 x bfloat> %c, <vscale x 1 x bfloat> %d34 ret <vscale x 1 x bfloat> %v35}36 37define <vscale x 2 x bfloat> @select_nxv2bf16(i1 zeroext %c, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {38; CHECK-LABEL: select_nxv2bf16:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma41; CHECK-NEXT: vmv.v.x v10, a042; CHECK-NEXT: vmsne.vi v0, v10, 043; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma44; CHECK-NEXT: vmerge.vvm v8, v9, v8, v045; CHECK-NEXT: ret46 %v = select i1 %c, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b47 ret <vscale x 2 x bfloat> %v48}49 50define <vscale x 2 x bfloat> @selectcc_nxv2bf16(bfloat %a, bfloat %b, <vscale x 2 x bfloat> %c, <vscale x 2 x bfloat> %d) {51; CHECK-LABEL: selectcc_nxv2bf16:52; CHECK: # %bb.0:53; CHECK-NEXT: fcvt.s.bf16 fa5, fa154; CHECK-NEXT: fcvt.s.bf16 fa4, fa055; CHECK-NEXT: feq.s a0, fa4, fa556; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma57; CHECK-NEXT: vmv.v.x v10, a058; CHECK-NEXT: vmsne.vi v0, v10, 059; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma60; CHECK-NEXT: vmerge.vvm v8, v9, v8, v061; CHECK-NEXT: ret62 %cmp = fcmp oeq bfloat %a, %b63 %v = select i1 %cmp, <vscale x 2 x bfloat> %c, <vscale x 2 x bfloat> %d64 ret <vscale x 2 x bfloat> %v65}66 67define <vscale x 4 x bfloat> @select_nxv4bf16(i1 zeroext %c, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {68; CHECK-LABEL: select_nxv4bf16:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma71; CHECK-NEXT: vmv.v.x v10, a072; CHECK-NEXT: vmsne.vi v0, v10, 073; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma74; CHECK-NEXT: vmerge.vvm v8, v9, v8, v075; CHECK-NEXT: ret76 %v = select i1 %c, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b77 ret <vscale x 4 x bfloat> %v78}79 80define <vscale x 4 x bfloat> @selectcc_nxv4bf16(bfloat %a, bfloat %b, <vscale x 4 x bfloat> %c, <vscale x 4 x bfloat> %d) {81; CHECK-LABEL: selectcc_nxv4bf16:82; CHECK: # %bb.0:83; CHECK-NEXT: fcvt.s.bf16 fa5, fa184; CHECK-NEXT: fcvt.s.bf16 fa4, fa085; CHECK-NEXT: feq.s a0, fa4, fa586; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma87; CHECK-NEXT: vmv.v.x v10, a088; CHECK-NEXT: vmsne.vi v0, v10, 089; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma90; CHECK-NEXT: vmerge.vvm v8, v9, v8, v091; CHECK-NEXT: ret92 %cmp = fcmp oeq bfloat %a, %b93 %v = select i1 %cmp, <vscale x 4 x bfloat> %c, <vscale x 4 x bfloat> %d94 ret <vscale x 4 x bfloat> %v95}96 97define <vscale x 8 x bfloat> @select_nxv8bf16(i1 zeroext %c, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {98; CHECK-LABEL: select_nxv8bf16:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma101; CHECK-NEXT: vmv.v.x v12, a0102; CHECK-NEXT: vmsne.vi v0, v12, 0103; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma104; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0105; CHECK-NEXT: ret106 %v = select i1 %c, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b107 ret <vscale x 8 x bfloat> %v108}109 110define <vscale x 8 x bfloat> @selectcc_nxv8bf16(bfloat %a, bfloat %b, <vscale x 8 x bfloat> %c, <vscale x 8 x bfloat> %d) {111; CHECK-LABEL: selectcc_nxv8bf16:112; CHECK: # %bb.0:113; CHECK-NEXT: fcvt.s.bf16 fa5, fa1114; CHECK-NEXT: fcvt.s.bf16 fa4, fa0115; CHECK-NEXT: feq.s a0, fa4, fa5116; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma117; CHECK-NEXT: vmv.v.x v12, a0118; CHECK-NEXT: vmsne.vi v0, v12, 0119; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma120; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0121; CHECK-NEXT: ret122 %cmp = fcmp oeq bfloat %a, %b123 %v = select i1 %cmp, <vscale x 8 x bfloat> %c, <vscale x 8 x bfloat> %d124 ret <vscale x 8 x bfloat> %v125}126 127define <vscale x 16 x bfloat> @select_nxv16bf16(i1 zeroext %c, <vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b) {128; CHECK-LABEL: select_nxv16bf16:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma131; CHECK-NEXT: vmv.v.x v16, a0132; CHECK-NEXT: vmsne.vi v0, v16, 0133; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma134; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0135; CHECK-NEXT: ret136 %v = select i1 %c, <vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b137 ret <vscale x 16 x bfloat> %v138}139 140define <vscale x 16 x bfloat> @selectcc_nxv16bf16(bfloat %a, bfloat %b, <vscale x 16 x bfloat> %c, <vscale x 16 x bfloat> %d) {141; CHECK-LABEL: selectcc_nxv16bf16:142; CHECK: # %bb.0:143; CHECK-NEXT: fcvt.s.bf16 fa5, fa1144; CHECK-NEXT: fcvt.s.bf16 fa4, fa0145; CHECK-NEXT: feq.s a0, fa4, fa5146; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma147; CHECK-NEXT: vmv.v.x v16, a0148; CHECK-NEXT: vmsne.vi v0, v16, 0149; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma150; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0151; CHECK-NEXT: ret152 %cmp = fcmp oeq bfloat %a, %b153 %v = select i1 %cmp, <vscale x 16 x bfloat> %c, <vscale x 16 x bfloat> %d154 ret <vscale x 16 x bfloat> %v155}156 157define <vscale x 32 x bfloat> @select_nxv32bf16(i1 zeroext %c, <vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) {158; CHECK-LABEL: select_nxv32bf16:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma161; CHECK-NEXT: vmv.v.x v24, a0162; CHECK-NEXT: vmsne.vi v0, v24, 0163; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma164; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0165; CHECK-NEXT: ret166 %v = select i1 %c, <vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b167 ret <vscale x 32 x bfloat> %v168}169 170define <vscale x 32 x bfloat> @selectcc_nxv32bf16(bfloat %a, bfloat %b, <vscale x 32 x bfloat> %c, <vscale x 32 x bfloat> %d) {171; CHECK-LABEL: selectcc_nxv32bf16:172; CHECK: # %bb.0:173; CHECK-NEXT: fcvt.s.bf16 fa5, fa1174; CHECK-NEXT: fcvt.s.bf16 fa4, fa0175; CHECK-NEXT: feq.s a0, fa4, fa5176; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma177; CHECK-NEXT: vmv.v.x v24, a0178; CHECK-NEXT: vmsne.vi v0, v24, 0179; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma180; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0181; CHECK-NEXT: ret182 %cmp = fcmp oeq bfloat %a, %b183 %v = select i1 %cmp, <vscale x 32 x bfloat> %c, <vscale x 32 x bfloat> %d184 ret <vscale x 32 x bfloat> %v185}186