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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s8; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s10 11define <vscale x 1 x half> @select_nxv1f16(i1 zeroext %c, <vscale x 1 x half> %a, <vscale x 1 x half> %b) {12; CHECK-LABEL: select_nxv1f16:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma15; CHECK-NEXT: vmv.v.x v10, a016; CHECK-NEXT: vmsne.vi v0, v10, 017; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma18; CHECK-NEXT: vmerge.vvm v8, v9, v8, v019; CHECK-NEXT: ret20 %v = select i1 %c, <vscale x 1 x half> %a, <vscale x 1 x half> %b21 ret <vscale x 1 x half> %v22}23 24define <vscale x 1 x half> @selectcc_nxv1f16(half %a, half %b, <vscale x 1 x half> %c, <vscale x 1 x half> %d) {25; CHECK-LABEL: selectcc_nxv1f16:26; CHECK: # %bb.0:27; CHECK-NEXT: feq.h a0, fa0, fa128; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma29; CHECK-NEXT: vmv.v.x v10, a030; CHECK-NEXT: vmsne.vi v0, v10, 031; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma32; CHECK-NEXT: vmerge.vvm v8, v9, v8, v033; CHECK-NEXT: ret34 %cmp = fcmp oeq half %a, %b35 %v = select i1 %cmp, <vscale x 1 x half> %c, <vscale x 1 x half> %d36 ret <vscale x 1 x half> %v37}38 39define <vscale x 2 x half> @select_nxv2f16(i1 zeroext %c, <vscale x 2 x half> %a, <vscale x 2 x half> %b) {40; CHECK-LABEL: select_nxv2f16:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma43; CHECK-NEXT: vmv.v.x v10, a044; CHECK-NEXT: vmsne.vi v0, v10, 045; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma46; CHECK-NEXT: vmerge.vvm v8, v9, v8, v047; CHECK-NEXT: ret48 %v = select i1 %c, <vscale x 2 x half> %a, <vscale x 2 x half> %b49 ret <vscale x 2 x half> %v50}51 52define <vscale x 2 x half> @selectcc_nxv2f16(half %a, half %b, <vscale x 2 x half> %c, <vscale x 2 x half> %d) {53; CHECK-LABEL: selectcc_nxv2f16:54; CHECK: # %bb.0:55; CHECK-NEXT: feq.h a0, fa0, fa156; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma57; CHECK-NEXT: vmv.v.x v10, a058; CHECK-NEXT: vmsne.vi v0, v10, 059; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma60; CHECK-NEXT: vmerge.vvm v8, v9, v8, v061; CHECK-NEXT: ret62 %cmp = fcmp oeq half %a, %b63 %v = select i1 %cmp, <vscale x 2 x half> %c, <vscale x 2 x half> %d64 ret <vscale x 2 x half> %v65}66 67define <vscale x 4 x half> @select_nxv4f16(i1 zeroext %c, <vscale x 4 x half> %a, <vscale x 4 x half> %b) {68; CHECK-LABEL: select_nxv4f16:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma71; CHECK-NEXT: vmv.v.x v10, a072; CHECK-NEXT: vmsne.vi v0, v10, 073; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma74; CHECK-NEXT: vmerge.vvm v8, v9, v8, v075; CHECK-NEXT: ret76 %v = select i1 %c, <vscale x 4 x half> %a, <vscale x 4 x half> %b77 ret <vscale x 4 x half> %v78}79 80define <vscale x 4 x half> @selectcc_nxv4f16(half %a, half %b, <vscale x 4 x half> %c, <vscale x 4 x half> %d) {81; CHECK-LABEL: selectcc_nxv4f16:82; CHECK: # %bb.0:83; CHECK-NEXT: feq.h a0, fa0, fa184; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma85; CHECK-NEXT: vmv.v.x v10, a086; CHECK-NEXT: vmsne.vi v0, v10, 087; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma88; CHECK-NEXT: vmerge.vvm v8, v9, v8, v089; CHECK-NEXT: ret90 %cmp = fcmp oeq half %a, %b91 %v = select i1 %cmp, <vscale x 4 x half> %c, <vscale x 4 x half> %d92 ret <vscale x 4 x half> %v93}94 95define <vscale x 8 x half> @select_nxv8f16(i1 zeroext %c, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {96; CHECK-LABEL: select_nxv8f16:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma99; CHECK-NEXT: vmv.v.x v12, a0100; CHECK-NEXT: vmsne.vi v0, v12, 0101; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma102; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0103; CHECK-NEXT: ret104 %v = select i1 %c, <vscale x 8 x half> %a, <vscale x 8 x half> %b105 ret <vscale x 8 x half> %v106}107 108define <vscale x 8 x half> @selectcc_nxv8f16(half %a, half %b, <vscale x 8 x half> %c, <vscale x 8 x half> %d) {109; CHECK-LABEL: selectcc_nxv8f16:110; CHECK: # %bb.0:111; CHECK-NEXT: feq.h a0, fa0, fa1112; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma113; CHECK-NEXT: vmv.v.x v12, a0114; CHECK-NEXT: vmsne.vi v0, v12, 0115; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma116; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0117; CHECK-NEXT: ret118 %cmp = fcmp oeq half %a, %b119 %v = select i1 %cmp, <vscale x 8 x half> %c, <vscale x 8 x half> %d120 ret <vscale x 8 x half> %v121}122 123define <vscale x 16 x half> @select_nxv16f16(i1 zeroext %c, <vscale x 16 x half> %a, <vscale x 16 x half> %b) {124; CHECK-LABEL: select_nxv16f16:125; CHECK: # %bb.0:126; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma127; CHECK-NEXT: vmv.v.x v16, a0128; CHECK-NEXT: vmsne.vi v0, v16, 0129; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma130; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0131; CHECK-NEXT: ret132 %v = select i1 %c, <vscale x 16 x half> %a, <vscale x 16 x half> %b133 ret <vscale x 16 x half> %v134}135 136define <vscale x 16 x half> @selectcc_nxv16f16(half %a, half %b, <vscale x 16 x half> %c, <vscale x 16 x half> %d) {137; CHECK-LABEL: selectcc_nxv16f16:138; CHECK: # %bb.0:139; CHECK-NEXT: feq.h a0, fa0, fa1140; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma141; CHECK-NEXT: vmv.v.x v16, a0142; CHECK-NEXT: vmsne.vi v0, v16, 0143; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma144; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0145; CHECK-NEXT: ret146 %cmp = fcmp oeq half %a, %b147 %v = select i1 %cmp, <vscale x 16 x half> %c, <vscale x 16 x half> %d148 ret <vscale x 16 x half> %v149}150 151define <vscale x 32 x half> @select_nxv32f16(i1 zeroext %c, <vscale x 32 x half> %a, <vscale x 32 x half> %b) {152; CHECK-LABEL: select_nxv32f16:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma155; CHECK-NEXT: vmv.v.x v24, a0156; CHECK-NEXT: vmsne.vi v0, v24, 0157; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma158; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0159; CHECK-NEXT: ret160 %v = select i1 %c, <vscale x 32 x half> %a, <vscale x 32 x half> %b161 ret <vscale x 32 x half> %v162}163 164define <vscale x 32 x half> @selectcc_nxv32f16(half %a, half %b, <vscale x 32 x half> %c, <vscale x 32 x half> %d) {165; CHECK-LABEL: selectcc_nxv32f16:166; CHECK: # %bb.0:167; CHECK-NEXT: feq.h a0, fa0, fa1168; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma169; CHECK-NEXT: vmv.v.x v24, a0170; CHECK-NEXT: vmsne.vi v0, v24, 0171; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma172; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0173; CHECK-NEXT: ret174 %cmp = fcmp oeq half %a, %b175 %v = select i1 %cmp, <vscale x 32 x half> %c, <vscale x 32 x half> %d176 ret <vscale x 32 x half> %v177}178 179define <vscale x 1 x float> @select_nxv1f32(i1 zeroext %c, <vscale x 1 x float> %a, <vscale x 1 x float> %b) {180; CHECK-LABEL: select_nxv1f32:181; CHECK: # %bb.0:182; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma183; CHECK-NEXT: vmv.v.x v10, a0184; CHECK-NEXT: vmsne.vi v0, v10, 0185; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma186; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0187; CHECK-NEXT: ret188 %v = select i1 %c, <vscale x 1 x float> %a, <vscale x 1 x float> %b189 ret <vscale x 1 x float> %v190}191 192define <vscale x 1 x float> @selectcc_nxv1f32(float %a, float %b, <vscale x 1 x float> %c, <vscale x 1 x float> %d) {193; CHECK-LABEL: selectcc_nxv1f32:194; CHECK: # %bb.0:195; CHECK-NEXT: feq.s a0, fa0, fa1196; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma197; CHECK-NEXT: vmv.v.x v10, a0198; CHECK-NEXT: vmsne.vi v0, v10, 0199; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma200; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0201; CHECK-NEXT: ret202 %cmp = fcmp oeq float %a, %b203 %v = select i1 %cmp, <vscale x 1 x float> %c, <vscale x 1 x float> %d204 ret <vscale x 1 x float> %v205}206 207define <vscale x 2 x float> @select_nxv2f32(i1 zeroext %c, <vscale x 2 x float> %a, <vscale x 2 x float> %b) {208; CHECK-LABEL: select_nxv2f32:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma211; CHECK-NEXT: vmv.v.x v10, a0212; CHECK-NEXT: vmsne.vi v0, v10, 0213; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma214; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0215; CHECK-NEXT: ret216 %v = select i1 %c, <vscale x 2 x float> %a, <vscale x 2 x float> %b217 ret <vscale x 2 x float> %v218}219 220define <vscale x 2 x float> @selectcc_nxv2f32(float %a, float %b, <vscale x 2 x float> %c, <vscale x 2 x float> %d) {221; CHECK-LABEL: selectcc_nxv2f32:222; CHECK: # %bb.0:223; CHECK-NEXT: feq.s a0, fa0, fa1224; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma225; CHECK-NEXT: vmv.v.x v10, a0226; CHECK-NEXT: vmsne.vi v0, v10, 0227; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma228; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0229; CHECK-NEXT: ret230 %cmp = fcmp oeq float %a, %b231 %v = select i1 %cmp, <vscale x 2 x float> %c, <vscale x 2 x float> %d232 ret <vscale x 2 x float> %v233}234 235define <vscale x 4 x float> @select_nxv4f32(i1 zeroext %c, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {236; CHECK-LABEL: select_nxv4f32:237; CHECK: # %bb.0:238; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma239; CHECK-NEXT: vmv.v.x v12, a0240; CHECK-NEXT: vmsne.vi v0, v12, 0241; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma242; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0243; CHECK-NEXT: ret244 %v = select i1 %c, <vscale x 4 x float> %a, <vscale x 4 x float> %b245 ret <vscale x 4 x float> %v246}247 248define <vscale x 4 x float> @selectcc_nxv4f32(float %a, float %b, <vscale x 4 x float> %c, <vscale x 4 x float> %d) {249; CHECK-LABEL: selectcc_nxv4f32:250; CHECK: # %bb.0:251; CHECK-NEXT: feq.s a0, fa0, fa1252; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma253; CHECK-NEXT: vmv.v.x v12, a0254; CHECK-NEXT: vmsne.vi v0, v12, 0255; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma256; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0257; CHECK-NEXT: ret258 %cmp = fcmp oeq float %a, %b259 %v = select i1 %cmp, <vscale x 4 x float> %c, <vscale x 4 x float> %d260 ret <vscale x 4 x float> %v261}262 263define <vscale x 8 x float> @select_nxv8f32(i1 zeroext %c, <vscale x 8 x float> %a, <vscale x 8 x float> %b) {264; CHECK-LABEL: select_nxv8f32:265; CHECK: # %bb.0:266; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma267; CHECK-NEXT: vmv.v.x v16, a0268; CHECK-NEXT: vmsne.vi v0, v16, 0269; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma270; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0271; CHECK-NEXT: ret272 %v = select i1 %c, <vscale x 8 x float> %a, <vscale x 8 x float> %b273 ret <vscale x 8 x float> %v274}275 276define <vscale x 8 x float> @selectcc_nxv8f32(float %a, float %b, <vscale x 8 x float> %c, <vscale x 8 x float> %d) {277; CHECK-LABEL: selectcc_nxv8f32:278; CHECK: # %bb.0:279; CHECK-NEXT: feq.s a0, fa0, fa1280; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma281; CHECK-NEXT: vmv.v.x v16, a0282; CHECK-NEXT: vmsne.vi v0, v16, 0283; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma284; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0285; CHECK-NEXT: ret286 %cmp = fcmp oeq float %a, %b287 %v = select i1 %cmp, <vscale x 8 x float> %c, <vscale x 8 x float> %d288 ret <vscale x 8 x float> %v289}290 291define <vscale x 16 x float> @select_nxv16f32(i1 zeroext %c, <vscale x 16 x float> %a, <vscale x 16 x float> %b) {292; CHECK-LABEL: select_nxv16f32:293; CHECK: # %bb.0:294; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma295; CHECK-NEXT: vmv.v.x v24, a0296; CHECK-NEXT: vmsne.vi v0, v24, 0297; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma298; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0299; CHECK-NEXT: ret300 %v = select i1 %c, <vscale x 16 x float> %a, <vscale x 16 x float> %b301 ret <vscale x 16 x float> %v302}303 304define <vscale x 16 x float> @selectcc_nxv16f32(float %a, float %b, <vscale x 16 x float> %c, <vscale x 16 x float> %d) {305; CHECK-LABEL: selectcc_nxv16f32:306; CHECK: # %bb.0:307; CHECK-NEXT: feq.s a0, fa0, fa1308; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma309; CHECK-NEXT: vmv.v.x v24, a0310; CHECK-NEXT: vmsne.vi v0, v24, 0311; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma312; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0313; CHECK-NEXT: ret314 %cmp = fcmp oeq float %a, %b315 %v = select i1 %cmp, <vscale x 16 x float> %c, <vscale x 16 x float> %d316 ret <vscale x 16 x float> %v317}318 319define <vscale x 1 x double> @select_nxv1f64(i1 zeroext %c, <vscale x 1 x double> %a, <vscale x 1 x double> %b) {320; CHECK-LABEL: select_nxv1f64:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma323; CHECK-NEXT: vmv.v.x v10, a0324; CHECK-NEXT: vmsne.vi v0, v10, 0325; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma326; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0327; CHECK-NEXT: ret328 %v = select i1 %c, <vscale x 1 x double> %a, <vscale x 1 x double> %b329 ret <vscale x 1 x double> %v330}331 332define <vscale x 1 x double> @selectcc_nxv1f64(double %a, double %b, <vscale x 1 x double> %c, <vscale x 1 x double> %d) {333; CHECK-LABEL: selectcc_nxv1f64:334; CHECK: # %bb.0:335; CHECK-NEXT: feq.d a0, fa0, fa1336; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma337; CHECK-NEXT: vmv.v.x v10, a0338; CHECK-NEXT: vmsne.vi v0, v10, 0339; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma340; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0341; CHECK-NEXT: ret342 %cmp = fcmp oeq double %a, %b343 %v = select i1 %cmp, <vscale x 1 x double> %c, <vscale x 1 x double> %d344 ret <vscale x 1 x double> %v345}346 347define <vscale x 2 x double> @select_nxv2f64(i1 zeroext %c, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {348; CHECK-LABEL: select_nxv2f64:349; CHECK: # %bb.0:350; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma351; CHECK-NEXT: vmv.v.x v12, a0352; CHECK-NEXT: vmsne.vi v0, v12, 0353; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma354; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0355; CHECK-NEXT: ret356 %v = select i1 %c, <vscale x 2 x double> %a, <vscale x 2 x double> %b357 ret <vscale x 2 x double> %v358}359 360define <vscale x 2 x double> @selectcc_nxv2f64(double %a, double %b, <vscale x 2 x double> %c, <vscale x 2 x double> %d) {361; CHECK-LABEL: selectcc_nxv2f64:362; CHECK: # %bb.0:363; CHECK-NEXT: feq.d a0, fa0, fa1364; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma365; CHECK-NEXT: vmv.v.x v12, a0366; CHECK-NEXT: vmsne.vi v0, v12, 0367; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma368; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0369; CHECK-NEXT: ret370 %cmp = fcmp oeq double %a, %b371 %v = select i1 %cmp, <vscale x 2 x double> %c, <vscale x 2 x double> %d372 ret <vscale x 2 x double> %v373}374 375define <vscale x 4 x double> @select_nxv4f64(i1 zeroext %c, <vscale x 4 x double> %a, <vscale x 4 x double> %b) {376; CHECK-LABEL: select_nxv4f64:377; CHECK: # %bb.0:378; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma379; CHECK-NEXT: vmv.v.x v16, a0380; CHECK-NEXT: vmsne.vi v0, v16, 0381; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma382; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0383; CHECK-NEXT: ret384 %v = select i1 %c, <vscale x 4 x double> %a, <vscale x 4 x double> %b385 ret <vscale x 4 x double> %v386}387 388define <vscale x 4 x double> @selectcc_nxv4f64(double %a, double %b, <vscale x 4 x double> %c, <vscale x 4 x double> %d) {389; CHECK-LABEL: selectcc_nxv4f64:390; CHECK: # %bb.0:391; CHECK-NEXT: feq.d a0, fa0, fa1392; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma393; CHECK-NEXT: vmv.v.x v16, a0394; CHECK-NEXT: vmsne.vi v0, v16, 0395; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma396; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0397; CHECK-NEXT: ret398 %cmp = fcmp oeq double %a, %b399 %v = select i1 %cmp, <vscale x 4 x double> %c, <vscale x 4 x double> %d400 ret <vscale x 4 x double> %v401}402 403define <vscale x 8 x double> @select_nxv8f64(i1 zeroext %c, <vscale x 8 x double> %a, <vscale x 8 x double> %b) {404; CHECK-LABEL: select_nxv8f64:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma407; CHECK-NEXT: vmv.v.x v24, a0408; CHECK-NEXT: vmsne.vi v0, v24, 0409; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma410; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0411; CHECK-NEXT: ret412 %v = select i1 %c, <vscale x 8 x double> %a, <vscale x 8 x double> %b413 ret <vscale x 8 x double> %v414}415 416define <vscale x 8 x double> @selectcc_nxv8f64(double %a, double %b, <vscale x 8 x double> %c, <vscale x 8 x double> %d) {417; CHECK-LABEL: selectcc_nxv8f64:418; CHECK: # %bb.0:419; CHECK-NEXT: feq.d a0, fa0, fa1420; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma421; CHECK-NEXT: vmv.v.x v24, a0422; CHECK-NEXT: vmsne.vi v0, v24, 0423; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma424; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0425; CHECK-NEXT: ret426 %cmp = fcmp oeq double %a, %b427 %v = select i1 %cmp, <vscale x 8 x double> %c, <vscale x 8 x double> %d428 ret <vscale x 8 x double> %v429}430