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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i1> @select_nxv1i1(i1 zeroext %c, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {8; CHECK-LABEL: select_nxv1i1:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma11; CHECK-NEXT: vmv.v.x v9, a012; CHECK-NEXT: vmsne.vi v9, v9, 013; CHECK-NEXT: vmandn.mm v8, v8, v914; CHECK-NEXT: vmand.mm v9, v0, v915; CHECK-NEXT: vmor.mm v0, v9, v816; CHECK-NEXT: ret17 %v = select i1 %c, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b18 ret <vscale x 1 x i1> %v19}20 21define <vscale x 1 x i1> @selectcc_nxv1i1(i1 signext %a, i1 signext %b, <vscale x 1 x i1> %c, <vscale x 1 x i1> %d) {22; CHECK-LABEL: selectcc_nxv1i1:23; CHECK: # %bb.0:24; CHECK-NEXT: xor a0, a0, a125; CHECK-NEXT: andi a0, a0, 126; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma27; CHECK-NEXT: vmv.v.x v9, a028; CHECK-NEXT: vmsne.vi v9, v9, 029; CHECK-NEXT: vmandn.mm v8, v8, v930; CHECK-NEXT: vmand.mm v9, v0, v931; CHECK-NEXT: vmor.mm v0, v9, v832; CHECK-NEXT: ret33 %cmp = icmp ne i1 %a, %b34 %v = select i1 %cmp, <vscale x 1 x i1> %c, <vscale x 1 x i1> %d35 ret <vscale x 1 x i1> %v36}37 38define <vscale x 2 x i1> @select_nxv2i1(i1 zeroext %c, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {39; CHECK-LABEL: select_nxv2i1:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma42; CHECK-NEXT: vmv.v.x v9, a043; CHECK-NEXT: vmsne.vi v9, v9, 044; CHECK-NEXT: vmandn.mm v8, v8, v945; CHECK-NEXT: vmand.mm v9, v0, v946; CHECK-NEXT: vmor.mm v0, v9, v847; CHECK-NEXT: ret48 %v = select i1 %c, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b49 ret <vscale x 2 x i1> %v50}51 52define <vscale x 2 x i1> @selectcc_nxv2i1(i1 signext %a, i1 signext %b, <vscale x 2 x i1> %c, <vscale x 2 x i1> %d) {53; CHECK-LABEL: selectcc_nxv2i1:54; CHECK: # %bb.0:55; CHECK-NEXT: xor a0, a0, a156; CHECK-NEXT: andi a0, a0, 157; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma58; CHECK-NEXT: vmv.v.x v9, a059; CHECK-NEXT: vmsne.vi v9, v9, 060; CHECK-NEXT: vmandn.mm v8, v8, v961; CHECK-NEXT: vmand.mm v9, v0, v962; CHECK-NEXT: vmor.mm v0, v9, v863; CHECK-NEXT: ret64 %cmp = icmp ne i1 %a, %b65 %v = select i1 %cmp, <vscale x 2 x i1> %c, <vscale x 2 x i1> %d66 ret <vscale x 2 x i1> %v67}68 69define <vscale x 4 x i1> @select_nxv4i1(i1 zeroext %c, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {70; CHECK-LABEL: select_nxv4i1:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma73; CHECK-NEXT: vmv.v.x v9, a074; CHECK-NEXT: vmsne.vi v9, v9, 075; CHECK-NEXT: vmandn.mm v8, v8, v976; CHECK-NEXT: vmand.mm v9, v0, v977; CHECK-NEXT: vmor.mm v0, v9, v878; CHECK-NEXT: ret79 %v = select i1 %c, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b80 ret <vscale x 4 x i1> %v81}82 83define <vscale x 4 x i1> @selectcc_nxv4i1(i1 signext %a, i1 signext %b, <vscale x 4 x i1> %c, <vscale x 4 x i1> %d) {84; CHECK-LABEL: selectcc_nxv4i1:85; CHECK: # %bb.0:86; CHECK-NEXT: xor a0, a0, a187; CHECK-NEXT: andi a0, a0, 188; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma89; CHECK-NEXT: vmv.v.x v9, a090; CHECK-NEXT: vmsne.vi v9, v9, 091; CHECK-NEXT: vmandn.mm v8, v8, v992; CHECK-NEXT: vmand.mm v9, v0, v993; CHECK-NEXT: vmor.mm v0, v9, v894; CHECK-NEXT: ret95 %cmp = icmp ne i1 %a, %b96 %v = select i1 %cmp, <vscale x 4 x i1> %c, <vscale x 4 x i1> %d97 ret <vscale x 4 x i1> %v98}99 100define <vscale x 8 x i1> @select_nxv8i1(i1 zeroext %c, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {101; CHECK-LABEL: select_nxv8i1:102; CHECK: # %bb.0:103; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma104; CHECK-NEXT: vmv.v.x v9, a0105; CHECK-NEXT: vmsne.vi v9, v9, 0106; CHECK-NEXT: vmandn.mm v8, v8, v9107; CHECK-NEXT: vmand.mm v9, v0, v9108; CHECK-NEXT: vmor.mm v0, v9, v8109; CHECK-NEXT: ret110 %v = select i1 %c, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b111 ret <vscale x 8 x i1> %v112}113 114define <vscale x 8 x i1> @selectcc_nxv8i1(i1 signext %a, i1 signext %b, <vscale x 8 x i1> %c, <vscale x 8 x i1> %d) {115; CHECK-LABEL: selectcc_nxv8i1:116; CHECK: # %bb.0:117; CHECK-NEXT: xor a0, a0, a1118; CHECK-NEXT: andi a0, a0, 1119; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma120; CHECK-NEXT: vmv.v.x v9, a0121; CHECK-NEXT: vmsne.vi v9, v9, 0122; CHECK-NEXT: vmandn.mm v8, v8, v9123; CHECK-NEXT: vmand.mm v9, v0, v9124; CHECK-NEXT: vmor.mm v0, v9, v8125; CHECK-NEXT: ret126 %cmp = icmp ne i1 %a, %b127 %v = select i1 %cmp, <vscale x 8 x i1> %c, <vscale x 8 x i1> %d128 ret <vscale x 8 x i1> %v129}130 131define <vscale x 16 x i1> @select_nxv16i1(i1 zeroext %c, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {132; CHECK-LABEL: select_nxv16i1:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma135; CHECK-NEXT: vmv.v.x v10, a0136; CHECK-NEXT: vmsne.vi v9, v10, 0137; CHECK-NEXT: vmandn.mm v8, v8, v9138; CHECK-NEXT: vmand.mm v9, v0, v9139; CHECK-NEXT: vmor.mm v0, v9, v8140; CHECK-NEXT: ret141 %v = select i1 %c, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b142 ret <vscale x 16 x i1> %v143}144 145define <vscale x 16 x i1> @selectcc_nxv16i1(i1 signext %a, i1 signext %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d) {146; CHECK-LABEL: selectcc_nxv16i1:147; CHECK: # %bb.0:148; CHECK-NEXT: xor a0, a0, a1149; CHECK-NEXT: andi a0, a0, 1150; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma151; CHECK-NEXT: vmv.v.x v10, a0152; CHECK-NEXT: vmsne.vi v9, v10, 0153; CHECK-NEXT: vmandn.mm v8, v8, v9154; CHECK-NEXT: vmand.mm v9, v0, v9155; CHECK-NEXT: vmor.mm v0, v9, v8156; CHECK-NEXT: ret157 %cmp = icmp ne i1 %a, %b158 %v = select i1 %cmp, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d159 ret <vscale x 16 x i1> %v160}161 162define <vscale x 32 x i1> @select_nxv32i1(i1 zeroext %c, <vscale x 32 x i1> %a, <vscale x 32 x i1> %b) {163; CHECK-LABEL: select_nxv32i1:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma166; CHECK-NEXT: vmv.v.x v12, a0167; CHECK-NEXT: vmsne.vi v9, v12, 0168; CHECK-NEXT: vmandn.mm v8, v8, v9169; CHECK-NEXT: vmand.mm v9, v0, v9170; CHECK-NEXT: vmor.mm v0, v9, v8171; CHECK-NEXT: ret172 %v = select i1 %c, <vscale x 32 x i1> %a, <vscale x 32 x i1> %b173 ret <vscale x 32 x i1> %v174}175 176define <vscale x 32 x i1> @selectcc_nxv32i1(i1 signext %a, i1 signext %b, <vscale x 32 x i1> %c, <vscale x 32 x i1> %d) {177; CHECK-LABEL: selectcc_nxv32i1:178; CHECK: # %bb.0:179; CHECK-NEXT: xor a0, a0, a1180; CHECK-NEXT: andi a0, a0, 1181; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma182; CHECK-NEXT: vmv.v.x v12, a0183; CHECK-NEXT: vmsne.vi v9, v12, 0184; CHECK-NEXT: vmandn.mm v8, v8, v9185; CHECK-NEXT: vmand.mm v9, v0, v9186; CHECK-NEXT: vmor.mm v0, v9, v8187; CHECK-NEXT: ret188 %cmp = icmp ne i1 %a, %b189 %v = select i1 %cmp, <vscale x 32 x i1> %c, <vscale x 32 x i1> %d190 ret <vscale x 32 x i1> %v191}192 193define <vscale x 64 x i1> @select_nxv64i1(i1 zeroext %c, <vscale x 64 x i1> %a, <vscale x 64 x i1> %b) {194; CHECK-LABEL: select_nxv64i1:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma197; CHECK-NEXT: vmv.v.x v16, a0198; CHECK-NEXT: vmsne.vi v9, v16, 0199; CHECK-NEXT: vmandn.mm v8, v8, v9200; CHECK-NEXT: vmand.mm v9, v0, v9201; CHECK-NEXT: vmor.mm v0, v9, v8202; CHECK-NEXT: ret203 %v = select i1 %c, <vscale x 64 x i1> %a, <vscale x 64 x i1> %b204 ret <vscale x 64 x i1> %v205}206 207define <vscale x 64 x i1> @selectcc_nxv64i1(i1 signext %a, i1 signext %b, <vscale x 64 x i1> %c, <vscale x 64 x i1> %d) {208; CHECK-LABEL: selectcc_nxv64i1:209; CHECK: # %bb.0:210; CHECK-NEXT: xor a0, a0, a1211; CHECK-NEXT: andi a0, a0, 1212; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma213; CHECK-NEXT: vmv.v.x v16, a0214; CHECK-NEXT: vmsne.vi v9, v16, 0215; CHECK-NEXT: vmandn.mm v8, v8, v9216; CHECK-NEXT: vmand.mm v9, v0, v9217; CHECK-NEXT: vmor.mm v0, v9, v8218; CHECK-NEXT: ret219 %cmp = icmp ne i1 %a, %b220 %v = select i1 %cmp, <vscale x 64 x i1> %c, <vscale x 64 x i1> %d221 ret <vscale x 64 x i1> %v222}223 224define <vscale x 1 x i8> @select_nxv1i8(i1 zeroext %c, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {225; CHECK-LABEL: select_nxv1i8:226; CHECK: # %bb.0:227; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma228; CHECK-NEXT: vmv.v.x v10, a0229; CHECK-NEXT: vmsne.vi v0, v10, 0230; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0231; CHECK-NEXT: ret232 %v = select i1 %c, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b233 ret <vscale x 1 x i8> %v234}235 236define <vscale x 1 x i8> @selectcc_nxv1i8(i8 signext %a, i8 signext %b, <vscale x 1 x i8> %c, <vscale x 1 x i8> %d) {237; CHECK-LABEL: selectcc_nxv1i8:238; CHECK: # %bb.0:239; CHECK-NEXT: xor a0, a0, a1240; CHECK-NEXT: snez a0, a0241; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma242; CHECK-NEXT: vmv.v.x v10, a0243; CHECK-NEXT: vmsne.vi v0, v10, 0244; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0245; CHECK-NEXT: ret246 %cmp = icmp ne i8 %a, %b247 %v = select i1 %cmp, <vscale x 1 x i8> %c, <vscale x 1 x i8> %d248 ret <vscale x 1 x i8> %v249}250 251define <vscale x 2 x i8> @select_nxv2i8(i1 zeroext %c, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {252; CHECK-LABEL: select_nxv2i8:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma255; CHECK-NEXT: vmv.v.x v10, a0256; CHECK-NEXT: vmsne.vi v0, v10, 0257; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0258; CHECK-NEXT: ret259 %v = select i1 %c, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b260 ret <vscale x 2 x i8> %v261}262 263define <vscale x 2 x i8> @selectcc_nxv2i8(i8 signext %a, i8 signext %b, <vscale x 2 x i8> %c, <vscale x 2 x i8> %d) {264; CHECK-LABEL: selectcc_nxv2i8:265; CHECK: # %bb.0:266; CHECK-NEXT: xor a0, a0, a1267; CHECK-NEXT: snez a0, a0268; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma269; CHECK-NEXT: vmv.v.x v10, a0270; CHECK-NEXT: vmsne.vi v0, v10, 0271; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0272; CHECK-NEXT: ret273 %cmp = icmp ne i8 %a, %b274 %v = select i1 %cmp, <vscale x 2 x i8> %c, <vscale x 2 x i8> %d275 ret <vscale x 2 x i8> %v276}277 278define <vscale x 4 x i8> @select_nxv4i8(i1 zeroext %c, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {279; CHECK-LABEL: select_nxv4i8:280; CHECK: # %bb.0:281; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma282; CHECK-NEXT: vmv.v.x v10, a0283; CHECK-NEXT: vmsne.vi v0, v10, 0284; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0285; CHECK-NEXT: ret286 %v = select i1 %c, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b287 ret <vscale x 4 x i8> %v288}289 290define <vscale x 4 x i8> @selectcc_nxv4i8(i8 signext %a, i8 signext %b, <vscale x 4 x i8> %c, <vscale x 4 x i8> %d) {291; CHECK-LABEL: selectcc_nxv4i8:292; CHECK: # %bb.0:293; CHECK-NEXT: xor a0, a0, a1294; CHECK-NEXT: snez a0, a0295; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma296; CHECK-NEXT: vmv.v.x v10, a0297; CHECK-NEXT: vmsne.vi v0, v10, 0298; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0299; CHECK-NEXT: ret300 %cmp = icmp ne i8 %a, %b301 %v = select i1 %cmp, <vscale x 4 x i8> %c, <vscale x 4 x i8> %d302 ret <vscale x 4 x i8> %v303}304 305define <vscale x 8 x i8> @select_nxv8i8(i1 zeroext %c, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {306; CHECK-LABEL: select_nxv8i8:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma309; CHECK-NEXT: vmv.v.x v10, a0310; CHECK-NEXT: vmsne.vi v0, v10, 0311; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0312; CHECK-NEXT: ret313 %v = select i1 %c, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b314 ret <vscale x 8 x i8> %v315}316 317define <vscale x 8 x i8> @selectcc_nxv8i8(i8 signext %a, i8 signext %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d) {318; CHECK-LABEL: selectcc_nxv8i8:319; CHECK: # %bb.0:320; CHECK-NEXT: xor a0, a0, a1321; CHECK-NEXT: snez a0, a0322; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma323; CHECK-NEXT: vmv.v.x v10, a0324; CHECK-NEXT: vmsne.vi v0, v10, 0325; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0326; CHECK-NEXT: ret327 %cmp = icmp ne i8 %a, %b328 %v = select i1 %cmp, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d329 ret <vscale x 8 x i8> %v330}331 332define <vscale x 16 x i8> @select_nxv16i8(i1 zeroext %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {333; CHECK-LABEL: select_nxv16i8:334; CHECK: # %bb.0:335; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma336; CHECK-NEXT: vmv.v.x v12, a0337; CHECK-NEXT: vmsne.vi v0, v12, 0338; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0339; CHECK-NEXT: ret340 %v = select i1 %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b341 ret <vscale x 16 x i8> %v342}343 344define <vscale x 16 x i8> @selectcc_nxv16i8(i8 signext %a, i8 signext %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d) {345; CHECK-LABEL: selectcc_nxv16i8:346; CHECK: # %bb.0:347; CHECK-NEXT: xor a0, a0, a1348; CHECK-NEXT: snez a0, a0349; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma350; CHECK-NEXT: vmv.v.x v12, a0351; CHECK-NEXT: vmsne.vi v0, v12, 0352; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0353; CHECK-NEXT: ret354 %cmp = icmp ne i8 %a, %b355 %v = select i1 %cmp, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d356 ret <vscale x 16 x i8> %v357}358 359define <vscale x 32 x i8> @select_nxv32i8(i1 zeroext %c, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {360; CHECK-LABEL: select_nxv32i8:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma363; CHECK-NEXT: vmv.v.x v16, a0364; CHECK-NEXT: vmsne.vi v0, v16, 0365; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0366; CHECK-NEXT: ret367 %v = select i1 %c, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b368 ret <vscale x 32 x i8> %v369}370 371define <vscale x 32 x i8> @selectcc_nxv32i8(i8 signext %a, i8 signext %b, <vscale x 32 x i8> %c, <vscale x 32 x i8> %d) {372; CHECK-LABEL: selectcc_nxv32i8:373; CHECK: # %bb.0:374; CHECK-NEXT: xor a0, a0, a1375; CHECK-NEXT: snez a0, a0376; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma377; CHECK-NEXT: vmv.v.x v16, a0378; CHECK-NEXT: vmsne.vi v0, v16, 0379; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0380; CHECK-NEXT: ret381 %cmp = icmp ne i8 %a, %b382 %v = select i1 %cmp, <vscale x 32 x i8> %c, <vscale x 32 x i8> %d383 ret <vscale x 32 x i8> %v384}385 386define <vscale x 64 x i8> @select_nxv64i8(i1 zeroext %c, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {387; CHECK-LABEL: select_nxv64i8:388; CHECK: # %bb.0:389; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma390; CHECK-NEXT: vmv.v.x v24, a0391; CHECK-NEXT: vmsne.vi v0, v24, 0392; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0393; CHECK-NEXT: ret394 %v = select i1 %c, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b395 ret <vscale x 64 x i8> %v396}397 398define <vscale x 64 x i8> @selectcc_nxv64i8(i8 signext %a, i8 signext %b, <vscale x 64 x i8> %c, <vscale x 64 x i8> %d) {399; CHECK-LABEL: selectcc_nxv64i8:400; CHECK: # %bb.0:401; CHECK-NEXT: xor a0, a0, a1402; CHECK-NEXT: snez a0, a0403; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma404; CHECK-NEXT: vmv.v.x v24, a0405; CHECK-NEXT: vmsne.vi v0, v24, 0406; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0407; CHECK-NEXT: ret408 %cmp = icmp ne i8 %a, %b409 %v = select i1 %cmp, <vscale x 64 x i8> %c, <vscale x 64 x i8> %d410 ret <vscale x 64 x i8> %v411}412 413define <vscale x 1 x i16> @select_nxv1i16(i1 zeroext %c, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b) {414; CHECK-LABEL: select_nxv1i16:415; CHECK: # %bb.0:416; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma417; CHECK-NEXT: vmv.v.x v10, a0418; CHECK-NEXT: vmsne.vi v0, v10, 0419; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma420; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0421; CHECK-NEXT: ret422 %v = select i1 %c, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b423 ret <vscale x 1 x i16> %v424}425 426define <vscale x 1 x i16> @selectcc_nxv1i16(i16 signext %a, i16 signext %b, <vscale x 1 x i16> %c, <vscale x 1 x i16> %d) {427; CHECK-LABEL: selectcc_nxv1i16:428; CHECK: # %bb.0:429; CHECK-NEXT: xor a0, a0, a1430; CHECK-NEXT: snez a0, a0431; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma432; CHECK-NEXT: vmv.v.x v10, a0433; CHECK-NEXT: vmsne.vi v0, v10, 0434; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma435; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0436; CHECK-NEXT: ret437 %cmp = icmp ne i16 %a, %b438 %v = select i1 %cmp, <vscale x 1 x i16> %c, <vscale x 1 x i16> %d439 ret <vscale x 1 x i16> %v440}441 442define <vscale x 2 x i16> @select_nxv2i16(i1 zeroext %c, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b) {443; CHECK-LABEL: select_nxv2i16:444; CHECK: # %bb.0:445; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma446; CHECK-NEXT: vmv.v.x v10, a0447; CHECK-NEXT: vmsne.vi v0, v10, 0448; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma449; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0450; CHECK-NEXT: ret451 %v = select i1 %c, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b452 ret <vscale x 2 x i16> %v453}454 455define <vscale x 2 x i16> @selectcc_nxv2i16(i16 signext %a, i16 signext %b, <vscale x 2 x i16> %c, <vscale x 2 x i16> %d) {456; CHECK-LABEL: selectcc_nxv2i16:457; CHECK: # %bb.0:458; CHECK-NEXT: xor a0, a0, a1459; CHECK-NEXT: snez a0, a0460; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma461; CHECK-NEXT: vmv.v.x v10, a0462; CHECK-NEXT: vmsne.vi v0, v10, 0463; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma464; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0465; CHECK-NEXT: ret466 %cmp = icmp ne i16 %a, %b467 %v = select i1 %cmp, <vscale x 2 x i16> %c, <vscale x 2 x i16> %d468 ret <vscale x 2 x i16> %v469}470 471define <vscale x 4 x i16> @select_nxv4i16(i1 zeroext %c, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {472; CHECK-LABEL: select_nxv4i16:473; CHECK: # %bb.0:474; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma475; CHECK-NEXT: vmv.v.x v10, a0476; CHECK-NEXT: vmsne.vi v0, v10, 0477; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma478; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0479; CHECK-NEXT: ret480 %v = select i1 %c, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b481 ret <vscale x 4 x i16> %v482}483 484define <vscale x 4 x i16> @selectcc_nxv4i16(i16 signext %a, i16 signext %b, <vscale x 4 x i16> %c, <vscale x 4 x i16> %d) {485; CHECK-LABEL: selectcc_nxv4i16:486; CHECK: # %bb.0:487; CHECK-NEXT: xor a0, a0, a1488; CHECK-NEXT: snez a0, a0489; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma490; CHECK-NEXT: vmv.v.x v10, a0491; CHECK-NEXT: vmsne.vi v0, v10, 0492; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma493; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0494; CHECK-NEXT: ret495 %cmp = icmp ne i16 %a, %b496 %v = select i1 %cmp, <vscale x 4 x i16> %c, <vscale x 4 x i16> %d497 ret <vscale x 4 x i16> %v498}499 500define <vscale x 8 x i16> @select_nxv8i16(i1 zeroext %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {501; CHECK-LABEL: select_nxv8i16:502; CHECK: # %bb.0:503; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma504; CHECK-NEXT: vmv.v.x v12, a0505; CHECK-NEXT: vmsne.vi v0, v12, 0506; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma507; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0508; CHECK-NEXT: ret509 %v = select i1 %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b510 ret <vscale x 8 x i16> %v511}512 513define <vscale x 8 x i16> @selectcc_nxv8i16(i16 signext %a, i16 signext %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d) {514; CHECK-LABEL: selectcc_nxv8i16:515; CHECK: # %bb.0:516; CHECK-NEXT: xor a0, a0, a1517; CHECK-NEXT: snez a0, a0518; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma519; CHECK-NEXT: vmv.v.x v12, a0520; CHECK-NEXT: vmsne.vi v0, v12, 0521; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma522; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0523; CHECK-NEXT: ret524 %cmp = icmp ne i16 %a, %b525 %v = select i1 %cmp, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d526 ret <vscale x 8 x i16> %v527}528 529define <vscale x 16 x i16> @select_nxv16i16(i1 zeroext %c, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {530; CHECK-LABEL: select_nxv16i16:531; CHECK: # %bb.0:532; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma533; CHECK-NEXT: vmv.v.x v16, a0534; CHECK-NEXT: vmsne.vi v0, v16, 0535; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma536; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0537; CHECK-NEXT: ret538 %v = select i1 %c, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b539 ret <vscale x 16 x i16> %v540}541 542define <vscale x 16 x i16> @selectcc_nxv16i16(i16 signext %a, i16 signext %b, <vscale x 16 x i16> %c, <vscale x 16 x i16> %d) {543; CHECK-LABEL: selectcc_nxv16i16:544; CHECK: # %bb.0:545; CHECK-NEXT: xor a0, a0, a1546; CHECK-NEXT: snez a0, a0547; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma548; CHECK-NEXT: vmv.v.x v16, a0549; CHECK-NEXT: vmsne.vi v0, v16, 0550; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma551; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0552; CHECK-NEXT: ret553 %cmp = icmp ne i16 %a, %b554 %v = select i1 %cmp, <vscale x 16 x i16> %c, <vscale x 16 x i16> %d555 ret <vscale x 16 x i16> %v556}557 558define <vscale x 32 x i16> @select_nxv32i16(i1 zeroext %c, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {559; CHECK-LABEL: select_nxv32i16:560; CHECK: # %bb.0:561; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma562; CHECK-NEXT: vmv.v.x v24, a0563; CHECK-NEXT: vmsne.vi v0, v24, 0564; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma565; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0566; CHECK-NEXT: ret567 %v = select i1 %c, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b568 ret <vscale x 32 x i16> %v569}570 571define <vscale x 32 x i16> @selectcc_nxv32i16(i16 signext %a, i16 signext %b, <vscale x 32 x i16> %c, <vscale x 32 x i16> %d) {572; CHECK-LABEL: selectcc_nxv32i16:573; CHECK: # %bb.0:574; CHECK-NEXT: xor a0, a0, a1575; CHECK-NEXT: snez a0, a0576; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma577; CHECK-NEXT: vmv.v.x v24, a0578; CHECK-NEXT: vmsne.vi v0, v24, 0579; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma580; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0581; CHECK-NEXT: ret582 %cmp = icmp ne i16 %a, %b583 %v = select i1 %cmp, <vscale x 32 x i16> %c, <vscale x 32 x i16> %d584 ret <vscale x 32 x i16> %v585}586 587define <vscale x 1 x i32> @select_nxv1i32(i1 zeroext %c, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {588; CHECK-LABEL: select_nxv1i32:589; CHECK: # %bb.0:590; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma591; CHECK-NEXT: vmv.v.x v10, a0592; CHECK-NEXT: vmsne.vi v0, v10, 0593; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma594; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0595; CHECK-NEXT: ret596 %v = select i1 %c, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b597 ret <vscale x 1 x i32> %v598}599 600define <vscale x 1 x i32> @selectcc_nxv1i32(i32 signext %a, i32 signext %b, <vscale x 1 x i32> %c, <vscale x 1 x i32> %d) {601; CHECK-LABEL: selectcc_nxv1i32:602; CHECK: # %bb.0:603; CHECK-NEXT: xor a0, a0, a1604; CHECK-NEXT: snez a0, a0605; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma606; CHECK-NEXT: vmv.v.x v10, a0607; CHECK-NEXT: vmsne.vi v0, v10, 0608; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma609; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0610; CHECK-NEXT: ret611 %cmp = icmp ne i32 %a, %b612 %v = select i1 %cmp, <vscale x 1 x i32> %c, <vscale x 1 x i32> %d613 ret <vscale x 1 x i32> %v614}615 616define <vscale x 2 x i32> @select_nxv2i32(i1 zeroext %c, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {617; CHECK-LABEL: select_nxv2i32:618; CHECK: # %bb.0:619; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma620; CHECK-NEXT: vmv.v.x v10, a0621; CHECK-NEXT: vmsne.vi v0, v10, 0622; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma623; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0624; CHECK-NEXT: ret625 %v = select i1 %c, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b626 ret <vscale x 2 x i32> %v627}628 629define <vscale x 2 x i32> @selectcc_nxv2i32(i32 signext %a, i32 signext %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d) {630; CHECK-LABEL: selectcc_nxv2i32:631; CHECK: # %bb.0:632; CHECK-NEXT: xor a0, a0, a1633; CHECK-NEXT: snez a0, a0634; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma635; CHECK-NEXT: vmv.v.x v10, a0636; CHECK-NEXT: vmsne.vi v0, v10, 0637; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma638; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0639; CHECK-NEXT: ret640 %cmp = icmp ne i32 %a, %b641 %v = select i1 %cmp, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d642 ret <vscale x 2 x i32> %v643}644 645define <vscale x 4 x i32> @select_nxv4i32(i1 zeroext %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {646; CHECK-LABEL: select_nxv4i32:647; CHECK: # %bb.0:648; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma649; CHECK-NEXT: vmv.v.x v12, a0650; CHECK-NEXT: vmsne.vi v0, v12, 0651; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma652; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0653; CHECK-NEXT: ret654 %v = select i1 %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b655 ret <vscale x 4 x i32> %v656}657 658define <vscale x 4 x i32> @selectcc_nxv4i32(i32 signext %a, i32 signext %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d) {659; CHECK-LABEL: selectcc_nxv4i32:660; CHECK: # %bb.0:661; CHECK-NEXT: xor a0, a0, a1662; CHECK-NEXT: snez a0, a0663; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma664; CHECK-NEXT: vmv.v.x v12, a0665; CHECK-NEXT: vmsne.vi v0, v12, 0666; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma667; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0668; CHECK-NEXT: ret669 %cmp = icmp ne i32 %a, %b670 %v = select i1 %cmp, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d671 ret <vscale x 4 x i32> %v672}673 674define <vscale x 8 x i32> @select_nxv8i32(i1 zeroext %c, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {675; CHECK-LABEL: select_nxv8i32:676; CHECK: # %bb.0:677; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma678; CHECK-NEXT: vmv.v.x v16, a0679; CHECK-NEXT: vmsne.vi v0, v16, 0680; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma681; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0682; CHECK-NEXT: ret683 %v = select i1 %c, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b684 ret <vscale x 8 x i32> %v685}686 687define <vscale x 8 x i32> @selectcc_nxv8i32(i32 signext %a, i32 signext %b, <vscale x 8 x i32> %c, <vscale x 8 x i32> %d) {688; CHECK-LABEL: selectcc_nxv8i32:689; CHECK: # %bb.0:690; CHECK-NEXT: xor a0, a0, a1691; CHECK-NEXT: snez a0, a0692; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma693; CHECK-NEXT: vmv.v.x v16, a0694; CHECK-NEXT: vmsne.vi v0, v16, 0695; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma696; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0697; CHECK-NEXT: ret698 %cmp = icmp ne i32 %a, %b699 %v = select i1 %cmp, <vscale x 8 x i32> %c, <vscale x 8 x i32> %d700 ret <vscale x 8 x i32> %v701}702 703define <vscale x 16 x i32> @select_nxv16i32(i1 zeroext %c, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {704; CHECK-LABEL: select_nxv16i32:705; CHECK: # %bb.0:706; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma707; CHECK-NEXT: vmv.v.x v24, a0708; CHECK-NEXT: vmsne.vi v0, v24, 0709; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma710; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0711; CHECK-NEXT: ret712 %v = select i1 %c, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b713 ret <vscale x 16 x i32> %v714}715 716define <vscale x 16 x i32> @selectcc_nxv16i32(i32 signext %a, i32 signext %b, <vscale x 16 x i32> %c, <vscale x 16 x i32> %d) {717; CHECK-LABEL: selectcc_nxv16i32:718; CHECK: # %bb.0:719; CHECK-NEXT: xor a0, a0, a1720; CHECK-NEXT: snez a0, a0721; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma722; CHECK-NEXT: vmv.v.x v24, a0723; CHECK-NEXT: vmsne.vi v0, v24, 0724; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma725; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0726; CHECK-NEXT: ret727 %cmp = icmp ne i32 %a, %b728 %v = select i1 %cmp, <vscale x 16 x i32> %c, <vscale x 16 x i32> %d729 ret <vscale x 16 x i32> %v730}731 732define <vscale x 1 x i64> @select_nxv1i64(i1 zeroext %c, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {733; CHECK-LABEL: select_nxv1i64:734; CHECK: # %bb.0:735; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma736; CHECK-NEXT: vmv.v.x v10, a0737; CHECK-NEXT: vmsne.vi v0, v10, 0738; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma739; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0740; CHECK-NEXT: ret741 %v = select i1 %c, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b742 ret <vscale x 1 x i64> %v743}744 745define <vscale x 1 x i64> @selectcc_nxv1i64(i64 signext %a, i64 signext %b, <vscale x 1 x i64> %c, <vscale x 1 x i64> %d) {746; RV32-LABEL: selectcc_nxv1i64:747; RV32: # %bb.0:748; RV32-NEXT: xor a1, a1, a3749; RV32-NEXT: xor a0, a0, a2750; RV32-NEXT: or a0, a0, a1751; RV32-NEXT: snez a0, a0752; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma753; RV32-NEXT: vmv.v.x v10, a0754; RV32-NEXT: vmsne.vi v0, v10, 0755; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma756; RV32-NEXT: vmerge.vvm v8, v9, v8, v0757; RV32-NEXT: ret758;759; RV64-LABEL: selectcc_nxv1i64:760; RV64: # %bb.0:761; RV64-NEXT: xor a0, a0, a1762; RV64-NEXT: snez a0, a0763; RV64-NEXT: vsetvli a1, zero, e8, mf8, ta, ma764; RV64-NEXT: vmv.v.x v10, a0765; RV64-NEXT: vmsne.vi v0, v10, 0766; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma767; RV64-NEXT: vmerge.vvm v8, v9, v8, v0768; RV64-NEXT: ret769 %cmp = icmp ne i64 %a, %b770 %v = select i1 %cmp, <vscale x 1 x i64> %c, <vscale x 1 x i64> %d771 ret <vscale x 1 x i64> %v772}773 774define <vscale x 2 x i64> @select_nxv2i64(i1 zeroext %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {775; CHECK-LABEL: select_nxv2i64:776; CHECK: # %bb.0:777; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma778; CHECK-NEXT: vmv.v.x v12, a0779; CHECK-NEXT: vmsne.vi v0, v12, 0780; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma781; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0782; CHECK-NEXT: ret783 %v = select i1 %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b784 ret <vscale x 2 x i64> %v785}786 787define <vscale x 2 x i64> @selectcc_nxv2i64(i64 signext %a, i64 signext %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d) {788; RV32-LABEL: selectcc_nxv2i64:789; RV32: # %bb.0:790; RV32-NEXT: xor a1, a1, a3791; RV32-NEXT: xor a0, a0, a2792; RV32-NEXT: or a0, a0, a1793; RV32-NEXT: snez a0, a0794; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma795; RV32-NEXT: vmv.v.x v12, a0796; RV32-NEXT: vmsne.vi v0, v12, 0797; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma798; RV32-NEXT: vmerge.vvm v8, v10, v8, v0799; RV32-NEXT: ret800;801; RV64-LABEL: selectcc_nxv2i64:802; RV64: # %bb.0:803; RV64-NEXT: xor a0, a0, a1804; RV64-NEXT: snez a0, a0805; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma806; RV64-NEXT: vmv.v.x v12, a0807; RV64-NEXT: vmsne.vi v0, v12, 0808; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma809; RV64-NEXT: vmerge.vvm v8, v10, v8, v0810; RV64-NEXT: ret811 %cmp = icmp ne i64 %a, %b812 %v = select i1 %cmp, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d813 ret <vscale x 2 x i64> %v814}815 816define <vscale x 4 x i64> @select_nxv4i64(i1 zeroext %c, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {817; CHECK-LABEL: select_nxv4i64:818; CHECK: # %bb.0:819; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma820; CHECK-NEXT: vmv.v.x v16, a0821; CHECK-NEXT: vmsne.vi v0, v16, 0822; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma823; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0824; CHECK-NEXT: ret825 %v = select i1 %c, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b826 ret <vscale x 4 x i64> %v827}828 829define <vscale x 4 x i64> @selectcc_nxv4i64(i64 signext %a, i64 signext %b, <vscale x 4 x i64> %c, <vscale x 4 x i64> %d) {830; RV32-LABEL: selectcc_nxv4i64:831; RV32: # %bb.0:832; RV32-NEXT: xor a1, a1, a3833; RV32-NEXT: xor a0, a0, a2834; RV32-NEXT: or a0, a0, a1835; RV32-NEXT: snez a0, a0836; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma837; RV32-NEXT: vmv.v.x v16, a0838; RV32-NEXT: vmsne.vi v0, v16, 0839; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma840; RV32-NEXT: vmerge.vvm v8, v12, v8, v0841; RV32-NEXT: ret842;843; RV64-LABEL: selectcc_nxv4i64:844; RV64: # %bb.0:845; RV64-NEXT: xor a0, a0, a1846; RV64-NEXT: snez a0, a0847; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma848; RV64-NEXT: vmv.v.x v16, a0849; RV64-NEXT: vmsne.vi v0, v16, 0850; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma851; RV64-NEXT: vmerge.vvm v8, v12, v8, v0852; RV64-NEXT: ret853 %cmp = icmp ne i64 %a, %b854 %v = select i1 %cmp, <vscale x 4 x i64> %c, <vscale x 4 x i64> %d855 ret <vscale x 4 x i64> %v856}857 858define <vscale x 8 x i64> @select_nxv8i64(i1 zeroext %c, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {859; CHECK-LABEL: select_nxv8i64:860; CHECK: # %bb.0:861; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma862; CHECK-NEXT: vmv.v.x v24, a0863; CHECK-NEXT: vmsne.vi v0, v24, 0864; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma865; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0866; CHECK-NEXT: ret867 %v = select i1 %c, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b868 ret <vscale x 8 x i64> %v869}870 871define <vscale x 8 x i64> @selectcc_nxv8i64(i64 signext %a, i64 signext %b, <vscale x 8 x i64> %c, <vscale x 8 x i64> %d) {872; RV32-LABEL: selectcc_nxv8i64:873; RV32: # %bb.0:874; RV32-NEXT: xor a1, a1, a3875; RV32-NEXT: xor a0, a0, a2876; RV32-NEXT: or a0, a0, a1877; RV32-NEXT: snez a0, a0878; RV32-NEXT: vsetvli a1, zero, e8, m1, ta, ma879; RV32-NEXT: vmv.v.x v24, a0880; RV32-NEXT: vmsne.vi v0, v24, 0881; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma882; RV32-NEXT: vmerge.vvm v8, v16, v8, v0883; RV32-NEXT: ret884;885; RV64-LABEL: selectcc_nxv8i64:886; RV64: # %bb.0:887; RV64-NEXT: xor a0, a0, a1888; RV64-NEXT: snez a0, a0889; RV64-NEXT: vsetvli a1, zero, e8, m1, ta, ma890; RV64-NEXT: vmv.v.x v24, a0891; RV64-NEXT: vmsne.vi v0, v24, 0892; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma893; RV64-NEXT: vmerge.vvm v8, v16, v8, v0894; RV64-NEXT: ret895 %cmp = icmp ne i64 %a, %b896 %v = select i1 %cmp, <vscale x 8 x i64> %c, <vscale x 8 x i64> %d897 ret <vscale x 8 x i64> %v898}899