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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV644 5; This test checks a regression in the select-to-sra transform, which was6; asserting (without a precondition) when the vector constants implicitly7; truncated their inputs, as we do on RV64.8define <4 x i32> @vselect_of_consts(<4 x i1> %cc) {9; RV32-LABEL: vselect_of_consts:10; RV32: # %bb.0:11; RV32-NEXT: lui a0, 28428012; RV32-NEXT: addi a0, a0, 29113; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma14; RV32-NEXT: vmv.v.x v8, a015; RV32-NEXT: lui a0, 21437616; RV32-NEXT: addi a0, a0, -203017; RV32-NEXT: vmerge.vxm v8, v8, a0, v018; RV32-NEXT: ret19;20; RV64-LABEL: vselect_of_consts:21; RV64: # %bb.0:22; RV64-NEXT: lui a0, 28428023; RV64-NEXT: addi a0, a0, 29124; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma25; RV64-NEXT: vmv.v.x v8, a026; RV64-NEXT: lui a0, 21437627; RV64-NEXT: addi a0, a0, -203028; RV64-NEXT: vmerge.vxm v8, v8, a0, v029; RV64-NEXT: ret30 %v = select <4 x i1> %cc, <4 x i32> <i32 878082066, i32 878082066, i32 878082066, i32 878082066>, <4 x i32> <i32 1164411171, i32 1164411171, i32 1164411171, i32 1164411171>31 ret <4 x i32> %v32}33