brintos / llvm-project-archived public Read only

1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+m,+v \3; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+m,+v \5; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 3 x i1> @icmp_eq_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb) {8; CHECK-LABEL: icmp_eq_vv_nxv3i8:9; CHECK:       # %bb.0:10; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma11; CHECK-NEXT:    vmseq.vv v0, v8, v912; CHECK-NEXT:    ret13  %vc = icmp eq <vscale x 3 x i8> %va, %vb14  ret <vscale x 3 x i1> %vc15}16 17define <vscale x 3 x i1> @icmp_eq_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b) {18; CHECK-LABEL: icmp_eq_vx_nxv3i8:19; CHECK:       # %bb.0:20; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma21; CHECK-NEXT:    vmseq.vx v0, v8, a022; CHECK-NEXT:    ret23  %head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 024  %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer25  %vc = icmp eq <vscale x 3 x i8> %va, %splat26  ret <vscale x 3 x i1> %vc27}28 29define <vscale x 3 x i1> @icmp_eq_xv_nxv3i8(<vscale x 3 x i8> %va, i8 %b) {30; CHECK-LABEL: icmp_eq_xv_nxv3i8:31; CHECK:       # %bb.0:32; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma33; CHECK-NEXT:    vmseq.vx v0, v8, a034; CHECK-NEXT:    ret35  %head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 036  %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer37  %vc = icmp eq <vscale x 3 x i8> %splat, %va38  ret <vscale x 3 x i1> %vc39}40 41define <vscale x 8 x i1> @icmp_eq_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {42; CHECK-LABEL: icmp_eq_vv_nxv8i8:43; CHECK:       # %bb.0:44; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma45; CHECK-NEXT:    vmseq.vv v0, v8, v946; CHECK-NEXT:    ret47  %vc = icmp eq <vscale x 8 x i8> %va, %vb48  ret <vscale x 8 x i1> %vc49}50 51define <vscale x 8 x i1> @icmp_eq_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {52; CHECK-LABEL: icmp_eq_vx_nxv8i8:53; CHECK:       # %bb.0:54; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma55; CHECK-NEXT:    vmseq.vx v0, v8, a056; CHECK-NEXT:    ret57  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 058  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer59  %vc = icmp eq <vscale x 8 x i8> %va, %splat60  ret <vscale x 8 x i1> %vc61}62 63define <vscale x 8 x i1> @icmp_eq_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {64; CHECK-LABEL: icmp_eq_xv_nxv8i8:65; CHECK:       # %bb.0:66; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma67; CHECK-NEXT:    vmseq.vx v0, v8, a068; CHECK-NEXT:    ret69  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 070  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer71  %vc = icmp eq <vscale x 8 x i8> %splat, %va72  ret <vscale x 8 x i1> %vc73}74 75define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_0(<vscale x 8 x i8> %va) {76; CHECK-LABEL: icmp_eq_vi_nxv8i8_0:77; CHECK:       # %bb.0:78; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma79; CHECK-NEXT:    vmseq.vi v0, v8, 080; CHECK-NEXT:    ret81  %vc = icmp eq <vscale x 8 x i8> %va, splat (i8 0)82  ret <vscale x 8 x i1> %vc83}84 85define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_1(<vscale x 8 x i8> %va) {86; CHECK-LABEL: icmp_eq_vi_nxv8i8_1:87; CHECK:       # %bb.0:88; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma89; CHECK-NEXT:    vmseq.vi v0, v8, 590; CHECK-NEXT:    ret91  %vc = icmp eq <vscale x 8 x i8> %va, splat (i8 5)92  ret <vscale x 8 x i1> %vc93}94 95define <vscale x 8 x i1> @icmp_eq_iv_nxv8i8_1(<vscale x 8 x i8> %va) {96; CHECK-LABEL: icmp_eq_iv_nxv8i8_1:97; CHECK:       # %bb.0:98; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma99; CHECK-NEXT:    vmseq.vi v0, v8, 5100; CHECK-NEXT:    ret101  %vc = icmp eq <vscale x 8 x i8> splat (i8 5), %va102  ret <vscale x 8 x i1> %vc103}104 105define <vscale x 8 x i1> @icmp_ne_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {106; CHECK-LABEL: icmp_ne_vv_nxv8i8:107; CHECK:       # %bb.0:108; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma109; CHECK-NEXT:    vmsne.vv v0, v8, v9110; CHECK-NEXT:    ret111  %vc = icmp ne <vscale x 8 x i8> %va, %vb112  ret <vscale x 8 x i1> %vc113}114 115define <vscale x 8 x i1> @icmp_ne_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {116; CHECK-LABEL: icmp_ne_vx_nxv8i8:117; CHECK:       # %bb.0:118; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma119; CHECK-NEXT:    vmsne.vx v0, v8, a0120; CHECK-NEXT:    ret121  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0122  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer123  %vc = icmp ne <vscale x 8 x i8> %va, %splat124  ret <vscale x 8 x i1> %vc125}126 127define <vscale x 8 x i1> @icmp_ne_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {128; CHECK-LABEL: icmp_ne_xv_nxv8i8:129; CHECK:       # %bb.0:130; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma131; CHECK-NEXT:    vmsne.vx v0, v8, a0132; CHECK-NEXT:    ret133  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0134  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer135  %vc = icmp ne <vscale x 8 x i8> %splat, %va136  ret <vscale x 8 x i1> %vc137}138 139define <vscale x 8 x i1> @icmp_ne_vi_nxv8i8_0(<vscale x 8 x i8> %va) {140; CHECK-LABEL: icmp_ne_vi_nxv8i8_0:141; CHECK:       # %bb.0:142; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma143; CHECK-NEXT:    vmsne.vi v0, v8, 5144; CHECK-NEXT:    ret145  %vc = icmp ne <vscale x 8 x i8> %va, splat (i8 5)146  ret <vscale x 8 x i1> %vc147}148 149define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {150; CHECK-LABEL: icmp_ugt_vv_nxv8i8:151; CHECK:       # %bb.0:152; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma153; CHECK-NEXT:    vmsltu.vv v0, v9, v8154; CHECK-NEXT:    ret155  %vc = icmp ugt <vscale x 8 x i8> %va, %vb156  ret <vscale x 8 x i1> %vc157}158 159define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {160; CHECK-LABEL: icmp_ugt_vx_nxv8i8:161; CHECK:       # %bb.0:162; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma163; CHECK-NEXT:    vmsgtu.vx v0, v8, a0164; CHECK-NEXT:    ret165  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0166  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer167  %vc = icmp ugt <vscale x 8 x i8> %va, %splat168  ret <vscale x 8 x i1> %vc169}170 171define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {172; CHECK-LABEL: icmp_ugt_xv_nxv8i8:173; CHECK:       # %bb.0:174; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma175; CHECK-NEXT:    vmsltu.vx v0, v8, a0176; CHECK-NEXT:    ret177  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0178  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer179  %vc = icmp ugt <vscale x 8 x i8> %splat, %va180  ret <vscale x 8 x i1> %vc181}182 183define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {184; CHECK-LABEL: icmp_ugt_vi_nxv8i8_0:185; CHECK:       # %bb.0:186; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma187; CHECK-NEXT:    vmsgtu.vi v0, v8, 5188; CHECK-NEXT:    ret189  %vc = icmp ugt <vscale x 8 x i8> %va, splat (i8 5)190  ret <vscale x 8 x i1> %vc191}192 193define <vscale x 8 x i1> @icmp_uge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {194; CHECK-LABEL: icmp_uge_vv_nxv8i8:195; CHECK:       # %bb.0:196; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma197; CHECK-NEXT:    vmsleu.vv v0, v9, v8198; CHECK-NEXT:    ret199  %vc = icmp uge <vscale x 8 x i8> %va, %vb200  ret <vscale x 8 x i1> %vc201}202 203define <vscale x 8 x i1> @icmp_uge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {204; CHECK-LABEL: icmp_uge_vx_nxv8i8:205; CHECK:       # %bb.0:206; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma207; CHECK-NEXT:    vmv.v.x v9, a0208; CHECK-NEXT:    vmsleu.vv v0, v9, v8209; CHECK-NEXT:    ret210  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0211  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer212  %vc = icmp uge <vscale x 8 x i8> %va, %splat213  ret <vscale x 8 x i1> %vc214}215 216define <vscale x 8 x i1> @icmp_uge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {217; CHECK-LABEL: icmp_uge_xv_nxv8i8:218; CHECK:       # %bb.0:219; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma220; CHECK-NEXT:    vmsleu.vx v0, v8, a0221; CHECK-NEXT:    ret222  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0223  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer224  %vc = icmp uge <vscale x 8 x i8> %splat, %va225  ret <vscale x 8 x i1> %vc226}227 228define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {229; CHECK-LABEL: icmp_uge_vi_nxv8i8_0:230; CHECK:       # %bb.0:231; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma232; CHECK-NEXT:    vmv.v.i v9, -16233; CHECK-NEXT:    vmsleu.vv v0, v9, v8234; CHECK-NEXT:    ret235  %vc = icmp uge <vscale x 8 x i8> %va, splat (i8 -16)236  ret <vscale x 8 x i1> %vc237}238 239define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {240; CHECK-LABEL: icmp_uge_vi_nxv8i8_1:241; CHECK:       # %bb.0:242; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma243; CHECK-NEXT:    vmsgtu.vi v0, v8, 14244; CHECK-NEXT:    ret245  %vc = icmp uge <vscale x 8 x i8> %va, splat (i8 15)246  ret <vscale x 8 x i1> %vc247}248 249define <vscale x 8 x i1> @icmp_uge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {250; CHECK-LABEL: icmp_uge_iv_nxv8i8_1:251; CHECK:       # %bb.0:252; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma253; CHECK-NEXT:    vmsleu.vi v0, v8, 15254; CHECK-NEXT:    ret255  %vc = icmp uge <vscale x 8 x i8> splat (i8 15), %va256  ret <vscale x 8 x i1> %vc257}258 259define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {260; CHECK-LABEL: icmp_uge_vi_nxv8i8_2:261; CHECK:       # %bb.0:262; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma263; CHECK-NEXT:    vmset.m v0264; CHECK-NEXT:    ret265  %vc = icmp uge <vscale x 8 x i8> %va, splat (i8 0)266  ret <vscale x 8 x i1> %vc267}268 269define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {270; CHECK-LABEL: icmp_uge_vi_nxv8i8_3:271; CHECK:       # %bb.0:272; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma273; CHECK-NEXT:    vmsgtu.vi v0, v8, 0274; CHECK-NEXT:    ret275  %vc = icmp uge <vscale x 8 x i8> %va, splat (i8 1)276  ret <vscale x 8 x i1> %vc277}278 279define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_4(<vscale x 8 x i8> %va) {280; CHECK-LABEL: icmp_uge_vi_nxv8i8_4:281; CHECK:       # %bb.0:282; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma283; CHECK-NEXT:    vmsgtu.vi v0, v8, -16284; CHECK-NEXT:    ret285  %vc = icmp uge <vscale x 8 x i8> %va, splat (i8 -15)286  ret <vscale x 8 x i1> %vc287}288 289define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) {290; CHECK-LABEL: icmp_uge_vi_nxv8i8_5:291; CHECK:       # %bb.0:292; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma293; CHECK-NEXT:    vmsgtu.vi v0, v8, 15294; CHECK-NEXT:    ret295  %vc = icmp uge <vscale x 8 x i8> %va, splat (i8 16)296  ret <vscale x 8 x i1> %vc297}298 299; Test that we don't optimize uge x, 0 -> ugt x, -1300define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, iXLen %vl) {301; CHECK-LABEL: icmp_uge_vi_nxv8i8_6:302; CHECK:       # %bb.0:303; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma304; CHECK-NEXT:    vmv.v.i v9, 0305; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma306; CHECK-NEXT:    vmsleu.vv v0, v9, v8307; CHECK-NEXT:    ret308  %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8> poison, i8 0, iXLen %vl)309  %vc = icmp uge <vscale x 8 x i8> %va, %splat310  ret <vscale x 8 x i1> %vc311}312 313define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {314; CHECK-LABEL: icmp_ult_vv_nxv8i8:315; CHECK:       # %bb.0:316; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma317; CHECK-NEXT:    vmsltu.vv v0, v8, v9318; CHECK-NEXT:    ret319  %vc = icmp ult <vscale x 8 x i8> %va, %vb320  ret <vscale x 8 x i1> %vc321}322 323define <vscale x 8 x i1> @icmp_ult_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {324; CHECK-LABEL: icmp_ult_vx_nxv8i8:325; CHECK:       # %bb.0:326; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma327; CHECK-NEXT:    vmsltu.vx v0, v8, a0328; CHECK-NEXT:    ret329  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0330  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer331  %vc = icmp ult <vscale x 8 x i8> %va, %splat332  ret <vscale x 8 x i1> %vc333}334 335define <vscale x 8 x i1> @icmp_ult_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {336; CHECK-LABEL: icmp_ult_xv_nxv8i8:337; CHECK:       # %bb.0:338; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma339; CHECK-NEXT:    vmsgtu.vx v0, v8, a0340; CHECK-NEXT:    ret341  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0342  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer343  %vc = icmp ult <vscale x 8 x i8> %splat, %va344  ret <vscale x 8 x i1> %vc345}346 347define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_0(<vscale x 8 x i8> %va) {348; CHECK-LABEL: icmp_ult_vi_nxv8i8_0:349; CHECK:       # %bb.0:350; CHECK-NEXT:    li a0, -16351; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma352; CHECK-NEXT:    vmsltu.vx v0, v8, a0353; CHECK-NEXT:    ret354  %vc = icmp ult <vscale x 8 x i8> %va, splat (i8 -16)355  ret <vscale x 8 x i1> %vc356}357 358define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_1(<vscale x 8 x i8> %va) {359; CHECK-LABEL: icmp_ult_vi_nxv8i8_1:360; CHECK:       # %bb.0:361; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma362; CHECK-NEXT:    vmsleu.vi v0, v8, -16363; CHECK-NEXT:    ret364  %vc = icmp ult <vscale x 8 x i8> %va, splat (i8 -15)365  ret <vscale x 8 x i1> %vc366}367 368define <vscale x 8 x i1> @icmp_ult_iv_nxv8i8_1(<vscale x 8 x i8> %va) {369; CHECK-LABEL: icmp_ult_iv_nxv8i8_1:370; CHECK:       # %bb.0:371; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma372; CHECK-NEXT:    vmsgtu.vi v0, v8, -15373; CHECK-NEXT:    ret374  %vc = icmp ult <vscale x 8 x i8> splat (i8 -15), %va375  ret <vscale x 8 x i1> %vc376}377 378define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_2(<vscale x 8 x i8> %va) {379; CHECK-LABEL: icmp_ult_vi_nxv8i8_2:380; CHECK:       # %bb.0:381; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma382; CHECK-NEXT:    vmclr.m v0383; CHECK-NEXT:    ret384  %vc = icmp ult <vscale x 8 x i8> %va, splat (i8 0)385  ret <vscale x 8 x i1> %vc386}387 388define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_3(<vscale x 8 x i8> %va) {389; CHECK-LABEL: icmp_ult_vi_nxv8i8_3:390; CHECK:       # %bb.0:391; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma392; CHECK-NEXT:    vmseq.vi v0, v8, 0393; CHECK-NEXT:    ret394  %vc = icmp ult <vscale x 8 x i8> %va, splat (i8 1)395  ret <vscale x 8 x i1> %vc396}397 398define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) {399; CHECK-LABEL: icmp_ult_vi_nxv8i8_4:400; CHECK:       # %bb.0:401; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma402; CHECK-NEXT:    vmsleu.vi v0, v8, 15403; CHECK-NEXT:    ret404  %vc = icmp ult <vscale x 8 x i8> %va, splat (i8 16)405  ret <vscale x 8 x i1> %vc406}407 408; Test that we don't optimize ult x, 0 -> ule x, -1409define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_5(<vscale x 8 x i8> %va, iXLen %vl) {410; CHECK-LABEL: icmp_ult_vi_nxv8i8_5:411; CHECK:       # %bb.0:412; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma413; CHECK-NEXT:    vmsltu.vx v0, v8, zero414; CHECK-NEXT:    ret415  %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8> poison, i8 0, iXLen %vl)416  %vc = icmp ult <vscale x 8 x i8> %va, %splat417  ret <vscale x 8 x i1> %vc418}419 420define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {421; CHECK-LABEL: icmp_ule_vv_nxv8i8:422; CHECK:       # %bb.0:423; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma424; CHECK-NEXT:    vmsleu.vv v0, v8, v9425; CHECK-NEXT:    ret426  %vc = icmp ule <vscale x 8 x i8> %va, %vb427  ret <vscale x 8 x i1> %vc428}429 430define <vscale x 8 x i1> @icmp_ule_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {431; CHECK-LABEL: icmp_ule_vx_nxv8i8:432; CHECK:       # %bb.0:433; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma434; CHECK-NEXT:    vmsleu.vx v0, v8, a0435; CHECK-NEXT:    ret436  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0437  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer438  %vc = icmp ule <vscale x 8 x i8> %va, %splat439  ret <vscale x 8 x i1> %vc440}441 442define <vscale x 8 x i1> @icmp_ule_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {443; CHECK-LABEL: icmp_ule_xv_nxv8i8:444; CHECK:       # %bb.0:445; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma446; CHECK-NEXT:    vmv.v.x v9, a0447; CHECK-NEXT:    vmsleu.vv v0, v9, v8448; CHECK-NEXT:    ret449  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0450  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer451  %vc = icmp ule <vscale x 8 x i8> %splat, %va452  ret <vscale x 8 x i1> %vc453}454 455define <vscale x 8 x i1> @icmp_ule_vi_nxv8i8_0(<vscale x 8 x i8> %va) {456; CHECK-LABEL: icmp_ule_vi_nxv8i8_0:457; CHECK:       # %bb.0:458; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma459; CHECK-NEXT:    vmsleu.vi v0, v8, 5460; CHECK-NEXT:    ret461  %vc = icmp ule <vscale x 8 x i8> %va, splat (i8 5)462  ret <vscale x 8 x i1> %vc463}464 465define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {466; CHECK-LABEL: icmp_sgt_vv_nxv8i8:467; CHECK:       # %bb.0:468; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma469; CHECK-NEXT:    vmslt.vv v0, v9, v8470; CHECK-NEXT:    ret471  %vc = icmp sgt <vscale x 8 x i8> %va, %vb472  ret <vscale x 8 x i1> %vc473}474 475define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {476; CHECK-LABEL: icmp_sgt_vx_nxv8i8:477; CHECK:       # %bb.0:478; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma479; CHECK-NEXT:    vmsgt.vx v0, v8, a0480; CHECK-NEXT:    ret481  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0482  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer483  %vc = icmp sgt <vscale x 8 x i8> %va, %splat484  ret <vscale x 8 x i1> %vc485}486 487define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {488; CHECK-LABEL: icmp_sgt_xv_nxv8i8:489; CHECK:       # %bb.0:490; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma491; CHECK-NEXT:    vmslt.vx v0, v8, a0492; CHECK-NEXT:    ret493  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0494  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer495  %vc = icmp sgt <vscale x 8 x i8> %splat, %va496  ret <vscale x 8 x i1> %vc497}498 499define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {500; CHECK-LABEL: icmp_sgt_vi_nxv8i8_0:501; CHECK:       # %bb.0:502; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma503; CHECK-NEXT:    vmsgt.vi v0, v8, 5504; CHECK-NEXT:    ret505  %vc = icmp sgt <vscale x 8 x i8> %va, splat (i8 5)506  ret <vscale x 8 x i1> %vc507}508 509define <vscale x 8 x i1> @icmp_sge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {510; CHECK-LABEL: icmp_sge_vv_nxv8i8:511; CHECK:       # %bb.0:512; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma513; CHECK-NEXT:    vmsle.vv v0, v9, v8514; CHECK-NEXT:    ret515  %vc = icmp sge <vscale x 8 x i8> %va, %vb516  ret <vscale x 8 x i1> %vc517}518 519define <vscale x 8 x i1> @icmp_sge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {520; CHECK-LABEL: icmp_sge_vx_nxv8i8:521; CHECK:       # %bb.0:522; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma523; CHECK-NEXT:    vmv.v.x v9, a0524; CHECK-NEXT:    vmsle.vv v0, v9, v8525; CHECK-NEXT:    ret526  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0527  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer528  %vc = icmp sge <vscale x 8 x i8> %va, %splat529  ret <vscale x 8 x i1> %vc530}531 532define <vscale x 8 x i1> @icmp_sge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {533; CHECK-LABEL: icmp_sge_xv_nxv8i8:534; CHECK:       # %bb.0:535; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma536; CHECK-NEXT:    vmsle.vx v0, v8, a0537; CHECK-NEXT:    ret538  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0539  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer540  %vc = icmp sge <vscale x 8 x i8> %splat, %va541  ret <vscale x 8 x i1> %vc542}543 544define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {545; CHECK-LABEL: icmp_sge_vi_nxv8i8_0:546; CHECK:       # %bb.0:547; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma548; CHECK-NEXT:    vmv.v.i v9, -16549; CHECK-NEXT:    vmsle.vv v0, v9, v8550; CHECK-NEXT:    ret551  %vc = icmp sge <vscale x 8 x i8> %va, splat (i8 -16)552  ret <vscale x 8 x i1> %vc553}554 555define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {556; CHECK-LABEL: icmp_sge_vi_nxv8i8_1:557; CHECK:       # %bb.0:558; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma559; CHECK-NEXT:    vmsgt.vi v0, v8, -16560; CHECK-NEXT:    ret561  %vc = icmp sge <vscale x 8 x i8> %va, splat (i8 -15)562  ret <vscale x 8 x i1> %vc563}564 565define <vscale x 8 x i1> @icmp_sge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {566; CHECK-LABEL: icmp_sge_iv_nxv8i8_1:567; CHECK:       # %bb.0:568; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma569; CHECK-NEXT:    vmsle.vi v0, v8, -15570; CHECK-NEXT:    ret571  %vc = icmp sge <vscale x 8 x i8> splat (i8 -15), %va572  ret <vscale x 8 x i1> %vc573}574 575define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {576; CHECK-LABEL: icmp_sge_vi_nxv8i8_2:577; CHECK:       # %bb.0:578; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma579; CHECK-NEXT:    vmsgt.vi v0, v8, -1580; CHECK-NEXT:    ret581  %vc = icmp sge <vscale x 8 x i8> %va, splat (i8 0)582  ret <vscale x 8 x i1> %vc583}584 585define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {586; CHECK-LABEL: icmp_sge_vi_nxv8i8_3:587; CHECK:       # %bb.0:588; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma589; CHECK-NEXT:    vmsgt.vi v0, v8, 15590; CHECK-NEXT:    ret591  %vc = icmp sge <vscale x 8 x i8> %va, splat (i8 16)592  ret <vscale x 8 x i1> %vc593}594 595define <vscale x 8 x i1> @icmp_slt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {596; CHECK-LABEL: icmp_slt_vv_nxv8i8:597; CHECK:       # %bb.0:598; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma599; CHECK-NEXT:    vmslt.vv v0, v8, v9600; CHECK-NEXT:    ret601  %vc = icmp slt <vscale x 8 x i8> %va, %vb602  ret <vscale x 8 x i1> %vc603}604 605define <vscale x 8 x i1> @icmp_slt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {606; CHECK-LABEL: icmp_slt_vx_nxv8i8:607; CHECK:       # %bb.0:608; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma609; CHECK-NEXT:    vmslt.vx v0, v8, a0610; CHECK-NEXT:    ret611  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0612  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer613  %vc = icmp slt <vscale x 8 x i8> %va, %splat614  ret <vscale x 8 x i1> %vc615}616 617define <vscale x 8 x i1> @icmp_slt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {618; CHECK-LABEL: icmp_slt_xv_nxv8i8:619; CHECK:       # %bb.0:620; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma621; CHECK-NEXT:    vmsgt.vx v0, v8, a0622; CHECK-NEXT:    ret623  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0624  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer625  %vc = icmp slt <vscale x 8 x i8> %splat, %va626  ret <vscale x 8 x i1> %vc627}628 629define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {630; CHECK-LABEL: icmp_slt_vi_nxv8i8_0:631; CHECK:       # %bb.0:632; CHECK-NEXT:    li a0, -16633; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma634; CHECK-NEXT:    vmslt.vx v0, v8, a0635; CHECK-NEXT:    ret636  %vc = icmp slt <vscale x 8 x i8> %va, splat (i8 -16)637  ret <vscale x 8 x i1> %vc638}639 640define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_1(<vscale x 8 x i8> %va) {641; CHECK-LABEL: icmp_slt_vi_nxv8i8_1:642; CHECK:       # %bb.0:643; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma644; CHECK-NEXT:    vmsle.vi v0, v8, -16645; CHECK-NEXT:    ret646  %vc = icmp slt <vscale x 8 x i8> %va, splat (i8 -15)647  ret <vscale x 8 x i1> %vc648}649 650define <vscale x 8 x i1> @icmp_slt_iv_nxv8i8_1(<vscale x 8 x i8> %va) {651; CHECK-LABEL: icmp_slt_iv_nxv8i8_1:652; CHECK:       # %bb.0:653; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma654; CHECK-NEXT:    vmsgt.vi v0, v8, -15655; CHECK-NEXT:    ret656  %vc = icmp slt <vscale x 8 x i8> splat (i8 -15), %va657  ret <vscale x 8 x i1> %vc658}659 660define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) {661; CHECK-LABEL: icmp_slt_vi_nxv8i8_2:662; CHECK:       # %bb.0:663; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma664; CHECK-NEXT:    vmsle.vi v0, v8, -1665; CHECK-NEXT:    ret666  %vc = icmp slt <vscale x 8 x i8> %va, splat (i8 0)667  ret <vscale x 8 x i1> %vc668}669 670define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_3(<vscale x 8 x i8> %va) {671; CHECK-LABEL: icmp_slt_vi_nxv8i8_3:672; CHECK:       # %bb.0:673; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma674; CHECK-NEXT:    vmsle.vi v0, v8, 15675; CHECK-NEXT:    ret676  %vc = icmp slt <vscale x 8 x i8> %va, splat (i8 16)677  ret <vscale x 8 x i1> %vc678}679 680define <vscale x 8 x i1> @icmp_sle_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {681; CHECK-LABEL: icmp_sle_vv_nxv8i8:682; CHECK:       # %bb.0:683; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma684; CHECK-NEXT:    vmsle.vv v0, v8, v9685; CHECK-NEXT:    ret686  %vc = icmp sle <vscale x 8 x i8> %va, %vb687  ret <vscale x 8 x i1> %vc688}689 690define <vscale x 8 x i1> @icmp_sle_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {691; CHECK-LABEL: icmp_sle_vx_nxv8i8:692; CHECK:       # %bb.0:693; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma694; CHECK-NEXT:    vmsle.vx v0, v8, a0695; CHECK-NEXT:    ret696  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0697  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer698  %vc = icmp sle <vscale x 8 x i8> %va, %splat699  ret <vscale x 8 x i1> %vc700}701 702define <vscale x 8 x i1> @icmp_sle_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {703; CHECK-LABEL: icmp_sle_xv_nxv8i8:704; CHECK:       # %bb.0:705; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma706; CHECK-NEXT:    vmv.v.x v9, a0707; CHECK-NEXT:    vmsle.vv v0, v9, v8708; CHECK-NEXT:    ret709  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0710  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer711  %vc = icmp sle <vscale x 8 x i8> %splat, %va712  ret <vscale x 8 x i1> %vc713}714 715define <vscale x 8 x i1> @icmp_sle_vi_nxv8i8_0(<vscale x 8 x i8> %va) {716; CHECK-LABEL: icmp_sle_vi_nxv8i8_0:717; CHECK:       # %bb.0:718; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma719; CHECK-NEXT:    vmsle.vi v0, v8, 5720; CHECK-NEXT:    ret721  %vc = icmp sle <vscale x 8 x i8> %va, splat (i8 5)722  ret <vscale x 8 x i1> %vc723}724 725define <vscale x 8 x i1> @icmp_eq_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {726; CHECK-LABEL: icmp_eq_vv_nxv8i16:727; CHECK:       # %bb.0:728; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma729; CHECK-NEXT:    vmseq.vv v0, v8, v10730; CHECK-NEXT:    ret731  %vc = icmp eq <vscale x 8 x i16> %va, %vb732  ret <vscale x 8 x i1> %vc733}734 735define <vscale x 8 x i1> @icmp_eq_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {736; CHECK-LABEL: icmp_eq_vx_nxv8i16:737; CHECK:       # %bb.0:738; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma739; CHECK-NEXT:    vmseq.vx v0, v8, a0740; CHECK-NEXT:    ret741  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0742  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer743  %vc = icmp eq <vscale x 8 x i16> %va, %splat744  ret <vscale x 8 x i1> %vc745}746 747define <vscale x 8 x i1> @icmp_eq_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {748; CHECK-LABEL: icmp_eq_xv_nxv8i16:749; CHECK:       # %bb.0:750; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma751; CHECK-NEXT:    vmseq.vx v0, v8, a0752; CHECK-NEXT:    ret753  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0754  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer755  %vc = icmp eq <vscale x 8 x i16> %splat, %va756  ret <vscale x 8 x i1> %vc757}758 759define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_0(<vscale x 8 x i16> %va) {760; CHECK-LABEL: icmp_eq_vi_nxv8i16_0:761; CHECK:       # %bb.0:762; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma763; CHECK-NEXT:    vmseq.vi v0, v8, 0764; CHECK-NEXT:    ret765  %vc = icmp eq <vscale x 8 x i16> %va, splat (i16 0)766  ret <vscale x 8 x i1> %vc767}768 769define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_1(<vscale x 8 x i16> %va) {770; CHECK-LABEL: icmp_eq_vi_nxv8i16_1:771; CHECK:       # %bb.0:772; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma773; CHECK-NEXT:    vmseq.vi v0, v8, 5774; CHECK-NEXT:    ret775  %vc = icmp eq <vscale x 8 x i16> %va, splat (i16 5)776  ret <vscale x 8 x i1> %vc777}778 779define <vscale x 8 x i1> @icmp_eq_iv_nxv8i16_1(<vscale x 8 x i16> %va) {780; CHECK-LABEL: icmp_eq_iv_nxv8i16_1:781; CHECK:       # %bb.0:782; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma783; CHECK-NEXT:    vmseq.vi v0, v8, 5784; CHECK-NEXT:    ret785  %vc = icmp eq <vscale x 8 x i16> splat (i16 5), %va786  ret <vscale x 8 x i1> %vc787}788 789define <vscale x 8 x i1> @icmp_ne_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {790; CHECK-LABEL: icmp_ne_vv_nxv8i16:791; CHECK:       # %bb.0:792; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma793; CHECK-NEXT:    vmsne.vv v0, v8, v10794; CHECK-NEXT:    ret795  %vc = icmp ne <vscale x 8 x i16> %va, %vb796  ret <vscale x 8 x i1> %vc797}798 799define <vscale x 8 x i1> @icmp_ne_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {800; CHECK-LABEL: icmp_ne_vx_nxv8i16:801; CHECK:       # %bb.0:802; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma803; CHECK-NEXT:    vmsne.vx v0, v8, a0804; CHECK-NEXT:    ret805  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0806  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer807  %vc = icmp ne <vscale x 8 x i16> %va, %splat808  ret <vscale x 8 x i1> %vc809}810 811define <vscale x 8 x i1> @icmp_ne_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {812; CHECK-LABEL: icmp_ne_xv_nxv8i16:813; CHECK:       # %bb.0:814; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma815; CHECK-NEXT:    vmsne.vx v0, v8, a0816; CHECK-NEXT:    ret817  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0818  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer819  %vc = icmp ne <vscale x 8 x i16> %splat, %va820  ret <vscale x 8 x i1> %vc821}822 823define <vscale x 8 x i1> @icmp_ne_vi_nxv8i16_0(<vscale x 8 x i16> %va) {824; CHECK-LABEL: icmp_ne_vi_nxv8i16_0:825; CHECK:       # %bb.0:826; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma827; CHECK-NEXT:    vmsne.vi v0, v8, 5828; CHECK-NEXT:    ret829  %vc = icmp ne <vscale x 8 x i16> %va, splat (i16 5)830  ret <vscale x 8 x i1> %vc831}832 833define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {834; CHECK-LABEL: icmp_ugt_vv_nxv8i16:835; CHECK:       # %bb.0:836; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma837; CHECK-NEXT:    vmsltu.vv v0, v10, v8838; CHECK-NEXT:    ret839  %vc = icmp ugt <vscale x 8 x i16> %va, %vb840  ret <vscale x 8 x i1> %vc841}842 843define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {844; CHECK-LABEL: icmp_ugt_vx_nxv8i16:845; CHECK:       # %bb.0:846; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma847; CHECK-NEXT:    vmsgtu.vx v0, v8, a0848; CHECK-NEXT:    ret849  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0850  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer851  %vc = icmp ugt <vscale x 8 x i16> %va, %splat852  ret <vscale x 8 x i1> %vc853}854 855define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {856; CHECK-LABEL: icmp_ugt_xv_nxv8i16:857; CHECK:       # %bb.0:858; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma859; CHECK-NEXT:    vmsltu.vx v0, v8, a0860; CHECK-NEXT:    ret861  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0862  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer863  %vc = icmp ugt <vscale x 8 x i16> %splat, %va864  ret <vscale x 8 x i1> %vc865}866 867define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {868; CHECK-LABEL: icmp_ugt_vi_nxv8i16_0:869; CHECK:       # %bb.0:870; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma871; CHECK-NEXT:    vmsgtu.vi v0, v8, 5872; CHECK-NEXT:    ret873  %vc = icmp ugt <vscale x 8 x i16> %va, splat (i16 5)874  ret <vscale x 8 x i1> %vc875}876 877define <vscale x 8 x i1> @icmp_uge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {878; CHECK-LABEL: icmp_uge_vv_nxv8i16:879; CHECK:       # %bb.0:880; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma881; CHECK-NEXT:    vmsleu.vv v0, v10, v8882; CHECK-NEXT:    ret883  %vc = icmp uge <vscale x 8 x i16> %va, %vb884  ret <vscale x 8 x i1> %vc885}886 887define <vscale x 8 x i1> @icmp_uge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {888; CHECK-LABEL: icmp_uge_vx_nxv8i16:889; CHECK:       # %bb.0:890; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma891; CHECK-NEXT:    vmv.v.x v10, a0892; CHECK-NEXT:    vmsleu.vv v0, v10, v8893; CHECK-NEXT:    ret894  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0895  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer896  %vc = icmp uge <vscale x 8 x i16> %va, %splat897  ret <vscale x 8 x i1> %vc898}899 900define <vscale x 8 x i1> @icmp_uge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {901; CHECK-LABEL: icmp_uge_xv_nxv8i16:902; CHECK:       # %bb.0:903; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma904; CHECK-NEXT:    vmsleu.vx v0, v8, a0905; CHECK-NEXT:    ret906  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0907  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer908  %vc = icmp uge <vscale x 8 x i16> %splat, %va909  ret <vscale x 8 x i1> %vc910}911 912define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {913; CHECK-LABEL: icmp_uge_vi_nxv8i16_0:914; CHECK:       # %bb.0:915; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma916; CHECK-NEXT:    vmv.v.i v10, -16917; CHECK-NEXT:    vmsleu.vv v0, v10, v8918; CHECK-NEXT:    ret919  %vc = icmp uge <vscale x 8 x i16> %va, splat (i16 -16)920  ret <vscale x 8 x i1> %vc921}922 923define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {924; CHECK-LABEL: icmp_uge_vi_nxv8i16_1:925; CHECK:       # %bb.0:926; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma927; CHECK-NEXT:    vmsgtu.vi v0, v8, 14928; CHECK-NEXT:    ret929  %vc = icmp uge <vscale x 8 x i16> %va, splat (i16 15)930  ret <vscale x 8 x i1> %vc931}932 933define <vscale x 8 x i1> @icmp_uge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {934; CHECK-LABEL: icmp_uge_iv_nxv8i16_1:935; CHECK:       # %bb.0:936; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma937; CHECK-NEXT:    vmsleu.vi v0, v8, 15938; CHECK-NEXT:    ret939  %vc = icmp uge <vscale x 8 x i16> splat (i16 15), %va940  ret <vscale x 8 x i1> %vc941}942 943define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {944; CHECK-LABEL: icmp_uge_vi_nxv8i16_2:945; CHECK:       # %bb.0:946; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma947; CHECK-NEXT:    vmset.m v0948; CHECK-NEXT:    ret949  %vc = icmp uge <vscale x 8 x i16> %va, splat (i16 0)950  ret <vscale x 8 x i1> %vc951}952 953define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {954; CHECK-LABEL: icmp_uge_vi_nxv8i16_3:955; CHECK:       # %bb.0:956; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma957; CHECK-NEXT:    vmsgtu.vi v0, v8, 0958; CHECK-NEXT:    ret959  %vc = icmp uge <vscale x 8 x i16> %va, splat (i16 1)960  ret <vscale x 8 x i1> %vc961}962 963define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_4(<vscale x 8 x i16> %va) {964; CHECK-LABEL: icmp_uge_vi_nxv8i16_4:965; CHECK:       # %bb.0:966; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma967; CHECK-NEXT:    vmsgtu.vi v0, v8, -16968; CHECK-NEXT:    ret969  %vc = icmp uge <vscale x 8 x i16> %va, splat (i16 -15)970  ret <vscale x 8 x i1> %vc971}972 973define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) {974; CHECK-LABEL: icmp_uge_vi_nxv8i16_5:975; CHECK:       # %bb.0:976; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma977; CHECK-NEXT:    vmsgtu.vi v0, v8, 15978; CHECK-NEXT:    ret979  %vc = icmp uge <vscale x 8 x i16> %va, splat (i16 16)980  ret <vscale x 8 x i1> %vc981}982 983define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {984; CHECK-LABEL: icmp_ult_vv_nxv8i16:985; CHECK:       # %bb.0:986; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma987; CHECK-NEXT:    vmsltu.vv v0, v8, v10988; CHECK-NEXT:    ret989  %vc = icmp ult <vscale x 8 x i16> %va, %vb990  ret <vscale x 8 x i1> %vc991}992 993define <vscale x 8 x i1> @icmp_ult_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {994; CHECK-LABEL: icmp_ult_vx_nxv8i16:995; CHECK:       # %bb.0:996; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma997; CHECK-NEXT:    vmsltu.vx v0, v8, a0998; CHECK-NEXT:    ret999  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01000  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1001  %vc = icmp ult <vscale x 8 x i16> %va, %splat1002  ret <vscale x 8 x i1> %vc1003}1004 1005define <vscale x 8 x i1> @icmp_ult_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1006; CHECK-LABEL: icmp_ult_xv_nxv8i16:1007; CHECK:       # %bb.0:1008; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1009; CHECK-NEXT:    vmsgtu.vx v0, v8, a01010; CHECK-NEXT:    ret1011  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01012  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1013  %vc = icmp ult <vscale x 8 x i16> %splat, %va1014  ret <vscale x 8 x i1> %vc1015}1016 1017define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_0(<vscale x 8 x i16> %va) {1018; CHECK-LABEL: icmp_ult_vi_nxv8i16_0:1019; CHECK:       # %bb.0:1020; CHECK-NEXT:    li a0, -161021; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1022; CHECK-NEXT:    vmsltu.vx v0, v8, a01023; CHECK-NEXT:    ret1024  %vc = icmp ult <vscale x 8 x i16> %va, splat (i16 -16)1025  ret <vscale x 8 x i1> %vc1026}1027 1028define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_1(<vscale x 8 x i16> %va) {1029; CHECK-LABEL: icmp_ult_vi_nxv8i16_1:1030; CHECK:       # %bb.0:1031; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1032; CHECK-NEXT:    vmsleu.vi v0, v8, -161033; CHECK-NEXT:    ret1034  %vc = icmp ult <vscale x 8 x i16> %va, splat (i16 -15)1035  ret <vscale x 8 x i1> %vc1036}1037 1038define <vscale x 8 x i1> @icmp_ult_iv_nxv8i16_1(<vscale x 8 x i16> %va) {1039; CHECK-LABEL: icmp_ult_iv_nxv8i16_1:1040; CHECK:       # %bb.0:1041; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1042; CHECK-NEXT:    vmsgtu.vi v0, v8, -151043; CHECK-NEXT:    ret1044  %vc = icmp ult <vscale x 8 x i16> splat (i16 -15), %va1045  ret <vscale x 8 x i1> %vc1046}1047 1048define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_2(<vscale x 8 x i16> %va) {1049; CHECK-LABEL: icmp_ult_vi_nxv8i16_2:1050; CHECK:       # %bb.0:1051; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1052; CHECK-NEXT:    vmclr.m v01053; CHECK-NEXT:    ret1054  %vc = icmp ult <vscale x 8 x i16> %va, splat (i16 0)1055  ret <vscale x 8 x i1> %vc1056}1057 1058define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_3(<vscale x 8 x i16> %va) {1059; CHECK-LABEL: icmp_ult_vi_nxv8i16_3:1060; CHECK:       # %bb.0:1061; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1062; CHECK-NEXT:    vmseq.vi v0, v8, 01063; CHECK-NEXT:    ret1064  %vc = icmp ult <vscale x 8 x i16> %va, splat (i16 1)1065  ret <vscale x 8 x i1> %vc1066}1067 1068define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_4(<vscale x 8 x i16> %va) {1069; CHECK-LABEL: icmp_ult_vi_nxv8i16_4:1070; CHECK:       # %bb.0:1071; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1072; CHECK-NEXT:    vmsleu.vi v0, v8, 151073; CHECK-NEXT:    ret1074  %vc = icmp ult <vscale x 8 x i16> %va, splat (i16 16)1075  ret <vscale x 8 x i1> %vc1076}1077 1078define <vscale x 8 x i1> @icmp_ule_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {1079; CHECK-LABEL: icmp_ule_vv_nxv8i16:1080; CHECK:       # %bb.0:1081; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1082; CHECK-NEXT:    vmsleu.vv v0, v8, v101083; CHECK-NEXT:    ret1084  %vc = icmp ule <vscale x 8 x i16> %va, %vb1085  ret <vscale x 8 x i1> %vc1086}1087 1088define <vscale x 8 x i1> @icmp_ule_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1089; CHECK-LABEL: icmp_ule_vx_nxv8i16:1090; CHECK:       # %bb.0:1091; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1092; CHECK-NEXT:    vmsleu.vx v0, v8, a01093; CHECK-NEXT:    ret1094  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01095  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1096  %vc = icmp ule <vscale x 8 x i16> %va, %splat1097  ret <vscale x 8 x i1> %vc1098}1099 1100define <vscale x 8 x i1> @icmp_ule_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1101; CHECK-LABEL: icmp_ule_xv_nxv8i16:1102; CHECK:       # %bb.0:1103; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1104; CHECK-NEXT:    vmv.v.x v10, a01105; CHECK-NEXT:    vmsleu.vv v0, v10, v81106; CHECK-NEXT:    ret1107  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01108  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1109  %vc = icmp ule <vscale x 8 x i16> %splat, %va1110  ret <vscale x 8 x i1> %vc1111}1112 1113define <vscale x 8 x i1> @icmp_ule_vi_nxv8i16_0(<vscale x 8 x i16> %va) {1114; CHECK-LABEL: icmp_ule_vi_nxv8i16_0:1115; CHECK:       # %bb.0:1116; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1117; CHECK-NEXT:    vmsleu.vi v0, v8, 51118; CHECK-NEXT:    ret1119  %vc = icmp ule <vscale x 8 x i16> %va, splat (i16 5)1120  ret <vscale x 8 x i1> %vc1121}1122 1123define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {1124; CHECK-LABEL: icmp_sgt_vv_nxv8i16:1125; CHECK:       # %bb.0:1126; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1127; CHECK-NEXT:    vmslt.vv v0, v10, v81128; CHECK-NEXT:    ret1129  %vc = icmp sgt <vscale x 8 x i16> %va, %vb1130  ret <vscale x 8 x i1> %vc1131}1132 1133define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1134; CHECK-LABEL: icmp_sgt_vx_nxv8i16:1135; CHECK:       # %bb.0:1136; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1137; CHECK-NEXT:    vmsgt.vx v0, v8, a01138; CHECK-NEXT:    ret1139  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01140  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1141  %vc = icmp sgt <vscale x 8 x i16> %va, %splat1142  ret <vscale x 8 x i1> %vc1143}1144 1145define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1146; CHECK-LABEL: icmp_sgt_xv_nxv8i16:1147; CHECK:       # %bb.0:1148; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1149; CHECK-NEXT:    vmslt.vx v0, v8, a01150; CHECK-NEXT:    ret1151  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01152  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1153  %vc = icmp sgt <vscale x 8 x i16> %splat, %va1154  ret <vscale x 8 x i1> %vc1155}1156 1157define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {1158; CHECK-LABEL: icmp_sgt_vi_nxv8i16_0:1159; CHECK:       # %bb.0:1160; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1161; CHECK-NEXT:    vmsgt.vi v0, v8, 51162; CHECK-NEXT:    ret1163  %vc = icmp sgt <vscale x 8 x i16> %va, splat (i16 5)1164  ret <vscale x 8 x i1> %vc1165}1166 1167define <vscale x 8 x i1> @icmp_sge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {1168; CHECK-LABEL: icmp_sge_vv_nxv8i16:1169; CHECK:       # %bb.0:1170; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1171; CHECK-NEXT:    vmsle.vv v0, v10, v81172; CHECK-NEXT:    ret1173  %vc = icmp sge <vscale x 8 x i16> %va, %vb1174  ret <vscale x 8 x i1> %vc1175}1176 1177define <vscale x 8 x i1> @icmp_sge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1178; CHECK-LABEL: icmp_sge_vx_nxv8i16:1179; CHECK:       # %bb.0:1180; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1181; CHECK-NEXT:    vmv.v.x v10, a01182; CHECK-NEXT:    vmsle.vv v0, v10, v81183; CHECK-NEXT:    ret1184  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01185  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1186  %vc = icmp sge <vscale x 8 x i16> %va, %splat1187  ret <vscale x 8 x i1> %vc1188}1189 1190define <vscale x 8 x i1> @icmp_sge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1191; CHECK-LABEL: icmp_sge_xv_nxv8i16:1192; CHECK:       # %bb.0:1193; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1194; CHECK-NEXT:    vmsle.vx v0, v8, a01195; CHECK-NEXT:    ret1196  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01197  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1198  %vc = icmp sge <vscale x 8 x i16> %splat, %va1199  ret <vscale x 8 x i1> %vc1200}1201 1202define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {1203; CHECK-LABEL: icmp_sge_vi_nxv8i16_0:1204; CHECK:       # %bb.0:1205; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1206; CHECK-NEXT:    vmv.v.i v10, -161207; CHECK-NEXT:    vmsle.vv v0, v10, v81208; CHECK-NEXT:    ret1209  %vc = icmp sge <vscale x 8 x i16> %va, splat (i16 -16)1210  ret <vscale x 8 x i1> %vc1211}1212 1213define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {1214; CHECK-LABEL: icmp_sge_vi_nxv8i16_1:1215; CHECK:       # %bb.0:1216; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1217; CHECK-NEXT:    vmsgt.vi v0, v8, -161218; CHECK-NEXT:    ret1219  %vc = icmp sge <vscale x 8 x i16> %va, splat (i16 -15)1220  ret <vscale x 8 x i1> %vc1221}1222 1223define <vscale x 8 x i1> @icmp_sge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {1224; CHECK-LABEL: icmp_sge_iv_nxv8i16_1:1225; CHECK:       # %bb.0:1226; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1227; CHECK-NEXT:    vmsle.vi v0, v8, -151228; CHECK-NEXT:    ret1229  %vc = icmp sge <vscale x 8 x i16> splat (i16 -15), %va1230  ret <vscale x 8 x i1> %vc1231}1232 1233define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {1234; CHECK-LABEL: icmp_sge_vi_nxv8i16_2:1235; CHECK:       # %bb.0:1236; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1237; CHECK-NEXT:    vmsgt.vi v0, v8, -11238; CHECK-NEXT:    ret1239  %vc = icmp sge <vscale x 8 x i16> %va, splat (i16 0)1240  ret <vscale x 8 x i1> %vc1241}1242 1243define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {1244; CHECK-LABEL: icmp_sge_vi_nxv8i16_3:1245; CHECK:       # %bb.0:1246; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1247; CHECK-NEXT:    vmsgt.vi v0, v8, 151248; CHECK-NEXT:    ret1249  %vc = icmp sge <vscale x 8 x i16> %va, splat (i16 16)1250  ret <vscale x 8 x i1> %vc1251}1252 1253define <vscale x 8 x i1> @icmp_slt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {1254; CHECK-LABEL: icmp_slt_vv_nxv8i16:1255; CHECK:       # %bb.0:1256; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1257; CHECK-NEXT:    vmslt.vv v0, v8, v101258; CHECK-NEXT:    ret1259  %vc = icmp slt <vscale x 8 x i16> %va, %vb1260  ret <vscale x 8 x i1> %vc1261}1262 1263define <vscale x 8 x i1> @icmp_slt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1264; CHECK-LABEL: icmp_slt_vx_nxv8i16:1265; CHECK:       # %bb.0:1266; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1267; CHECK-NEXT:    vmslt.vx v0, v8, a01268; CHECK-NEXT:    ret1269  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01270  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1271  %vc = icmp slt <vscale x 8 x i16> %va, %splat1272  ret <vscale x 8 x i1> %vc1273}1274 1275define <vscale x 8 x i1> @icmp_slt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1276; CHECK-LABEL: icmp_slt_xv_nxv8i16:1277; CHECK:       # %bb.0:1278; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1279; CHECK-NEXT:    vmsgt.vx v0, v8, a01280; CHECK-NEXT:    ret1281  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01282  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1283  %vc = icmp slt <vscale x 8 x i16> %splat, %va1284  ret <vscale x 8 x i1> %vc1285}1286 1287define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {1288; CHECK-LABEL: icmp_slt_vi_nxv8i16_0:1289; CHECK:       # %bb.0:1290; CHECK-NEXT:    li a0, -161291; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1292; CHECK-NEXT:    vmslt.vx v0, v8, a01293; CHECK-NEXT:    ret1294  %vc = icmp slt <vscale x 8 x i16> %va, splat (i16 -16)1295  ret <vscale x 8 x i1> %vc1296}1297 1298define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_1(<vscale x 8 x i16> %va) {1299; CHECK-LABEL: icmp_slt_vi_nxv8i16_1:1300; CHECK:       # %bb.0:1301; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1302; CHECK-NEXT:    vmsle.vi v0, v8, -161303; CHECK-NEXT:    ret1304  %vc = icmp slt <vscale x 8 x i16> %va, splat (i16 -15)1305  ret <vscale x 8 x i1> %vc1306}1307 1308define <vscale x 8 x i1> @icmp_slt_iv_nxv8i16_1(<vscale x 8 x i16> %va) {1309; CHECK-LABEL: icmp_slt_iv_nxv8i16_1:1310; CHECK:       # %bb.0:1311; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1312; CHECK-NEXT:    vmsgt.vi v0, v8, -151313; CHECK-NEXT:    ret1314  %vc = icmp slt <vscale x 8 x i16> splat (i16 -15), %va1315  ret <vscale x 8 x i1> %vc1316}1317 1318define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) {1319; CHECK-LABEL: icmp_slt_vi_nxv8i16_2:1320; CHECK:       # %bb.0:1321; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1322; CHECK-NEXT:    vmsle.vi v0, v8, -11323; CHECK-NEXT:    ret1324  %vc = icmp slt <vscale x 8 x i16> %va, splat (i16 0)1325  ret <vscale x 8 x i1> %vc1326}1327 1328define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_3(<vscale x 8 x i16> %va) {1329; CHECK-LABEL: icmp_slt_vi_nxv8i16_3:1330; CHECK:       # %bb.0:1331; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1332; CHECK-NEXT:    vmsle.vi v0, v8, 151333; CHECK-NEXT:    ret1334  %vc = icmp slt <vscale x 8 x i16> %va, splat (i16 16)1335  ret <vscale x 8 x i1> %vc1336}1337 1338define <vscale x 8 x i1> @icmp_sle_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {1339; CHECK-LABEL: icmp_sle_vv_nxv8i16:1340; CHECK:       # %bb.0:1341; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1342; CHECK-NEXT:    vmsle.vv v0, v8, v101343; CHECK-NEXT:    ret1344  %vc = icmp sle <vscale x 8 x i16> %va, %vb1345  ret <vscale x 8 x i1> %vc1346}1347 1348define <vscale x 8 x i1> @icmp_sle_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1349; CHECK-LABEL: icmp_sle_vx_nxv8i16:1350; CHECK:       # %bb.0:1351; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1352; CHECK-NEXT:    vmsle.vx v0, v8, a01353; CHECK-NEXT:    ret1354  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01355  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1356  %vc = icmp sle <vscale x 8 x i16> %va, %splat1357  ret <vscale x 8 x i1> %vc1358}1359 1360define <vscale x 8 x i1> @icmp_sle_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {1361; CHECK-LABEL: icmp_sle_xv_nxv8i16:1362; CHECK:       # %bb.0:1363; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1364; CHECK-NEXT:    vmv.v.x v10, a01365; CHECK-NEXT:    vmsle.vv v0, v10, v81366; CHECK-NEXT:    ret1367  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 01368  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1369  %vc = icmp sle <vscale x 8 x i16> %splat, %va1370  ret <vscale x 8 x i1> %vc1371}1372 1373define <vscale x 8 x i1> @icmp_sle_vi_nxv8i16_0(<vscale x 8 x i16> %va) {1374; CHECK-LABEL: icmp_sle_vi_nxv8i16_0:1375; CHECK:       # %bb.0:1376; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1377; CHECK-NEXT:    vmsle.vi v0, v8, 51378; CHECK-NEXT:    ret1379  %vc = icmp sle <vscale x 8 x i16> %va, splat (i16 5)1380  ret <vscale x 8 x i1> %vc1381}1382 1383define <vscale x 8 x i1> @icmp_eq_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {1384; CHECK-LABEL: icmp_eq_vv_nxv8i32:1385; CHECK:       # %bb.0:1386; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1387; CHECK-NEXT:    vmseq.vv v0, v8, v121388; CHECK-NEXT:    ret1389  %vc = icmp eq <vscale x 8 x i32> %va, %vb1390  ret <vscale x 8 x i1> %vc1391}1392 1393define <vscale x 8 x i1> @icmp_eq_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1394; CHECK-LABEL: icmp_eq_vx_nxv8i32:1395; CHECK:       # %bb.0:1396; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1397; CHECK-NEXT:    vmseq.vx v0, v8, a01398; CHECK-NEXT:    ret1399  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01400  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1401  %vc = icmp eq <vscale x 8 x i32> %va, %splat1402  ret <vscale x 8 x i1> %vc1403}1404 1405define <vscale x 8 x i1> @icmp_eq_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1406; CHECK-LABEL: icmp_eq_xv_nxv8i32:1407; CHECK:       # %bb.0:1408; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1409; CHECK-NEXT:    vmseq.vx v0, v8, a01410; CHECK-NEXT:    ret1411  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01412  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1413  %vc = icmp eq <vscale x 8 x i32> %splat, %va1414  ret <vscale x 8 x i1> %vc1415}1416 1417define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_0(<vscale x 8 x i32> %va) {1418; CHECK-LABEL: icmp_eq_vi_nxv8i32_0:1419; CHECK:       # %bb.0:1420; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1421; CHECK-NEXT:    vmseq.vi v0, v8, 01422; CHECK-NEXT:    ret1423  %vc = icmp eq <vscale x 8 x i32> %va, splat (i32 0)1424  ret <vscale x 8 x i1> %vc1425}1426 1427define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_1(<vscale x 8 x i32> %va) {1428; CHECK-LABEL: icmp_eq_vi_nxv8i32_1:1429; CHECK:       # %bb.0:1430; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1431; CHECK-NEXT:    vmseq.vi v0, v8, 51432; CHECK-NEXT:    ret1433  %vc = icmp eq <vscale x 8 x i32> %va, splat (i32 5)1434  ret <vscale x 8 x i1> %vc1435}1436 1437define <vscale x 8 x i1> @icmp_eq_iv_nxv8i32_1(<vscale x 8 x i32> %va) {1438; CHECK-LABEL: icmp_eq_iv_nxv8i32_1:1439; CHECK:       # %bb.0:1440; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1441; CHECK-NEXT:    vmseq.vi v0, v8, 51442; CHECK-NEXT:    ret1443  %vc = icmp eq <vscale x 8 x i32> splat (i32 5), %va1444  ret <vscale x 8 x i1> %vc1445}1446 1447define <vscale x 8 x i1> @icmp_ne_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {1448; CHECK-LABEL: icmp_ne_vv_nxv8i32:1449; CHECK:       # %bb.0:1450; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1451; CHECK-NEXT:    vmsne.vv v0, v8, v121452; CHECK-NEXT:    ret1453  %vc = icmp ne <vscale x 8 x i32> %va, %vb1454  ret <vscale x 8 x i1> %vc1455}1456 1457define <vscale x 8 x i1> @icmp_ne_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1458; CHECK-LABEL: icmp_ne_vx_nxv8i32:1459; CHECK:       # %bb.0:1460; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1461; CHECK-NEXT:    vmsne.vx v0, v8, a01462; CHECK-NEXT:    ret1463  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01464  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1465  %vc = icmp ne <vscale x 8 x i32> %va, %splat1466  ret <vscale x 8 x i1> %vc1467}1468 1469define <vscale x 8 x i1> @icmp_ne_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1470; CHECK-LABEL: icmp_ne_xv_nxv8i32:1471; CHECK:       # %bb.0:1472; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1473; CHECK-NEXT:    vmsne.vx v0, v8, a01474; CHECK-NEXT:    ret1475  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01476  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1477  %vc = icmp ne <vscale x 8 x i32> %splat, %va1478  ret <vscale x 8 x i1> %vc1479}1480 1481define <vscale x 8 x i1> @icmp_ne_vi_nxv8i32_0(<vscale x 8 x i32> %va) {1482; CHECK-LABEL: icmp_ne_vi_nxv8i32_0:1483; CHECK:       # %bb.0:1484; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1485; CHECK-NEXT:    vmsne.vi v0, v8, 51486; CHECK-NEXT:    ret1487  %vc = icmp ne <vscale x 8 x i32> %va, splat (i32 5)1488  ret <vscale x 8 x i1> %vc1489}1490 1491define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {1492; CHECK-LABEL: icmp_ugt_vv_nxv8i32:1493; CHECK:       # %bb.0:1494; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1495; CHECK-NEXT:    vmsltu.vv v0, v12, v81496; CHECK-NEXT:    ret1497  %vc = icmp ugt <vscale x 8 x i32> %va, %vb1498  ret <vscale x 8 x i1> %vc1499}1500 1501define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1502; CHECK-LABEL: icmp_ugt_vx_nxv8i32:1503; CHECK:       # %bb.0:1504; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1505; CHECK-NEXT:    vmsgtu.vx v0, v8, a01506; CHECK-NEXT:    ret1507  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01508  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1509  %vc = icmp ugt <vscale x 8 x i32> %va, %splat1510  ret <vscale x 8 x i1> %vc1511}1512 1513define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1514; CHECK-LABEL: icmp_ugt_xv_nxv8i32:1515; CHECK:       # %bb.0:1516; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1517; CHECK-NEXT:    vmsltu.vx v0, v8, a01518; CHECK-NEXT:    ret1519  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01520  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1521  %vc = icmp ugt <vscale x 8 x i32> %splat, %va1522  ret <vscale x 8 x i1> %vc1523}1524 1525define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {1526; CHECK-LABEL: icmp_ugt_vi_nxv8i32_0:1527; CHECK:       # %bb.0:1528; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1529; CHECK-NEXT:    vmsgtu.vi v0, v8, 51530; CHECK-NEXT:    ret1531  %vc = icmp ugt <vscale x 8 x i32> %va, splat (i32 5)1532  ret <vscale x 8 x i1> %vc1533}1534 1535define <vscale x 8 x i1> @icmp_uge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {1536; CHECK-LABEL: icmp_uge_vv_nxv8i32:1537; CHECK:       # %bb.0:1538; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1539; CHECK-NEXT:    vmsleu.vv v0, v12, v81540; CHECK-NEXT:    ret1541  %vc = icmp uge <vscale x 8 x i32> %va, %vb1542  ret <vscale x 8 x i1> %vc1543}1544 1545define <vscale x 8 x i1> @icmp_uge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1546; CHECK-LABEL: icmp_uge_vx_nxv8i32:1547; CHECK:       # %bb.0:1548; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1549; CHECK-NEXT:    vmv.v.x v12, a01550; CHECK-NEXT:    vmsleu.vv v0, v12, v81551; CHECK-NEXT:    ret1552  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01553  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1554  %vc = icmp uge <vscale x 8 x i32> %va, %splat1555  ret <vscale x 8 x i1> %vc1556}1557 1558define <vscale x 8 x i1> @icmp_uge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1559; CHECK-LABEL: icmp_uge_xv_nxv8i32:1560; CHECK:       # %bb.0:1561; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1562; CHECK-NEXT:    vmsleu.vx v0, v8, a01563; CHECK-NEXT:    ret1564  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01565  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1566  %vc = icmp uge <vscale x 8 x i32> %splat, %va1567  ret <vscale x 8 x i1> %vc1568}1569 1570define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {1571; CHECK-LABEL: icmp_uge_vi_nxv8i32_0:1572; CHECK:       # %bb.0:1573; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1574; CHECK-NEXT:    vmv.v.i v12, -161575; CHECK-NEXT:    vmsleu.vv v0, v12, v81576; CHECK-NEXT:    ret1577  %vc = icmp uge <vscale x 8 x i32> %va, splat (i32 -16)1578  ret <vscale x 8 x i1> %vc1579}1580 1581define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {1582; CHECK-LABEL: icmp_uge_vi_nxv8i32_1:1583; CHECK:       # %bb.0:1584; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1585; CHECK-NEXT:    vmsgtu.vi v0, v8, 141586; CHECK-NEXT:    ret1587  %vc = icmp uge <vscale x 8 x i32> %va, splat (i32 15)1588  ret <vscale x 8 x i1> %vc1589}1590 1591define <vscale x 8 x i1> @icmp_uge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {1592; CHECK-LABEL: icmp_uge_iv_nxv8i32_1:1593; CHECK:       # %bb.0:1594; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1595; CHECK-NEXT:    vmsleu.vi v0, v8, 151596; CHECK-NEXT:    ret1597  %vc = icmp uge <vscale x 8 x i32> splat (i32 15), %va1598  ret <vscale x 8 x i1> %vc1599}1600 1601define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {1602; CHECK-LABEL: icmp_uge_vi_nxv8i32_2:1603; CHECK:       # %bb.0:1604; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1605; CHECK-NEXT:    vmset.m v01606; CHECK-NEXT:    ret1607  %vc = icmp uge <vscale x 8 x i32> %va, splat (i32 0)1608  ret <vscale x 8 x i1> %vc1609}1610 1611define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {1612; CHECK-LABEL: icmp_uge_vi_nxv8i32_3:1613; CHECK:       # %bb.0:1614; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1615; CHECK-NEXT:    vmsgtu.vi v0, v8, 01616; CHECK-NEXT:    ret1617  %vc = icmp uge <vscale x 8 x i32> %va, splat (i32 1)1618  ret <vscale x 8 x i1> %vc1619}1620 1621define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_4(<vscale x 8 x i32> %va) {1622; CHECK-LABEL: icmp_uge_vi_nxv8i32_4:1623; CHECK:       # %bb.0:1624; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1625; CHECK-NEXT:    vmsgtu.vi v0, v8, -161626; CHECK-NEXT:    ret1627  %vc = icmp uge <vscale x 8 x i32> %va, splat (i32 -15)1628  ret <vscale x 8 x i1> %vc1629}1630 1631define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_5(<vscale x 8 x i32> %va) {1632; CHECK-LABEL: icmp_uge_vi_nxv8i32_5:1633; CHECK:       # %bb.0:1634; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1635; CHECK-NEXT:    vmsgtu.vi v0, v8, 151636; CHECK-NEXT:    ret1637  %vc = icmp uge <vscale x 8 x i32> %va, splat (i32 16)1638  ret <vscale x 8 x i1> %vc1639}1640 1641define <vscale x 8 x i1> @icmp_ult_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {1642; CHECK-LABEL: icmp_ult_vv_nxv8i32:1643; CHECK:       # %bb.0:1644; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1645; CHECK-NEXT:    vmsltu.vv v0, v8, v121646; CHECK-NEXT:    ret1647  %vc = icmp ult <vscale x 8 x i32> %va, %vb1648  ret <vscale x 8 x i1> %vc1649}1650 1651define <vscale x 8 x i1> @icmp_ult_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1652; CHECK-LABEL: icmp_ult_vx_nxv8i32:1653; CHECK:       # %bb.0:1654; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1655; CHECK-NEXT:    vmsltu.vx v0, v8, a01656; CHECK-NEXT:    ret1657  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01658  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1659  %vc = icmp ult <vscale x 8 x i32> %va, %splat1660  ret <vscale x 8 x i1> %vc1661}1662 1663define <vscale x 8 x i1> @icmp_ult_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1664; CHECK-LABEL: icmp_ult_xv_nxv8i32:1665; CHECK:       # %bb.0:1666; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1667; CHECK-NEXT:    vmsgtu.vx v0, v8, a01668; CHECK-NEXT:    ret1669  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01670  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1671  %vc = icmp ult <vscale x 8 x i32> %splat, %va1672  ret <vscale x 8 x i1> %vc1673}1674 1675define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_0(<vscale x 8 x i32> %va) {1676; CHECK-LABEL: icmp_ult_vi_nxv8i32_0:1677; CHECK:       # %bb.0:1678; CHECK-NEXT:    li a0, -161679; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1680; CHECK-NEXT:    vmsltu.vx v0, v8, a01681; CHECK-NEXT:    ret1682  %vc = icmp ult <vscale x 8 x i32> %va, splat (i32 -16)1683  ret <vscale x 8 x i1> %vc1684}1685 1686define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_1(<vscale x 8 x i32> %va) {1687; CHECK-LABEL: icmp_ult_vi_nxv8i32_1:1688; CHECK:       # %bb.0:1689; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1690; CHECK-NEXT:    vmsleu.vi v0, v8, -161691; CHECK-NEXT:    ret1692  %vc = icmp ult <vscale x 8 x i32> %va, splat (i32 -15)1693  ret <vscale x 8 x i1> %vc1694}1695 1696define <vscale x 8 x i1> @icmp_ult_iv_nxv8i32_1(<vscale x 8 x i32> %va) {1697; CHECK-LABEL: icmp_ult_iv_nxv8i32_1:1698; CHECK:       # %bb.0:1699; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1700; CHECK-NEXT:    vmsgtu.vi v0, v8, -151701; CHECK-NEXT:    ret1702  %vc = icmp ult <vscale x 8 x i32> splat (i32 -15), %va1703  ret <vscale x 8 x i1> %vc1704}1705 1706define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_2(<vscale x 8 x i32> %va) {1707; CHECK-LABEL: icmp_ult_vi_nxv8i32_2:1708; CHECK:       # %bb.0:1709; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1710; CHECK-NEXT:    vmclr.m v01711; CHECK-NEXT:    ret1712  %vc = icmp ult <vscale x 8 x i32> %va, splat (i32 0)1713  ret <vscale x 8 x i1> %vc1714}1715 1716define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_3(<vscale x 8 x i32> %va) {1717; CHECK-LABEL: icmp_ult_vi_nxv8i32_3:1718; CHECK:       # %bb.0:1719; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1720; CHECK-NEXT:    vmseq.vi v0, v8, 01721; CHECK-NEXT:    ret1722  %vc = icmp ult <vscale x 8 x i32> %va, splat (i32 1)1723  ret <vscale x 8 x i1> %vc1724}1725 1726define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_4(<vscale x 8 x i32> %va) {1727; CHECK-LABEL: icmp_ult_vi_nxv8i32_4:1728; CHECK:       # %bb.0:1729; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1730; CHECK-NEXT:    vmsleu.vi v0, v8, 151731; CHECK-NEXT:    ret1732  %vc = icmp ult <vscale x 8 x i32> %va, splat (i32 16)1733  ret <vscale x 8 x i1> %vc1734}1735 1736define <vscale x 8 x i1> @icmp_ule_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {1737; CHECK-LABEL: icmp_ule_vv_nxv8i32:1738; CHECK:       # %bb.0:1739; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1740; CHECK-NEXT:    vmsleu.vv v0, v8, v121741; CHECK-NEXT:    ret1742  %vc = icmp ule <vscale x 8 x i32> %va, %vb1743  ret <vscale x 8 x i1> %vc1744}1745 1746define <vscale x 8 x i1> @icmp_ule_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1747; CHECK-LABEL: icmp_ule_vx_nxv8i32:1748; CHECK:       # %bb.0:1749; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1750; CHECK-NEXT:    vmsleu.vx v0, v8, a01751; CHECK-NEXT:    ret1752  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01753  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1754  %vc = icmp ule <vscale x 8 x i32> %va, %splat1755  ret <vscale x 8 x i1> %vc1756}1757 1758define <vscale x 8 x i1> @icmp_ule_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1759; CHECK-LABEL: icmp_ule_xv_nxv8i32:1760; CHECK:       # %bb.0:1761; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1762; CHECK-NEXT:    vmv.v.x v12, a01763; CHECK-NEXT:    vmsleu.vv v0, v12, v81764; CHECK-NEXT:    ret1765  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01766  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1767  %vc = icmp ule <vscale x 8 x i32> %splat, %va1768  ret <vscale x 8 x i1> %vc1769}1770 1771define <vscale x 8 x i1> @icmp_ule_vi_nxv8i32_0(<vscale x 8 x i32> %va) {1772; CHECK-LABEL: icmp_ule_vi_nxv8i32_0:1773; CHECK:       # %bb.0:1774; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1775; CHECK-NEXT:    vmsleu.vi v0, v8, 51776; CHECK-NEXT:    ret1777  %vc = icmp ule <vscale x 8 x i32> %va, splat (i32 5)1778  ret <vscale x 8 x i1> %vc1779}1780 1781define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {1782; CHECK-LABEL: icmp_sgt_vv_nxv8i32:1783; CHECK:       # %bb.0:1784; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1785; CHECK-NEXT:    vmslt.vv v0, v12, v81786; CHECK-NEXT:    ret1787  %vc = icmp sgt <vscale x 8 x i32> %va, %vb1788  ret <vscale x 8 x i1> %vc1789}1790 1791define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1792; CHECK-LABEL: icmp_sgt_vx_nxv8i32:1793; CHECK:       # %bb.0:1794; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1795; CHECK-NEXT:    vmsgt.vx v0, v8, a01796; CHECK-NEXT:    ret1797  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01798  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1799  %vc = icmp sgt <vscale x 8 x i32> %va, %splat1800  ret <vscale x 8 x i1> %vc1801}1802 1803define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1804; CHECK-LABEL: icmp_sgt_xv_nxv8i32:1805; CHECK:       # %bb.0:1806; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1807; CHECK-NEXT:    vmslt.vx v0, v8, a01808; CHECK-NEXT:    ret1809  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01810  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1811  %vc = icmp sgt <vscale x 8 x i32> %splat, %va1812  ret <vscale x 8 x i1> %vc1813}1814 1815define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {1816; CHECK-LABEL: icmp_sgt_vi_nxv8i32_0:1817; CHECK:       # %bb.0:1818; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1819; CHECK-NEXT:    vmsgt.vi v0, v8, 51820; CHECK-NEXT:    ret1821  %vc = icmp sgt <vscale x 8 x i32> %va, splat (i32 5)1822  ret <vscale x 8 x i1> %vc1823}1824 1825define <vscale x 8 x i1> @icmp_sge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {1826; CHECK-LABEL: icmp_sge_vv_nxv8i32:1827; CHECK:       # %bb.0:1828; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1829; CHECK-NEXT:    vmsle.vv v0, v12, v81830; CHECK-NEXT:    ret1831  %vc = icmp sge <vscale x 8 x i32> %va, %vb1832  ret <vscale x 8 x i1> %vc1833}1834 1835define <vscale x 8 x i1> @icmp_sge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1836; CHECK-LABEL: icmp_sge_vx_nxv8i32:1837; CHECK:       # %bb.0:1838; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1839; CHECK-NEXT:    vmv.v.x v12, a01840; CHECK-NEXT:    vmsle.vv v0, v12, v81841; CHECK-NEXT:    ret1842  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01843  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1844  %vc = icmp sge <vscale x 8 x i32> %va, %splat1845  ret <vscale x 8 x i1> %vc1846}1847 1848define <vscale x 8 x i1> @icmp_sge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1849; CHECK-LABEL: icmp_sge_xv_nxv8i32:1850; CHECK:       # %bb.0:1851; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1852; CHECK-NEXT:    vmsle.vx v0, v8, a01853; CHECK-NEXT:    ret1854  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01855  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1856  %vc = icmp sge <vscale x 8 x i32> %splat, %va1857  ret <vscale x 8 x i1> %vc1858}1859 1860define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {1861; CHECK-LABEL: icmp_sge_vi_nxv8i32_0:1862; CHECK:       # %bb.0:1863; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1864; CHECK-NEXT:    vmv.v.i v12, -161865; CHECK-NEXT:    vmsle.vv v0, v12, v81866; CHECK-NEXT:    ret1867  %vc = icmp sge <vscale x 8 x i32> %va, splat (i32 -16)1868  ret <vscale x 8 x i1> %vc1869}1870 1871define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {1872; CHECK-LABEL: icmp_sge_vi_nxv8i32_1:1873; CHECK:       # %bb.0:1874; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1875; CHECK-NEXT:    vmsgt.vi v0, v8, -161876; CHECK-NEXT:    ret1877  %vc = icmp sge <vscale x 8 x i32> %va, splat (i32 -15)1878  ret <vscale x 8 x i1> %vc1879}1880 1881define <vscale x 8 x i1> @icmp_sge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {1882; CHECK-LABEL: icmp_sge_iv_nxv8i32_1:1883; CHECK:       # %bb.0:1884; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1885; CHECK-NEXT:    vmsle.vi v0, v8, -151886; CHECK-NEXT:    ret1887  %vc = icmp sge <vscale x 8 x i32> splat (i32 -15), %va1888  ret <vscale x 8 x i1> %vc1889}1890 1891define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {1892; CHECK-LABEL: icmp_sge_vi_nxv8i32_2:1893; CHECK:       # %bb.0:1894; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1895; CHECK-NEXT:    vmsgt.vi v0, v8, -11896; CHECK-NEXT:    ret1897  %vc = icmp sge <vscale x 8 x i32> %va, splat (i32 0)1898  ret <vscale x 8 x i1> %vc1899}1900 1901define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {1902; CHECK-LABEL: icmp_sge_vi_nxv8i32_3:1903; CHECK:       # %bb.0:1904; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1905; CHECK-NEXT:    vmsgt.vi v0, v8, 151906; CHECK-NEXT:    ret1907  %vc = icmp sge <vscale x 8 x i32> %va, splat (i32 16)1908  ret <vscale x 8 x i1> %vc1909}1910 1911define <vscale x 8 x i1> @icmp_slt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {1912; CHECK-LABEL: icmp_slt_vv_nxv8i32:1913; CHECK:       # %bb.0:1914; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1915; CHECK-NEXT:    vmslt.vv v0, v8, v121916; CHECK-NEXT:    ret1917  %vc = icmp slt <vscale x 8 x i32> %va, %vb1918  ret <vscale x 8 x i1> %vc1919}1920 1921define <vscale x 8 x i1> @icmp_slt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1922; CHECK-LABEL: icmp_slt_vx_nxv8i32:1923; CHECK:       # %bb.0:1924; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1925; CHECK-NEXT:    vmslt.vx v0, v8, a01926; CHECK-NEXT:    ret1927  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01928  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1929  %vc = icmp slt <vscale x 8 x i32> %va, %splat1930  ret <vscale x 8 x i1> %vc1931}1932 1933define <vscale x 8 x i1> @icmp_slt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {1934; CHECK-LABEL: icmp_slt_xv_nxv8i32:1935; CHECK:       # %bb.0:1936; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1937; CHECK-NEXT:    vmsgt.vx v0, v8, a01938; CHECK-NEXT:    ret1939  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01940  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1941  %vc = icmp slt <vscale x 8 x i32> %splat, %va1942  ret <vscale x 8 x i1> %vc1943}1944 1945define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {1946; CHECK-LABEL: icmp_slt_vi_nxv8i32_0:1947; CHECK:       # %bb.0:1948; CHECK-NEXT:    li a0, -161949; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma1950; CHECK-NEXT:    vmslt.vx v0, v8, a01951; CHECK-NEXT:    ret1952  %vc = icmp slt <vscale x 8 x i32> %va, splat (i32 -16)1953  ret <vscale x 8 x i1> %vc1954}1955 1956define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_1(<vscale x 8 x i32> %va) {1957; CHECK-LABEL: icmp_slt_vi_nxv8i32_1:1958; CHECK:       # %bb.0:1959; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1960; CHECK-NEXT:    vmsle.vi v0, v8, -161961; CHECK-NEXT:    ret1962  %vc = icmp slt <vscale x 8 x i32> %va, splat (i32 -15)1963  ret <vscale x 8 x i1> %vc1964}1965 1966define <vscale x 8 x i1> @icmp_slt_iv_nxv8i32_1(<vscale x 8 x i32> %va) {1967; CHECK-LABEL: icmp_slt_iv_nxv8i32_1:1968; CHECK:       # %bb.0:1969; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1970; CHECK-NEXT:    vmsgt.vi v0, v8, -151971; CHECK-NEXT:    ret1972  %vc = icmp slt <vscale x 8 x i32> splat (i32 -15), %va1973  ret <vscale x 8 x i1> %vc1974}1975 1976define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) {1977; CHECK-LABEL: icmp_slt_vi_nxv8i32_2:1978; CHECK:       # %bb.0:1979; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1980; CHECK-NEXT:    vmsle.vi v0, v8, -11981; CHECK-NEXT:    ret1982  %vc = icmp slt <vscale x 8 x i32> %va, splat (i32 0)1983  ret <vscale x 8 x i1> %vc1984}1985 1986define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_3(<vscale x 8 x i32> %va) {1987; CHECK-LABEL: icmp_slt_vi_nxv8i32_3:1988; CHECK:       # %bb.0:1989; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1990; CHECK-NEXT:    vmsle.vi v0, v8, 151991; CHECK-NEXT:    ret1992  %vc = icmp slt <vscale x 8 x i32> %va, splat (i32 16)1993  ret <vscale x 8 x i1> %vc1994}1995 1996define <vscale x 8 x i1> @icmp_sle_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {1997; CHECK-LABEL: icmp_sle_vv_nxv8i32:1998; CHECK:       # %bb.0:1999; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma2000; CHECK-NEXT:    vmsle.vv v0, v8, v122001; CHECK-NEXT:    ret2002  %vc = icmp sle <vscale x 8 x i32> %va, %vb2003  ret <vscale x 8 x i1> %vc2004}2005 2006define <vscale x 8 x i1> @icmp_sle_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {2007; CHECK-LABEL: icmp_sle_vx_nxv8i32:2008; CHECK:       # %bb.0:2009; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma2010; CHECK-NEXT:    vmsle.vx v0, v8, a02011; CHECK-NEXT:    ret2012  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 02013  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer2014  %vc = icmp sle <vscale x 8 x i32> %va, %splat2015  ret <vscale x 8 x i1> %vc2016}2017 2018define <vscale x 8 x i1> @icmp_sle_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {2019; CHECK-LABEL: icmp_sle_xv_nxv8i32:2020; CHECK:       # %bb.0:2021; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma2022; CHECK-NEXT:    vmv.v.x v12, a02023; CHECK-NEXT:    vmsle.vv v0, v12, v82024; CHECK-NEXT:    ret2025  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 02026  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer2027  %vc = icmp sle <vscale x 8 x i32> %splat, %va2028  ret <vscale x 8 x i1> %vc2029}2030 2031define <vscale x 8 x i1> @icmp_sle_vi_nxv8i32_0(<vscale x 8 x i32> %va) {2032; CHECK-LABEL: icmp_sle_vi_nxv8i32_0:2033; CHECK:       # %bb.0:2034; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma2035; CHECK-NEXT:    vmsle.vi v0, v8, 52036; CHECK-NEXT:    ret2037  %vc = icmp sle <vscale x 8 x i32> %va, splat (i32 5)2038  ret <vscale x 8 x i1> %vc2039}2040 2041define <vscale x 8 x i1> @icmp_eq_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {2042; CHECK-LABEL: icmp_eq_vv_nxv8i64:2043; CHECK:       # %bb.0:2044; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2045; CHECK-NEXT:    vmseq.vv v0, v8, v162046; CHECK-NEXT:    ret2047  %vc = icmp eq <vscale x 8 x i64> %va, %vb2048  ret <vscale x 8 x i1> %vc2049}2050 2051define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2052; RV32-LABEL: icmp_eq_vx_nxv8i64:2053; RV32:       # %bb.0:2054; RV32-NEXT:    addi sp, sp, -162055; RV32-NEXT:    .cfi_def_cfa_offset 162056; RV32-NEXT:    sw a0, 8(sp)2057; RV32-NEXT:    sw a1, 12(sp)2058; RV32-NEXT:    addi a0, sp, 82059; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2060; RV32-NEXT:    vlse64.v v16, (a0), zero2061; RV32-NEXT:    vmseq.vv v0, v8, v162062; RV32-NEXT:    addi sp, sp, 162063; RV32-NEXT:    .cfi_def_cfa_offset 02064; RV32-NEXT:    ret2065;2066; RV64-LABEL: icmp_eq_vx_nxv8i64:2067; RV64:       # %bb.0:2068; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2069; RV64-NEXT:    vmseq.vx v0, v8, a02070; RV64-NEXT:    ret2071  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02072  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2073  %vc = icmp eq <vscale x 8 x i64> %va, %splat2074  ret <vscale x 8 x i1> %vc2075}2076 2077define <vscale x 8 x i1> @icmp_eq_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2078; RV32-LABEL: icmp_eq_xv_nxv8i64:2079; RV32:       # %bb.0:2080; RV32-NEXT:    addi sp, sp, -162081; RV32-NEXT:    .cfi_def_cfa_offset 162082; RV32-NEXT:    sw a0, 8(sp)2083; RV32-NEXT:    sw a1, 12(sp)2084; RV32-NEXT:    addi a0, sp, 82085; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2086; RV32-NEXT:    vlse64.v v16, (a0), zero2087; RV32-NEXT:    vmseq.vv v0, v16, v82088; RV32-NEXT:    addi sp, sp, 162089; RV32-NEXT:    .cfi_def_cfa_offset 02090; RV32-NEXT:    ret2091;2092; RV64-LABEL: icmp_eq_xv_nxv8i64:2093; RV64:       # %bb.0:2094; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2095; RV64-NEXT:    vmseq.vx v0, v8, a02096; RV64-NEXT:    ret2097  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02098  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2099  %vc = icmp eq <vscale x 8 x i64> %splat, %va2100  ret <vscale x 8 x i1> %vc2101}2102 2103define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_0(<vscale x 8 x i64> %va) {2104; CHECK-LABEL: icmp_eq_vi_nxv8i64_0:2105; CHECK:       # %bb.0:2106; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2107; CHECK-NEXT:    vmseq.vi v0, v8, 02108; CHECK-NEXT:    ret2109  %vc = icmp eq <vscale x 8 x i64> %va, splat (i64 0)2110  ret <vscale x 8 x i1> %vc2111}2112 2113define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_1(<vscale x 8 x i64> %va) {2114; CHECK-LABEL: icmp_eq_vi_nxv8i64_1:2115; CHECK:       # %bb.0:2116; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2117; CHECK-NEXT:    vmseq.vi v0, v8, 52118; CHECK-NEXT:    ret2119  %vc = icmp eq <vscale x 8 x i64> %va, splat (i64 5)2120  ret <vscale x 8 x i1> %vc2121}2122 2123define <vscale x 8 x i1> @icmp_eq_iv_nxv8i64_1(<vscale x 8 x i64> %va) {2124; CHECK-LABEL: icmp_eq_iv_nxv8i64_1:2125; CHECK:       # %bb.0:2126; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2127; CHECK-NEXT:    vmseq.vi v0, v8, 52128; CHECK-NEXT:    ret2129  %vc = icmp eq <vscale x 8 x i64> splat (i64 5), %va2130  ret <vscale x 8 x i1> %vc2131}2132 2133define <vscale x 8 x i1> @icmp_ne_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {2134; CHECK-LABEL: icmp_ne_vv_nxv8i64:2135; CHECK:       # %bb.0:2136; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2137; CHECK-NEXT:    vmsne.vv v0, v8, v162138; CHECK-NEXT:    ret2139  %vc = icmp ne <vscale x 8 x i64> %va, %vb2140  ret <vscale x 8 x i1> %vc2141}2142 2143define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2144; RV32-LABEL: icmp_ne_vx_nxv8i64:2145; RV32:       # %bb.0:2146; RV32-NEXT:    addi sp, sp, -162147; RV32-NEXT:    .cfi_def_cfa_offset 162148; RV32-NEXT:    sw a0, 8(sp)2149; RV32-NEXT:    sw a1, 12(sp)2150; RV32-NEXT:    addi a0, sp, 82151; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2152; RV32-NEXT:    vlse64.v v16, (a0), zero2153; RV32-NEXT:    vmsne.vv v0, v8, v162154; RV32-NEXT:    addi sp, sp, 162155; RV32-NEXT:    .cfi_def_cfa_offset 02156; RV32-NEXT:    ret2157;2158; RV64-LABEL: icmp_ne_vx_nxv8i64:2159; RV64:       # %bb.0:2160; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2161; RV64-NEXT:    vmsne.vx v0, v8, a02162; RV64-NEXT:    ret2163  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02164  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2165  %vc = icmp ne <vscale x 8 x i64> %va, %splat2166  ret <vscale x 8 x i1> %vc2167}2168 2169define <vscale x 8 x i1> @icmp_ne_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2170; RV32-LABEL: icmp_ne_xv_nxv8i64:2171; RV32:       # %bb.0:2172; RV32-NEXT:    addi sp, sp, -162173; RV32-NEXT:    .cfi_def_cfa_offset 162174; RV32-NEXT:    sw a0, 8(sp)2175; RV32-NEXT:    sw a1, 12(sp)2176; RV32-NEXT:    addi a0, sp, 82177; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2178; RV32-NEXT:    vlse64.v v16, (a0), zero2179; RV32-NEXT:    vmsne.vv v0, v16, v82180; RV32-NEXT:    addi sp, sp, 162181; RV32-NEXT:    .cfi_def_cfa_offset 02182; RV32-NEXT:    ret2183;2184; RV64-LABEL: icmp_ne_xv_nxv8i64:2185; RV64:       # %bb.0:2186; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2187; RV64-NEXT:    vmsne.vx v0, v8, a02188; RV64-NEXT:    ret2189  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02190  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2191  %vc = icmp ne <vscale x 8 x i64> %splat, %va2192  ret <vscale x 8 x i1> %vc2193}2194 2195define <vscale x 8 x i1> @icmp_ne_vi_nxv8i64_0(<vscale x 8 x i64> %va) {2196; CHECK-LABEL: icmp_ne_vi_nxv8i64_0:2197; CHECK:       # %bb.0:2198; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2199; CHECK-NEXT:    vmsne.vi v0, v8, 52200; CHECK-NEXT:    ret2201  %vc = icmp ne <vscale x 8 x i64> %va, splat (i64 5)2202  ret <vscale x 8 x i1> %vc2203}2204 2205define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {2206; CHECK-LABEL: icmp_ugt_vv_nxv8i64:2207; CHECK:       # %bb.0:2208; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2209; CHECK-NEXT:    vmsltu.vv v0, v16, v82210; CHECK-NEXT:    ret2211  %vc = icmp ugt <vscale x 8 x i64> %va, %vb2212  ret <vscale x 8 x i1> %vc2213}2214 2215define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2216; RV32-LABEL: icmp_ugt_vx_nxv8i64:2217; RV32:       # %bb.0:2218; RV32-NEXT:    addi sp, sp, -162219; RV32-NEXT:    .cfi_def_cfa_offset 162220; RV32-NEXT:    sw a0, 8(sp)2221; RV32-NEXT:    sw a1, 12(sp)2222; RV32-NEXT:    addi a0, sp, 82223; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2224; RV32-NEXT:    vlse64.v v16, (a0), zero2225; RV32-NEXT:    vmsltu.vv v0, v16, v82226; RV32-NEXT:    addi sp, sp, 162227; RV32-NEXT:    .cfi_def_cfa_offset 02228; RV32-NEXT:    ret2229;2230; RV64-LABEL: icmp_ugt_vx_nxv8i64:2231; RV64:       # %bb.0:2232; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2233; RV64-NEXT:    vmsgtu.vx v0, v8, a02234; RV64-NEXT:    ret2235  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02236  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2237  %vc = icmp ugt <vscale x 8 x i64> %va, %splat2238  ret <vscale x 8 x i1> %vc2239}2240 2241define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2242; RV32-LABEL: icmp_ugt_xv_nxv8i64:2243; RV32:       # %bb.0:2244; RV32-NEXT:    addi sp, sp, -162245; RV32-NEXT:    .cfi_def_cfa_offset 162246; RV32-NEXT:    sw a0, 8(sp)2247; RV32-NEXT:    sw a1, 12(sp)2248; RV32-NEXT:    addi a0, sp, 82249; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2250; RV32-NEXT:    vlse64.v v16, (a0), zero2251; RV32-NEXT:    vmsltu.vv v0, v8, v162252; RV32-NEXT:    addi sp, sp, 162253; RV32-NEXT:    .cfi_def_cfa_offset 02254; RV32-NEXT:    ret2255;2256; RV64-LABEL: icmp_ugt_xv_nxv8i64:2257; RV64:       # %bb.0:2258; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2259; RV64-NEXT:    vmsltu.vx v0, v8, a02260; RV64-NEXT:    ret2261  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02262  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2263  %vc = icmp ugt <vscale x 8 x i64> %splat, %va2264  ret <vscale x 8 x i1> %vc2265}2266 2267define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {2268; CHECK-LABEL: icmp_ugt_vi_nxv8i64_0:2269; CHECK:       # %bb.0:2270; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2271; CHECK-NEXT:    vmsgtu.vi v0, v8, 52272; CHECK-NEXT:    ret2273  %vc = icmp ugt <vscale x 8 x i64> %va, splat (i64 5)2274  ret <vscale x 8 x i1> %vc2275}2276 2277define <vscale x 8 x i1> @icmp_uge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {2278; CHECK-LABEL: icmp_uge_vv_nxv8i64:2279; CHECK:       # %bb.0:2280; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2281; CHECK-NEXT:    vmsleu.vv v0, v16, v82282; CHECK-NEXT:    ret2283  %vc = icmp uge <vscale x 8 x i64> %va, %vb2284  ret <vscale x 8 x i1> %vc2285}2286 2287define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2288; RV32-LABEL: icmp_uge_vx_nxv8i64:2289; RV32:       # %bb.0:2290; RV32-NEXT:    addi sp, sp, -162291; RV32-NEXT:    .cfi_def_cfa_offset 162292; RV32-NEXT:    sw a0, 8(sp)2293; RV32-NEXT:    sw a1, 12(sp)2294; RV32-NEXT:    addi a0, sp, 82295; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2296; RV32-NEXT:    vlse64.v v16, (a0), zero2297; RV32-NEXT:    vmsleu.vv v0, v16, v82298; RV32-NEXT:    addi sp, sp, 162299; RV32-NEXT:    .cfi_def_cfa_offset 02300; RV32-NEXT:    ret2301;2302; RV64-LABEL: icmp_uge_vx_nxv8i64:2303; RV64:       # %bb.0:2304; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2305; RV64-NEXT:    vmv.v.x v16, a02306; RV64-NEXT:    vmsleu.vv v0, v16, v82307; RV64-NEXT:    ret2308  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02309  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2310  %vc = icmp uge <vscale x 8 x i64> %va, %splat2311  ret <vscale x 8 x i1> %vc2312}2313 2314define <vscale x 8 x i1> @icmp_uge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2315; RV32-LABEL: icmp_uge_xv_nxv8i64:2316; RV32:       # %bb.0:2317; RV32-NEXT:    addi sp, sp, -162318; RV32-NEXT:    .cfi_def_cfa_offset 162319; RV32-NEXT:    sw a0, 8(sp)2320; RV32-NEXT:    sw a1, 12(sp)2321; RV32-NEXT:    addi a0, sp, 82322; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2323; RV32-NEXT:    vlse64.v v16, (a0), zero2324; RV32-NEXT:    vmsleu.vv v0, v8, v162325; RV32-NEXT:    addi sp, sp, 162326; RV32-NEXT:    .cfi_def_cfa_offset 02327; RV32-NEXT:    ret2328;2329; RV64-LABEL: icmp_uge_xv_nxv8i64:2330; RV64:       # %bb.0:2331; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2332; RV64-NEXT:    vmsleu.vx v0, v8, a02333; RV64-NEXT:    ret2334  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02335  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2336  %vc = icmp uge <vscale x 8 x i64> %splat, %va2337  ret <vscale x 8 x i1> %vc2338}2339 2340define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {2341; CHECK-LABEL: icmp_uge_vi_nxv8i64_0:2342; CHECK:       # %bb.0:2343; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2344; CHECK-NEXT:    vmv.v.i v16, -162345; CHECK-NEXT:    vmsleu.vv v0, v16, v82346; CHECK-NEXT:    ret2347  %vc = icmp uge <vscale x 8 x i64> %va, splat (i64 -16)2348  ret <vscale x 8 x i1> %vc2349}2350 2351define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {2352; CHECK-LABEL: icmp_uge_vi_nxv8i64_1:2353; CHECK:       # %bb.0:2354; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2355; CHECK-NEXT:    vmsgtu.vi v0, v8, 142356; CHECK-NEXT:    ret2357  %vc = icmp uge <vscale x 8 x i64> %va, splat (i64 15)2358  ret <vscale x 8 x i1> %vc2359}2360 2361define <vscale x 8 x i1> @icmp_uge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {2362; CHECK-LABEL: icmp_uge_iv_nxv8i64_1:2363; CHECK:       # %bb.0:2364; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2365; CHECK-NEXT:    vmsleu.vi v0, v8, 152366; CHECK-NEXT:    ret2367  %vc = icmp uge <vscale x 8 x i64> splat (i64 15), %va2368  ret <vscale x 8 x i1> %vc2369}2370 2371define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {2372; CHECK-LABEL: icmp_uge_vi_nxv8i64_2:2373; CHECK:       # %bb.0:2374; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma2375; CHECK-NEXT:    vmset.m v02376; CHECK-NEXT:    ret2377  %vc = icmp uge <vscale x 8 x i64> %va, splat (i64 0)2378  ret <vscale x 8 x i1> %vc2379}2380 2381define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {2382; CHECK-LABEL: icmp_uge_vi_nxv8i64_3:2383; CHECK:       # %bb.0:2384; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2385; CHECK-NEXT:    vmsgtu.vi v0, v8, 02386; CHECK-NEXT:    ret2387  %vc = icmp uge <vscale x 8 x i64> %va, splat (i64 1)2388  ret <vscale x 8 x i1> %vc2389}2390 2391define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_4(<vscale x 8 x i64> %va) {2392; CHECK-LABEL: icmp_uge_vi_nxv8i64_4:2393; CHECK:       # %bb.0:2394; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2395; CHECK-NEXT:    vmsgtu.vi v0, v8, -162396; CHECK-NEXT:    ret2397  %vc = icmp uge <vscale x 8 x i64> %va, splat (i64 -15)2398  ret <vscale x 8 x i1> %vc2399}2400 2401define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_5(<vscale x 8 x i64> %va) {2402; CHECK-LABEL: icmp_uge_vi_nxv8i64_5:2403; CHECK:       # %bb.0:2404; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2405; CHECK-NEXT:    vmsgtu.vi v0, v8, 152406; CHECK-NEXT:    ret2407  %vc = icmp uge <vscale x 8 x i64> %va, splat (i64 16)2408  ret <vscale x 8 x i1> %vc2409}2410 2411define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {2412; CHECK-LABEL: icmp_ult_vv_nxv8i64:2413; CHECK:       # %bb.0:2414; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2415; CHECK-NEXT:    vmsltu.vv v0, v8, v162416; CHECK-NEXT:    ret2417  %vc = icmp ult <vscale x 8 x i64> %va, %vb2418  ret <vscale x 8 x i1> %vc2419}2420 2421define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2422; RV32-LABEL: icmp_ult_vx_nxv8i64:2423; RV32:       # %bb.0:2424; RV32-NEXT:    addi sp, sp, -162425; RV32-NEXT:    .cfi_def_cfa_offset 162426; RV32-NEXT:    sw a0, 8(sp)2427; RV32-NEXT:    sw a1, 12(sp)2428; RV32-NEXT:    addi a0, sp, 82429; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2430; RV32-NEXT:    vlse64.v v16, (a0), zero2431; RV32-NEXT:    vmsltu.vv v0, v8, v162432; RV32-NEXT:    addi sp, sp, 162433; RV32-NEXT:    .cfi_def_cfa_offset 02434; RV32-NEXT:    ret2435;2436; RV64-LABEL: icmp_ult_vx_nxv8i64:2437; RV64:       # %bb.0:2438; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2439; RV64-NEXT:    vmsltu.vx v0, v8, a02440; RV64-NEXT:    ret2441  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02442  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2443  %vc = icmp ult <vscale x 8 x i64> %va, %splat2444  ret <vscale x 8 x i1> %vc2445}2446 2447define <vscale x 8 x i1> @icmp_ult_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2448; RV32-LABEL: icmp_ult_xv_nxv8i64:2449; RV32:       # %bb.0:2450; RV32-NEXT:    addi sp, sp, -162451; RV32-NEXT:    .cfi_def_cfa_offset 162452; RV32-NEXT:    sw a0, 8(sp)2453; RV32-NEXT:    sw a1, 12(sp)2454; RV32-NEXT:    addi a0, sp, 82455; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2456; RV32-NEXT:    vlse64.v v16, (a0), zero2457; RV32-NEXT:    vmsltu.vv v0, v16, v82458; RV32-NEXT:    addi sp, sp, 162459; RV32-NEXT:    .cfi_def_cfa_offset 02460; RV32-NEXT:    ret2461;2462; RV64-LABEL: icmp_ult_xv_nxv8i64:2463; RV64:       # %bb.0:2464; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2465; RV64-NEXT:    vmsgtu.vx v0, v8, a02466; RV64-NEXT:    ret2467  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02468  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2469  %vc = icmp ult <vscale x 8 x i64> %splat, %va2470  ret <vscale x 8 x i1> %vc2471}2472 2473define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_0(<vscale x 8 x i64> %va) {2474; CHECK-LABEL: icmp_ult_vi_nxv8i64_0:2475; CHECK:       # %bb.0:2476; CHECK-NEXT:    li a0, -162477; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2478; CHECK-NEXT:    vmsltu.vx v0, v8, a02479; CHECK-NEXT:    ret2480  %vc = icmp ult <vscale x 8 x i64> %va, splat (i64 -16)2481  ret <vscale x 8 x i1> %vc2482}2483 2484define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_1(<vscale x 8 x i64> %va) {2485; CHECK-LABEL: icmp_ult_vi_nxv8i64_1:2486; CHECK:       # %bb.0:2487; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2488; CHECK-NEXT:    vmsleu.vi v0, v8, -162489; CHECK-NEXT:    ret2490  %vc = icmp ult <vscale x 8 x i64> %va, splat (i64 -15)2491  ret <vscale x 8 x i1> %vc2492}2493 2494define <vscale x 8 x i1> @icmp_ult_iv_nxv8i64_1(<vscale x 8 x i64> %va) {2495; CHECK-LABEL: icmp_ult_iv_nxv8i64_1:2496; CHECK:       # %bb.0:2497; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2498; CHECK-NEXT:    vmsgtu.vi v0, v8, -152499; CHECK-NEXT:    ret2500  %vc = icmp ult <vscale x 8 x i64> splat (i64 -15), %va2501  ret <vscale x 8 x i1> %vc2502}2503 2504define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_2(<vscale x 8 x i64> %va) {2505; CHECK-LABEL: icmp_ult_vi_nxv8i64_2:2506; CHECK:       # %bb.0:2507; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma2508; CHECK-NEXT:    vmclr.m v02509; CHECK-NEXT:    ret2510  %vc = icmp ult <vscale x 8 x i64> %va, splat (i64 0)2511  ret <vscale x 8 x i1> %vc2512}2513 2514define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_3(<vscale x 8 x i64> %va) {2515; CHECK-LABEL: icmp_ult_vi_nxv8i64_3:2516; CHECK:       # %bb.0:2517; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2518; CHECK-NEXT:    vmseq.vi v0, v8, 02519; CHECK-NEXT:    ret2520  %vc = icmp ult <vscale x 8 x i64> %va, splat (i64 1)2521  ret <vscale x 8 x i1> %vc2522}2523 2524define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_4(<vscale x 8 x i64> %va) {2525; CHECK-LABEL: icmp_ult_vi_nxv8i64_4:2526; CHECK:       # %bb.0:2527; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2528; CHECK-NEXT:    vmsleu.vi v0, v8, 152529; CHECK-NEXT:    ret2530  %vc = icmp ult <vscale x 8 x i64> %va, splat (i64 16)2531  ret <vscale x 8 x i1> %vc2532}2533 2534define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {2535; CHECK-LABEL: icmp_ule_vv_nxv8i64:2536; CHECK:       # %bb.0:2537; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2538; CHECK-NEXT:    vmsleu.vv v0, v8, v162539; CHECK-NEXT:    ret2540  %vc = icmp ule <vscale x 8 x i64> %va, %vb2541  ret <vscale x 8 x i1> %vc2542}2543 2544define <vscale x 8 x i1> @icmp_ule_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2545; RV32-LABEL: icmp_ule_vx_nxv8i64:2546; RV32:       # %bb.0:2547; RV32-NEXT:    addi sp, sp, -162548; RV32-NEXT:    .cfi_def_cfa_offset 162549; RV32-NEXT:    sw a0, 8(sp)2550; RV32-NEXT:    sw a1, 12(sp)2551; RV32-NEXT:    addi a0, sp, 82552; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2553; RV32-NEXT:    vlse64.v v16, (a0), zero2554; RV32-NEXT:    vmsleu.vv v0, v8, v162555; RV32-NEXT:    addi sp, sp, 162556; RV32-NEXT:    .cfi_def_cfa_offset 02557; RV32-NEXT:    ret2558;2559; RV64-LABEL: icmp_ule_vx_nxv8i64:2560; RV64:       # %bb.0:2561; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2562; RV64-NEXT:    vmsleu.vx v0, v8, a02563; RV64-NEXT:    ret2564  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02565  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2566  %vc = icmp ule <vscale x 8 x i64> %va, %splat2567  ret <vscale x 8 x i1> %vc2568}2569 2570define <vscale x 8 x i1> @icmp_ule_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2571; RV32-LABEL: icmp_ule_xv_nxv8i64:2572; RV32:       # %bb.0:2573; RV32-NEXT:    addi sp, sp, -162574; RV32-NEXT:    .cfi_def_cfa_offset 162575; RV32-NEXT:    sw a0, 8(sp)2576; RV32-NEXT:    sw a1, 12(sp)2577; RV32-NEXT:    addi a0, sp, 82578; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2579; RV32-NEXT:    vlse64.v v16, (a0), zero2580; RV32-NEXT:    vmsleu.vv v0, v16, v82581; RV32-NEXT:    addi sp, sp, 162582; RV32-NEXT:    .cfi_def_cfa_offset 02583; RV32-NEXT:    ret2584;2585; RV64-LABEL: icmp_ule_xv_nxv8i64:2586; RV64:       # %bb.0:2587; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2588; RV64-NEXT:    vmv.v.x v16, a02589; RV64-NEXT:    vmsleu.vv v0, v16, v82590; RV64-NEXT:    ret2591  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02592  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2593  %vc = icmp ule <vscale x 8 x i64> %splat, %va2594  ret <vscale x 8 x i1> %vc2595}2596 2597define <vscale x 8 x i1> @icmp_ule_vi_nxv8i64_0(<vscale x 8 x i64> %va) {2598; CHECK-LABEL: icmp_ule_vi_nxv8i64_0:2599; CHECK:       # %bb.0:2600; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2601; CHECK-NEXT:    vmsleu.vi v0, v8, 52602; CHECK-NEXT:    ret2603  %vc = icmp ule <vscale x 8 x i64> %va, splat (i64 5)2604  ret <vscale x 8 x i1> %vc2605}2606 2607define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {2608; CHECK-LABEL: icmp_sgt_vv_nxv8i64:2609; CHECK:       # %bb.0:2610; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2611; CHECK-NEXT:    vmslt.vv v0, v16, v82612; CHECK-NEXT:    ret2613  %vc = icmp sgt <vscale x 8 x i64> %va, %vb2614  ret <vscale x 8 x i1> %vc2615}2616 2617define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2618; RV32-LABEL: icmp_sgt_vx_nxv8i64:2619; RV32:       # %bb.0:2620; RV32-NEXT:    addi sp, sp, -162621; RV32-NEXT:    .cfi_def_cfa_offset 162622; RV32-NEXT:    sw a0, 8(sp)2623; RV32-NEXT:    sw a1, 12(sp)2624; RV32-NEXT:    addi a0, sp, 82625; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2626; RV32-NEXT:    vlse64.v v16, (a0), zero2627; RV32-NEXT:    vmslt.vv v0, v16, v82628; RV32-NEXT:    addi sp, sp, 162629; RV32-NEXT:    .cfi_def_cfa_offset 02630; RV32-NEXT:    ret2631;2632; RV64-LABEL: icmp_sgt_vx_nxv8i64:2633; RV64:       # %bb.0:2634; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2635; RV64-NEXT:    vmsgt.vx v0, v8, a02636; RV64-NEXT:    ret2637  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02638  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2639  %vc = icmp sgt <vscale x 8 x i64> %va, %splat2640  ret <vscale x 8 x i1> %vc2641}2642 2643define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2644; RV32-LABEL: icmp_sgt_xv_nxv8i64:2645; RV32:       # %bb.0:2646; RV32-NEXT:    addi sp, sp, -162647; RV32-NEXT:    .cfi_def_cfa_offset 162648; RV32-NEXT:    sw a0, 8(sp)2649; RV32-NEXT:    sw a1, 12(sp)2650; RV32-NEXT:    addi a0, sp, 82651; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2652; RV32-NEXT:    vlse64.v v16, (a0), zero2653; RV32-NEXT:    vmslt.vv v0, v8, v162654; RV32-NEXT:    addi sp, sp, 162655; RV32-NEXT:    .cfi_def_cfa_offset 02656; RV32-NEXT:    ret2657;2658; RV64-LABEL: icmp_sgt_xv_nxv8i64:2659; RV64:       # %bb.0:2660; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2661; RV64-NEXT:    vmslt.vx v0, v8, a02662; RV64-NEXT:    ret2663  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02664  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2665  %vc = icmp sgt <vscale x 8 x i64> %splat, %va2666  ret <vscale x 8 x i1> %vc2667}2668 2669define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {2670; CHECK-LABEL: icmp_sgt_vi_nxv8i64_0:2671; CHECK:       # %bb.0:2672; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2673; CHECK-NEXT:    vmsgt.vi v0, v8, 52674; CHECK-NEXT:    ret2675  %vc = icmp sgt <vscale x 8 x i64> %va, splat (i64 5)2676  ret <vscale x 8 x i1> %vc2677}2678 2679define <vscale x 8 x i1> @icmp_sge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {2680; CHECK-LABEL: icmp_sge_vv_nxv8i64:2681; CHECK:       # %bb.0:2682; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2683; CHECK-NEXT:    vmsle.vv v0, v16, v82684; CHECK-NEXT:    ret2685  %vc = icmp sge <vscale x 8 x i64> %va, %vb2686  ret <vscale x 8 x i1> %vc2687}2688 2689define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2690; RV32-LABEL: icmp_sge_vx_nxv8i64:2691; RV32:       # %bb.0:2692; RV32-NEXT:    addi sp, sp, -162693; RV32-NEXT:    .cfi_def_cfa_offset 162694; RV32-NEXT:    sw a0, 8(sp)2695; RV32-NEXT:    sw a1, 12(sp)2696; RV32-NEXT:    addi a0, sp, 82697; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2698; RV32-NEXT:    vlse64.v v16, (a0), zero2699; RV32-NEXT:    vmsle.vv v0, v16, v82700; RV32-NEXT:    addi sp, sp, 162701; RV32-NEXT:    .cfi_def_cfa_offset 02702; RV32-NEXT:    ret2703;2704; RV64-LABEL: icmp_sge_vx_nxv8i64:2705; RV64:       # %bb.0:2706; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2707; RV64-NEXT:    vmv.v.x v16, a02708; RV64-NEXT:    vmsle.vv v0, v16, v82709; RV64-NEXT:    ret2710  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02711  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2712  %vc = icmp sge <vscale x 8 x i64> %va, %splat2713  ret <vscale x 8 x i1> %vc2714}2715 2716define <vscale x 8 x i1> @icmp_sge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2717; RV32-LABEL: icmp_sge_xv_nxv8i64:2718; RV32:       # %bb.0:2719; RV32-NEXT:    addi sp, sp, -162720; RV32-NEXT:    .cfi_def_cfa_offset 162721; RV32-NEXT:    sw a0, 8(sp)2722; RV32-NEXT:    sw a1, 12(sp)2723; RV32-NEXT:    addi a0, sp, 82724; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2725; RV32-NEXT:    vlse64.v v16, (a0), zero2726; RV32-NEXT:    vmsle.vv v0, v8, v162727; RV32-NEXT:    addi sp, sp, 162728; RV32-NEXT:    .cfi_def_cfa_offset 02729; RV32-NEXT:    ret2730;2731; RV64-LABEL: icmp_sge_xv_nxv8i64:2732; RV64:       # %bb.0:2733; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2734; RV64-NEXT:    vmsle.vx v0, v8, a02735; RV64-NEXT:    ret2736  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02737  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2738  %vc = icmp sge <vscale x 8 x i64> %splat, %va2739  ret <vscale x 8 x i1> %vc2740}2741 2742define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {2743; CHECK-LABEL: icmp_sge_vi_nxv8i64_0:2744; CHECK:       # %bb.0:2745; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2746; CHECK-NEXT:    vmv.v.i v16, -162747; CHECK-NEXT:    vmsle.vv v0, v16, v82748; CHECK-NEXT:    ret2749  %vc = icmp sge <vscale x 8 x i64> %va, splat (i64 -16)2750  ret <vscale x 8 x i1> %vc2751}2752 2753define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {2754; CHECK-LABEL: icmp_sge_vi_nxv8i64_1:2755; CHECK:       # %bb.0:2756; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2757; CHECK-NEXT:    vmsgt.vi v0, v8, -162758; CHECK-NEXT:    ret2759  %vc = icmp sge <vscale x 8 x i64> %va, splat (i64 -15)2760  ret <vscale x 8 x i1> %vc2761}2762 2763define <vscale x 8 x i1> @icmp_sge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {2764; CHECK-LABEL: icmp_sge_iv_nxv8i64_1:2765; CHECK:       # %bb.0:2766; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2767; CHECK-NEXT:    vmsle.vi v0, v8, -152768; CHECK-NEXT:    ret2769  %vc = icmp sge <vscale x 8 x i64> splat (i64 -15), %va2770  ret <vscale x 8 x i1> %vc2771}2772 2773define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {2774; CHECK-LABEL: icmp_sge_vi_nxv8i64_2:2775; CHECK:       # %bb.0:2776; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2777; CHECK-NEXT:    vmsgt.vi v0, v8, -12778; CHECK-NEXT:    ret2779  %vc = icmp sge <vscale x 8 x i64> %va, splat (i64 0)2780  ret <vscale x 8 x i1> %vc2781}2782 2783define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {2784; CHECK-LABEL: icmp_sge_vi_nxv8i64_3:2785; CHECK:       # %bb.0:2786; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2787; CHECK-NEXT:    vmsgt.vi v0, v8, 152788; CHECK-NEXT:    ret2789  %vc = icmp sge <vscale x 8 x i64> %va, splat (i64 16)2790  ret <vscale x 8 x i1> %vc2791}2792 2793define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {2794; CHECK-LABEL: icmp_slt_vv_nxv8i64:2795; CHECK:       # %bb.0:2796; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2797; CHECK-NEXT:    vmslt.vv v0, v8, v162798; CHECK-NEXT:    ret2799  %vc = icmp slt <vscale x 8 x i64> %va, %vb2800  ret <vscale x 8 x i1> %vc2801}2802 2803define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2804; RV32-LABEL: icmp_slt_vx_nxv8i64:2805; RV32:       # %bb.0:2806; RV32-NEXT:    addi sp, sp, -162807; RV32-NEXT:    .cfi_def_cfa_offset 162808; RV32-NEXT:    sw a0, 8(sp)2809; RV32-NEXT:    sw a1, 12(sp)2810; RV32-NEXT:    addi a0, sp, 82811; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2812; RV32-NEXT:    vlse64.v v16, (a0), zero2813; RV32-NEXT:    vmslt.vv v0, v8, v162814; RV32-NEXT:    addi sp, sp, 162815; RV32-NEXT:    .cfi_def_cfa_offset 02816; RV32-NEXT:    ret2817;2818; RV64-LABEL: icmp_slt_vx_nxv8i64:2819; RV64:       # %bb.0:2820; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2821; RV64-NEXT:    vmslt.vx v0, v8, a02822; RV64-NEXT:    ret2823  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02824  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2825  %vc = icmp slt <vscale x 8 x i64> %va, %splat2826  ret <vscale x 8 x i1> %vc2827}2828 2829define <vscale x 8 x i1> @icmp_slt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2830; RV32-LABEL: icmp_slt_xv_nxv8i64:2831; RV32:       # %bb.0:2832; RV32-NEXT:    addi sp, sp, -162833; RV32-NEXT:    .cfi_def_cfa_offset 162834; RV32-NEXT:    sw a0, 8(sp)2835; RV32-NEXT:    sw a1, 12(sp)2836; RV32-NEXT:    addi a0, sp, 82837; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2838; RV32-NEXT:    vlse64.v v16, (a0), zero2839; RV32-NEXT:    vmslt.vv v0, v16, v82840; RV32-NEXT:    addi sp, sp, 162841; RV32-NEXT:    .cfi_def_cfa_offset 02842; RV32-NEXT:    ret2843;2844; RV64-LABEL: icmp_slt_xv_nxv8i64:2845; RV64:       # %bb.0:2846; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2847; RV64-NEXT:    vmsgt.vx v0, v8, a02848; RV64-NEXT:    ret2849  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02850  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2851  %vc = icmp slt <vscale x 8 x i64> %splat, %va2852  ret <vscale x 8 x i1> %vc2853}2854 2855define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {2856; CHECK-LABEL: icmp_slt_vi_nxv8i64_0:2857; CHECK:       # %bb.0:2858; CHECK-NEXT:    li a0, -162859; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2860; CHECK-NEXT:    vmslt.vx v0, v8, a02861; CHECK-NEXT:    ret2862  %vc = icmp slt <vscale x 8 x i64> %va, splat (i64 -16)2863  ret <vscale x 8 x i1> %vc2864}2865 2866define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_1(<vscale x 8 x i64> %va) {2867; CHECK-LABEL: icmp_slt_vi_nxv8i64_1:2868; CHECK:       # %bb.0:2869; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2870; CHECK-NEXT:    vmsle.vi v0, v8, -162871; CHECK-NEXT:    ret2872  %vc = icmp slt <vscale x 8 x i64> %va, splat (i64 -15)2873  ret <vscale x 8 x i1> %vc2874}2875 2876define <vscale x 8 x i1> @icmp_slt_iv_nxv8i64_1(<vscale x 8 x i64> %va) {2877; CHECK-LABEL: icmp_slt_iv_nxv8i64_1:2878; CHECK:       # %bb.0:2879; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2880; CHECK-NEXT:    vmsgt.vi v0, v8, -152881; CHECK-NEXT:    ret2882  %vc = icmp slt <vscale x 8 x i64> splat (i64 -15), %va2883  ret <vscale x 8 x i1> %vc2884}2885 2886define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) {2887; CHECK-LABEL: icmp_slt_vi_nxv8i64_2:2888; CHECK:       # %bb.0:2889; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2890; CHECK-NEXT:    vmsle.vi v0, v8, -12891; CHECK-NEXT:    ret2892  %vc = icmp slt <vscale x 8 x i64> %va, splat (i64 0)2893  ret <vscale x 8 x i1> %vc2894}2895 2896define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_3(<vscale x 8 x i64> %va) {2897; CHECK-LABEL: icmp_slt_vi_nxv8i64_3:2898; CHECK:       # %bb.0:2899; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2900; CHECK-NEXT:    vmsle.vi v0, v8, 152901; CHECK-NEXT:    ret2902  %vc = icmp slt <vscale x 8 x i64> %va, splat (i64 16)2903  ret <vscale x 8 x i1> %vc2904}2905 2906define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {2907; CHECK-LABEL: icmp_sle_vv_nxv8i64:2908; CHECK:       # %bb.0:2909; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2910; CHECK-NEXT:    vmsle.vv v0, v8, v162911; CHECK-NEXT:    ret2912  %vc = icmp sle <vscale x 8 x i64> %va, %vb2913  ret <vscale x 8 x i1> %vc2914}2915 2916define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2917; RV32-LABEL: icmp_sle_vx_nxv8i64:2918; RV32:       # %bb.0:2919; RV32-NEXT:    addi sp, sp, -162920; RV32-NEXT:    .cfi_def_cfa_offset 162921; RV32-NEXT:    sw a0, 8(sp)2922; RV32-NEXT:    sw a1, 12(sp)2923; RV32-NEXT:    addi a0, sp, 82924; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2925; RV32-NEXT:    vlse64.v v16, (a0), zero2926; RV32-NEXT:    vmsle.vv v0, v8, v162927; RV32-NEXT:    addi sp, sp, 162928; RV32-NEXT:    .cfi_def_cfa_offset 02929; RV32-NEXT:    ret2930;2931; RV64-LABEL: icmp_sle_vx_nxv8i64:2932; RV64:       # %bb.0:2933; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2934; RV64-NEXT:    vmsle.vx v0, v8, a02935; RV64-NEXT:    ret2936  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02937  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2938  %vc = icmp sle <vscale x 8 x i64> %va, %splat2939  ret <vscale x 8 x i1> %vc2940}2941 2942define <vscale x 8 x i1> @icmp_sle_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {2943; RV32-LABEL: icmp_sle_xv_nxv8i64:2944; RV32:       # %bb.0:2945; RV32-NEXT:    addi sp, sp, -162946; RV32-NEXT:    .cfi_def_cfa_offset 162947; RV32-NEXT:    sw a0, 8(sp)2948; RV32-NEXT:    sw a1, 12(sp)2949; RV32-NEXT:    addi a0, sp, 82950; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2951; RV32-NEXT:    vlse64.v v16, (a0), zero2952; RV32-NEXT:    vmsle.vv v0, v16, v82953; RV32-NEXT:    addi sp, sp, 162954; RV32-NEXT:    .cfi_def_cfa_offset 02955; RV32-NEXT:    ret2956;2957; RV64-LABEL: icmp_sle_xv_nxv8i64:2958; RV64:       # %bb.0:2959; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma2960; RV64-NEXT:    vmv.v.x v16, a02961; RV64-NEXT:    vmsle.vv v0, v16, v82962; RV64-NEXT:    ret2963  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02964  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2965  %vc = icmp sle <vscale x 8 x i64> %splat, %va2966  ret <vscale x 8 x i1> %vc2967}2968 2969define <vscale x 8 x i1> @icmp_sle_vi_nxv8i64_0(<vscale x 8 x i64> %va) {2970; CHECK-LABEL: icmp_sle_vi_nxv8i64_0:2971; CHECK:       # %bb.0:2972; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma2973; CHECK-NEXT:    vmsle.vi v0, v8, 52974; CHECK-NEXT:    ret2975  %vc = icmp sle <vscale x 8 x i64> %va, splat (i64 5)2976  ret <vscale x 8 x i1> %vc2977}2978 2979; Check a setcc with two constant splats, which would previously get stuck in2980; an infinite loop. DAGCombine isn't clever enough to constant-fold2981; splat_vectors but could continuously swap the operands, trying to put the2982; splat on the RHS.2983define <vscale x 8 x i1> @icmp_eq_ii_nxv8i8() {2984; CHECK-LABEL: icmp_eq_ii_nxv8i8:2985; CHECK:       # %bb.0:2986; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma2987; CHECK-NEXT:    vmclr.m v02988; CHECK-NEXT:    ret2989  %vc = icmp eq <vscale x 8 x i8> splat (i8 5), splat (i8 2)2990  ret <vscale x 8 x i1> %vc2991}2992 2993; This icmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR2994; node. Ensure we correctly (custom) lower this.2995define <vscale x 16 x i1> @icmp_eq_vi_nx16i64(<vscale x 16 x i64> %va) {2996; CHECK-LABEL: icmp_eq_vi_nx16i64:2997; CHECK:       # %bb.0:2998; CHECK-NEXT:    csrr a0, vlenb2999; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma3000; CHECK-NEXT:    vmseq.vi v24, v16, 03001; CHECK-NEXT:    srli a0, a0, 33002; CHECK-NEXT:    vmseq.vi v0, v8, 03003; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma3004; CHECK-NEXT:    vslideup.vx v0, v24, a03005; CHECK-NEXT:    ret3006  %vc = icmp eq <vscale x 16 x i64> %va, zeroinitializer3007  ret <vscale x 16 x i1> %vc3008}3009