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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+xsfvfbfexp16e \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+xsfvfbfexp16e \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 1 x bfloat> @intrinsic_sf_vfexp_v_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma11; CHECK-NEXT: sf.vfexp.v v8, v812; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16(15 <vscale x 1 x bfloat> poison,16 <vscale x 1 x bfloat> %0,17 iXLen %1)18 19 ret <vscale x 1 x bfloat> %a20}21 22define <vscale x 2 x bfloat> @intrinsic_sf_vfexp_v_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1) nounwind {23; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv2bf16:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma26; CHECK-NEXT: sf.vfexp.v v8, v827; CHECK-NEXT: ret28entry:29 %a = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16(30 <vscale x 2 x bfloat> poison,31 <vscale x 2 x bfloat> %0,32 iXLen %1)33 34 ret <vscale x 2 x bfloat> %a35}36 37define <vscale x 4 x bfloat> @intrinsic_sf_vfexp_v_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1) nounwind {38; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv4bf16:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma41; CHECK-NEXT: sf.vfexp.v v8, v842; CHECK-NEXT: ret43entry:44 %a = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16(45 <vscale x 4 x bfloat> poison,46 <vscale x 4 x bfloat> %0,47 iXLen %1)48 49 ret <vscale x 4 x bfloat> %a50}51 52define <vscale x 8 x bfloat> @intrinsic_sf_vfexp_v_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1) nounwind {53; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv8bf16:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma56; CHECK-NEXT: sf.vfexp.v v8, v857; CHECK-NEXT: ret58entry:59 %a = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16(60 <vscale x 8 x bfloat> poison,61 <vscale x 8 x bfloat> %0,62 iXLen %1)63 64 ret <vscale x 8 x bfloat> %a65}66 67define <vscale x 16 x bfloat> @intrinsic_sf_vfexp_v_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1) nounwind {68; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv16bf16:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma71; CHECK-NEXT: sf.vfexp.v v8, v872; CHECK-NEXT: ret73entry:74 %a = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16(75 <vscale x 16 x bfloat> poison,76 <vscale x 16 x bfloat> %0,77 iXLen %1)78 79 ret <vscale x 16 x bfloat> %a80}81 82define <vscale x 32 x bfloat> @intrinsic_sf_vfexp_v_nxv32bf16(<vscale x 32 x bfloat> %0, iXLen %1) nounwind {83; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv32bf16:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma86; CHECK-NEXT: sf.vfexp.v v8, v887; CHECK-NEXT: ret88entry:89 %a = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16(90 <vscale x 32 x bfloat> poison,91 <vscale x 32 x bfloat> %0,92 iXLen %1)93 94 ret <vscale x 32 x bfloat> %a95}96 97define <vscale x 1 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %m, iXLen %2) nounwind {98; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv1bf16:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, mu101; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t102; CHECK-NEXT: ret103entry:104 %a = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16(105 <vscale x 1 x bfloat> %0,106 <vscale x 1 x bfloat> %1,107 <vscale x 1 x i1> %m,108 iXLen %2, iXLen 0)109 110 ret <vscale x 1 x bfloat> %a111}112 113define <vscale x 2 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %m, iXLen %2) nounwind {114; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv2bf16:115; CHECK: # %bb.0: # %entry116; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, mu117; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t118; CHECK-NEXT: ret119entry:120 %a = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16(121 <vscale x 2 x bfloat> %0,122 <vscale x 2 x bfloat> %1,123 <vscale x 2 x i1> %m,124 iXLen %2, iXLen 0)125 126 ret <vscale x 2 x bfloat> %a127}128 129define <vscale x 4 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %m, iXLen %2) nounwind {130; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv4bf16:131; CHECK: # %bb.0: # %entry132; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, mu133; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t134; CHECK-NEXT: ret135entry:136 %a = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16(137 <vscale x 4 x bfloat> %0,138 <vscale x 4 x bfloat> %1,139 <vscale x 4 x i1> %m,140 iXLen %2, iXLen 0)141 142 ret <vscale x 4 x bfloat> %a143}144 145define <vscale x 8 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %m, iXLen %2) nounwind {146; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv8bf16:147; CHECK: # %bb.0: # %entry148; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, mu149; CHECK-NEXT: sf.vfexp.v v8, v10, v0.t150; CHECK-NEXT: ret151entry:152 %a = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16(153 <vscale x 8 x bfloat> %0,154 <vscale x 8 x bfloat> %1,155 <vscale x 8 x i1> %m,156 iXLen %2, iXLen 0)157 158 ret <vscale x 8 x bfloat> %a159}160 161define <vscale x 16 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %m, iXLen %2) nounwind {162; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv16bf16:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, mu165; CHECK-NEXT: sf.vfexp.v v8, v12, v0.t166; CHECK-NEXT: ret167entry:168 %a = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv16bf16(169 <vscale x 16 x bfloat> %0,170 <vscale x 16 x bfloat> %1,171 <vscale x 16 x i1> %m,172 iXLen %2, iXLen 0)173 174 ret <vscale x 16 x bfloat> %a175}176 177define <vscale x 32 x bfloat> @intrinsic_sf_vfexp_mask_v_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %m, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv32bf16:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, tu, mu181; CHECK-NEXT: sf.vfexp.v v8, v16, v0.t182; CHECK-NEXT: ret183entry:184 %a = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv32bf16(185 <vscale x 32 x bfloat> %0,186 <vscale x 32 x bfloat> %1,187 <vscale x 32 x i1> %m,188 iXLen %2, iXLen 0)189 190 ret <vscale x 32 x bfloat> %a191}192