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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvfexp32e \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvfexp32e \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 1 x float> @intrinsic_sf_vfexp_v_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv1f32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma11; CHECK-NEXT: sf.vfexp.v v8, v812; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32(15 <vscale x 1 x float> poison,16 <vscale x 1 x float> %0,17 iXLen %1)18 19 ret <vscale x 1 x float> %a20}21 22define <vscale x 2 x float> @intrinsic_sf_vfexp_v_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {23; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv2f32:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma26; CHECK-NEXT: sf.vfexp.v v8, v827; CHECK-NEXT: ret28entry:29 %a = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32(30 <vscale x 2 x float> poison,31 <vscale x 2 x float> %0,32 iXLen %1)33 34 ret <vscale x 2 x float> %a35}36 37define <vscale x 4 x float> @intrinsic_sf_vfexp_v_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {38; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv4f32:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma41; CHECK-NEXT: sf.vfexp.v v8, v842; CHECK-NEXT: ret43entry:44 %a = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32(45 <vscale x 4 x float> poison,46 <vscale x 4 x float> %0,47 iXLen %1)48 49 ret <vscale x 4 x float> %a50}51 52define <vscale x 8 x float> @intrinsic_sf_vfexp_v_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {53; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv8f32:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma56; CHECK-NEXT: sf.vfexp.v v8, v857; CHECK-NEXT: ret58entry:59 %a = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32(60 <vscale x 8 x float> poison,61 <vscale x 8 x float> %0,62 iXLen %1)63 64 ret <vscale x 8 x float> %a65}66 67define <vscale x 16 x float> @intrinsic_sf_vfexp_v_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {68; CHECK-LABEL: intrinsic_sf_vfexp_v_nxv16f32:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma71; CHECK-NEXT: sf.vfexp.v v8, v872; CHECK-NEXT: ret73entry:74 %a = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32(75 <vscale x 16 x float> poison,76 <vscale x 16 x float> %0,77 iXLen %1)78 79 ret <vscale x 16 x float> %a80}81 82define <vscale x 1 x float> @intrinsic_sf_vfexp_mask_v_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %m, iXLen %2) nounwind {83; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv1f32:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu86; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t87; CHECK-NEXT: ret88entry:89 %a = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32(90 <vscale x 1 x float> %0,91 <vscale x 1 x float> %1,92 <vscale x 1 x i1> %m,93 iXLen %2, iXLen 0)94 95 ret <vscale x 1 x float> %a96}97 98define <vscale x 2 x float> @intrinsic_sf_vfexp_mask_v_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %m, iXLen %2) nounwind {99; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv2f32:100; CHECK: # %bb.0: # %entry101; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu102; CHECK-NEXT: sf.vfexp.v v8, v9, v0.t103; CHECK-NEXT: ret104entry:105 %a = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32(106 <vscale x 2 x float> %0,107 <vscale x 2 x float> %1,108 <vscale x 2 x i1> %m,109 iXLen %2, iXLen 0)110 111 ret <vscale x 2 x float> %a112}113 114define <vscale x 4 x float> @intrinsic_sf_vfexp_mask_v_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %m, iXLen %2) nounwind {115; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv4f32:116; CHECK: # %bb.0: # %entry117; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu118; CHECK-NEXT: sf.vfexp.v v8, v10, v0.t119; CHECK-NEXT: ret120entry:121 %a = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32(122 <vscale x 4 x float> %0,123 <vscale x 4 x float> %1,124 <vscale x 4 x i1> %m,125 iXLen %2, iXLen 0)126 127 ret <vscale x 4 x float> %a128}129 130define <vscale x 8 x float> @intrinsic_sf_vfexp_mask_v_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %m, iXLen %2) nounwind {131; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv8f32:132; CHECK: # %bb.0: # %entry133; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu134; CHECK-NEXT: sf.vfexp.v v8, v12, v0.t135; CHECK-NEXT: ret136entry:137 %a = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32(138 <vscale x 8 x float> %0,139 <vscale x 8 x float> %1,140 <vscale x 8 x i1> %m,141 iXLen %2, iXLen 0)142 143 ret <vscale x 8 x float> %a144}145 146define <vscale x 16 x float> @intrinsic_sf_vfexp_mask_v_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %m, iXLen %2) nounwind {147; CHECK-LABEL: intrinsic_sf_vfexp_mask_v_nxv16f32:148; CHECK: # %bb.0: # %entry149; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu150; CHECK-NEXT: sf.vfexp.v v8, v16, v0.t151; CHECK-NEXT: ret152entry:153 %a = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32(154 <vscale x 16 x float> %0,155 <vscale x 16 x float> %1,156 <vscale x 16 x i1> %m,157 iXLen %2, iXLen 0)158 159 ret <vscale x 16 x float> %a160}161